WO2015188476A1 - 薄膜晶体管及其制作方法、oled背板和显示装置 - Google Patents

薄膜晶体管及其制作方法、oled背板和显示装置 Download PDF

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WO2015188476A1
WO2015188476A1 PCT/CN2014/086079 CN2014086079W WO2015188476A1 WO 2015188476 A1 WO2015188476 A1 WO 2015188476A1 CN 2014086079 W CN2014086079 W CN 2014086079W WO 2015188476 A1 WO2015188476 A1 WO 2015188476A1
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layer
thin film
substrate
gate electrode
film transistor
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PCT/CN2014/086079
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English (en)
French (fr)
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王灿
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京东方科技集团股份有限公司
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Priority to US14/435,825 priority Critical patent/US20160181290A1/en
Publication of WO2015188476A1 publication Critical patent/WO2015188476A1/zh

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Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an OLED backplane, and a display device.
  • a thin film transistor is a field effect transistor and is widely used.
  • a thin film transistor is mainly used to form a driving circuit for controlling the loading of a display signal on an independent pixel.
  • the thin film transistor mainly includes an active layer, a gate electrode, a gate insulating layer, a source electrode, and a drain electrode.
  • an aluminum film (a metal aluminum or aluminum alloy film, hereinafter collectively referred to as an aluminum film) is generally deposited on a substrate to form a gate electrode; and then a PECVD (Plasma Enhanced Chemical Vapor Deposition) is used on the gate electrode.
  • PECVD Plasma enhanced chemical vapor deposition method deposits silicon oxide as a gate insulating layer.
  • the surface is prone to hillocks and becomes uneven, which affects the matching between the gate insulating layer and the subsequently formed active layer, resulting in a film.
  • the performance of the transistor is affected.
  • Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, an OLED backplane, and a display device. According to the embodiment of the invention, the generation of hillocks on the surface of the aluminum film can be effectively reduced, the stability of the performance of the active layer can be improved, and the power consumption of the product can be reduced, and the market competitiveness of the product can be improved.
  • an embodiment of the present invention provides a thin film transistor including: a substrate, and a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode sequentially formed over the substrate.
  • the gate electrode is formed between the substrate and the gate insulating layer.
  • the thin film transistor further includes: a first transition layer disposed on the substrate and located between the gate electrode and the substrate, a thermal expansion coefficient of a material of the first transition layer being thermal expansion of a material of the substrate a coefficient between a coefficient of thermal expansion of a material of the gate electrode; and a temperature at which the gate insulating layer is formed is lower than a first limit temperature, the first limit temperature indicating that a film layer of the gate electrode is subjected to compressive stress without The temperature corresponding to the limit value of the deformation.
  • the gate electrode is formed of aluminum and the first extreme temperature is 150 °C.
  • the substrate is a glass substrate and the material of the first transition layer is alumina.
  • the first transition layer has a thickness of 50 to 200 nm.
  • the material of the active layer is an oxide semiconductor material.
  • the material of the gate insulating layer is aluminum oxide.
  • a second transition layer is further disposed between the active layer and the gate insulating layer, and the material of the second transition layer is a high oxygen oxide of the active layer forming material.
  • the mass percentage of oxygen in the high oxygen oxide is from 50% to 80%.
  • the present invention also provides an OLED backplane comprising the above-described thin film transistor.
  • the present invention also provides a display device comprising the above-described thin film transistor, or the above OLED backplane.
  • the present invention also provides a method of fabricating a thin film transistor, comprising:
  • first transition layer material having a thermal expansion coefficient between a thermal expansion coefficient of a material of the substrate and a thermal expansion coefficient of a material of the gate electrode;
  • An active layer, a source electrode, and a drain electrode are sequentially formed on the gate insulating layer.
  • the forming a gate metal layer pattern including the gate electrode specifically: forming an aluminum thin film on the first transition layer, and forming a gate metal layer pattern including a gate electrode by a patterning process;
  • the first limit temperature is 150 °C.
  • the substrate is a glass substrate
  • the first transition layer is formed of aluminum oxide
  • the forming the first transition layer on the substrate is: forming an aluminum oxide film on the substrate by a sputtering method; forming the aluminum thin film on the first transition layer: using a sputtering method An aluminum film is formed on the aluminum oxide film.
  • the forming material of the active layer is an oxide semiconductor material; before the forming of the active layer, the fabricating method further includes: forming a second transition layer on the gate insulating layer, the second The material of the transition layer is a high oxygen oxide of the active layer forming material.
  • the OLED back sheet and the display device provided between the gate electrode and the substrate, a thermal expansion coefficient is set between the thermal expansion coefficient of the material of the substrate and the thermal expansion coefficient of the material of the gate electrode. a first transition layer; and, changing a material or a film formation manner of the gate insulating layer such that a film forming temperature of the material of the gate insulating layer is lower than a compressive stress of the inside of the gate electrode material Limit value (if the gate electrode forming material is an aluminum film, the temperature corresponding to the limit value is between 100 and 150 ° C, and the specific value can be determined by experiments in advance), which can effectively reduce the high temperature process formed in the gate insulating layer.
  • the stress in the gate electrode 12 caused by the difference in thermal expansion coefficient between the substrate 10 and the film layer of the gate electrode 12, thereby reducing the generation of hillocks to a certain extent, improving the stability of the performance of the active layer, and reducing the power consumption of the product. Improve product market competitiveness.
  • FIG. 1 is a schematic structural view of a thin film transistor according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural diagram of a thin film transistor according to Embodiment 2 of the present invention.
  • FIG. 3 is a flow chart of a method for fabricating a thin film transistor according to Embodiment 3 of the present invention.
  • FIG. 4 is a schematic structural diagram of an IPS array substrate according to Embodiment 4 of the present invention.
  • Embodiments of the present invention provide a thin film transistor, a method for fabricating the same, an OLED backplane, and a display device, which can effectively reduce the generation of hillocks on the surface of the aluminum film, improve the stability of the performance of the active layer, and reduce Product power consumption, improve product market competitiveness.
  • the gate electrode is formed by etching after depositing an aluminum film (metal aluminum or aluminum alloy) on the substrate; then, above the gate electrode, silicon oxide (or silicon nitride) is deposited by PECVD.
  • PECVD film forming temperature is relatively high (generally greater than 300 ° C), and the aluminum film used to form the gate electrode can easily cause hillock problems on the surface of the aluminum film through the high temperature process.
  • the inventors have carefully studied and found out that the hillocks are produced as follows.
  • the thermal expansion coefficient of the substrate generally a glass substrate
  • the thermal expansion coefficient of the aluminum film as the gate electrode thermal expansion of the aluminum film on the side adjacent to the substrate is limited in the high temperature process.
  • the elastic deformation of the aluminum film increases.
  • the compressive stress inside the aluminum film can reach the limit, at which time it will release the compressive stress by means of atomic diffusion. A hillock is formed on the surface of the film.
  • Embodiment 1 of the present invention provides a thin film transistor.
  • the thin film transistor includes a substrate 10 and a gate electrode 12, a gate insulating layer 13, an active layer 14, a source electrode 15, and a drain electrode 16 which are sequentially formed over the substrate 10.
  • a gate electrode 12 is formed over the substrate 10, and a gate insulating layer 13 is formed between the gate electrode 12 and the substrate 10.
  • the thin film transistor of this embodiment further includes a first transition layer 11 disposed on the substrate 10 and located between the gate electrode 12 and the substrate 10.
  • the coefficient of thermal expansion of the material of the first transition layer 11 is between the coefficient of thermal expansion of the material of the substrate 10 and the coefficient of thermal expansion of the material of the gate electrode 12; and the film formation temperature of the material of the gate insulating layer 13 is lower than the first of the gate electrode 12.
  • Limit temperature refers to a temperature corresponding to a limit value at which the film layer of the gate electrode 12 is subjected to compressive stress without deformation. When the temperature with which the gate electrode 12 is subjected exceeds the first limit temperature, the film layer of the gate electrode 12 will release the compressive stress by atom diffusion, forming a hillock on the film surface of the gate electrode 12.
  • a first transition layer having a thermal expansion coefficient between a thermal expansion coefficient of the substrate and a thermal expansion coefficient of the gate electrode is disposed between the gate electrode and the substrate, and a film formation temperature of the gate insulating layer is decreased. Therefore, the stress in the gate electrode caused by the difference in thermal expansion coefficient between the substrate and the gate electrode layer in the high-temperature process formed by the gate insulating layer is effectively reduced, thereby reducing the generation of hillocks and improving the performance of the active layer to a certain extent.
  • the stability, and reduce the power consumption of the product improve the competitiveness of the product market.
  • the material of the gate electrode 12 in the above embodiment is generally an alloy of aluminum metal or aluminum, and may be other metal or alloy materials.
  • the substrate 10 is typically a glass substrate.
  • the coefficient of thermal expansion of the material is: glass ⁇ oxide ⁇ metal ⁇ high polymer. Therefore, the first transition layer 11 is generally formed of an oxide having a coefficient of thermal expansion between the glass and the metal.
  • the material of the substrate 10 is quartz glass
  • the material of the gate electrode 12 is pure metal aluminum material
  • the material of the first transition layer 11 is aluminum oxide
  • the thickness of the first excess layer is 50-200 nm.
  • the thermal expansion coefficient of aluminum is 23.6x10 -6 /K
  • the thermal expansion coefficient of quartz glass is 0.57 ⁇ 10 -6 /K
  • the thermal expansion coefficient of alumina is 8.8 ⁇ 10 -6 /K.
  • the first extreme temperature is between 100 and 150 °C.
  • the specific value of the first limit temperature corresponding to the material of the gate electrode 12 can be determined experimentally or theoretically based on the material of the gate electrode 12.
  • the material of the active layer 14 is, for example, an oxide semiconductor including zinc oxide ZnO, IGZO, IZO, ZTO, or the like.
  • the above oxide thin film transistor using an oxide semiconductor as an active layer material is simpler than a low temperature polysilicon (LTPS) thin film transistor, the fabrication cost is low, and the film layer is mostly formed into an amorphous structure, and has an excellent large area uniformity. sexually, it is very suitable for high-resolution active matrix OLED (AMOLED), flexible display and other new display requirements, especially for the production line of the big generation.
  • the process of the oxide thin film transistor is compatible with the process of the amorphous silicon thin film transistor (a-Si TFT), so that it can be fabricated on the original a-Si TFT production line through technical modification, which can greatly save equipment investment. reduce manufacturing cost.
  • the threshold voltage Vth shift phenomenon in the current-voltage characteristics (IV characteristics) occurs during long-term use of an oxide semiconductor device at a high temperature or a low temperature.
  • IV characteristics current-voltage characteristics
  • the active layer of the oxide semiconductor is in direct contact with the material of the gate insulating layer, and there is a mismatch in performance, so that the oxide semiconductor trap state problem is easily amplified, causing charge accumulation, resulting in drift of the IV characteristic.
  • aluminum oxide having a band gap width of 8.9 ev is selected as the gate insulating layer 13, so that carriers in the active layer 14 do not easily pass the barrier into the gate insulating layer 13, thereby avoiding the active layer 14. Unstable. This achieves good contact between the gate insulating layer 13 and the oxide semiconductor as the active layer 14, reduces interface defects between the gate insulating layer 13 and the active layer 14, and improves carriers in the active layer 14. Mobility.
  • the selection of the material of the gate insulating layer 13 is considered in addition to the compatibility with the oxide semiconductor, and the formation of the hillock in the film layer of the gate electrode during the formation of the gate insulating layer 13, the gate insulating layer 13 is also considered.
  • the dielectric constant K is also considered.
  • Conventional gate insulating layer materials generally use SiO 2 .
  • the PECVD film forming temperature of SiO 2 is relatively high (>300 ° C), which easily causes the problem of hillocks in the pure aluminum film as the gate electrode.
  • the dielectric constant of SiO 2 is low (the dielectric of SiO2)
  • the constant k ⁇ 3.9 when formed as a gate insulating layer, the TFT has a low permittivity and a high operating voltage, resulting in a large power consumption of the device. In the era of today's smartphone development, low power consumption is an important factor that must be considered due to battery capacity limitations.
  • One way to reduce power consumption is to select a high-k gate insulating material to reduce the driving voltage, such as high-k materials such as Al 2 O 3 , Y 2 O 3 , BaSrTiO, Ta 2 O 5 .
  • the gate insulating layer 13 forming material is preferably alumina (Al 2 O 3 ).
  • alumina has a high dielectric constant (k ⁇ 8.7), can achieve low operating voltage, high output current, and has good insulation properties, so that TFT devices have a very low leakage current; on the other hand, alumina
  • a band gap width of 8.9 eV can be achieved, and carriers of the active layer 14 do not easily cross the barrier into the gate insulating layer 13 to avoid instability of the active layer 14, thereby realizing an oxide semiconductor with the active layer 14.
  • Good contact reduces interface defects between the gate insulating layer 13 and the active layer 14 and improves carrier mobility.
  • the aluminum oxide film can be prepared by a sputtering method, and the film formation temperature is low, and the generation of hillocks in the gate electrode film layer can be avoided. Moreover, the process is simple, the cost is low, and no additional investment is required.
  • FIG. 2 is a schematic structural diagram of a thin film transistor according to Embodiment 2 of the present invention.
  • the thin film transistor of the embodiment further includes A second transition layer 141 is disposed between the active layer 14 and the gate insulating layer 13.
  • the material of the second transition layer 141 is a high oxygen oxide of the material of the active layer 14.
  • the deposition of the high oxy oxide film is performed before the active layer is formed by depositing an oxide semiconductor, and the mass percentage of the oxygen content of the high oxy oxide is about 50% to 80%.
  • the film is basically an insulating film, which can serve as a transition layer between the gate insulating layer and the oxide semiconductor material, effectively improving the interface matching between the gate insulating layer and the oxide active layer.
  • the thin film transistor provided by the invention can effectively suppress the generation of hillocks on the surface of the aluminum film, improve the stability of the performance of the active layer, reduce the power consumption of the product, and improve the competitiveness of the product market.
  • Embodiments of the present invention also provide an OLED backplane including the above-described thin film transistor.
  • the OLED backplane provided in this embodiment improves the stability of the active layer performance, can weaken the threshold voltage Vth offset phenomenon to a certain extent, and reduces the power consumption of the product.
  • the embodiment of the invention further provides a display device comprising the above-mentioned thin film transistor or the above OLED backplane.
  • the stability of the active layer performance of the display device provided by the embodiment is improved, the threshold voltage Vth offset phenomenon can be weakened to a certain extent, and the display effect is improved, and the display device has a small driving voltage and saves energy.
  • the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • an embodiment of the present invention further provides a method for fabricating a thin film transistor. As shown in FIG. 3, the manufacturing method includes the following steps:
  • the thermal expansion coefficient of the material of the first transition layer 11 is between the thermal expansion coefficient of the material of the substrate 10 and the thermal expansion coefficient of the material of the gate electrode 12;
  • the active layer 14, the source electrode 15, and the drain electrode 16 are sequentially formed on the gate insulating layer 13.
  • a first transition layer having a thermal expansion coefficient between a thermal expansion coefficient of a substrate material and a thermal expansion coefficient of a gate electrode material is first deposited on the substrate, and a material or a film formation manner of the gate insulating layer is changed.
  • the film forming temperature of the gate insulating layer material is lower than the first limit temperature corresponding to the limit value of the compressive stress received inside the gate electrode material, thereby effectively reducing the generation of hillocks on the surface of the gate electrode film layer and improving the active layer. Performance stability, and reduce product power consumption, improve product market competitiveness.
  • the step 102 of forming a gate metal layer pattern including the gate electrode 12 includes, for example, forming an aluminum thin film on the first transition layer 11, and forming a gate metal layer pattern including the gate electrode 12 by a patterning process.
  • the material of the gate electrode 12 is aluminum, and the corresponding first limit temperature is 150 °C.
  • the substrate 10 in this embodiment is, for example, a glass substrate, and the material of the first transition layer 11 is, for example, alumina.
  • the step 101 of forming the first transition layer 11 on the substrate 10 includes, for example, forming an aluminum oxide film on the substrate 10 by a sputtering method.
  • Step 102 includes, for example, forming an aluminum thin film on the aluminum oxide film by a sputtering method.
  • the aluminum oxide film can be prepared by a sputtering method, and the film formation temperature is low, which can avoid the generation of hillocks on the surface of the film of the gate electrode, that is, the surface of the aluminum film, and the process is simple, the cost is low, and no additional investment is required.
  • the material of the active layer 14 is, for example, an oxide semiconductor material.
  • the fabrication method according to an embodiment of the present invention further includes: forming a second transition layer 141 on the gate insulating layer 13, The material of the second transition layer 141 is a high oxygen oxide of the active layer 14 forming material.
  • deposition of a high oxy oxide film is performed directly in the same chamber under an oxygen-rich atmosphere. Then, the atmosphere in the chamber is changed, and deposition of the oxide semiconductor film layer of the active layer is performed.
  • the high oxygen oxide film has a mass percentage of oxygen of about 50% to 80%, and the film is basically an insulating film, which can serve as a transition layer between the gate insulating layer and the oxide semiconductor material, thereby effectively improving the gate insulating layer and Interface matching of the oxide active layer.
  • Step 1 an aluminum oxide film as the first transition layer 11 is formed on the substrate 10.
  • Oxygen gas (about 5%) was introduced into the sputtering pure aluminum chamber, and pure aluminum reactive sputtering was performed, and the sputtering thickness was 50-200 angstroms.
  • the film layer serves as the first transition layer 11, and the first transition layer 11 does not need to be patterned.
  • Step 2 directly sputtering the pure aluminum gate electrode 12 in the sputtering pure aluminum chamber (temperature selection 100-150 ° C), no oxygen is introduced into the sputtering chamber, and vacuum is again applied to avoid oxidation of pure aluminum. Patterning is then performed using a conventional method to etch a gate electrode pattern including the gate electrode 12.
  • Step 3 sputtering of an aluminum oxide film as the gate insulating layer 13 is performed at a low temperature.
  • Argon Ar and oxygen O 2 were introduced into the sputtering pure aluminum chamber, and the oxygen concentration was about 5%.
  • the aluminum oxide film was sputter-deposited to a thickness of about 1000 to 2000 angstroms. Thereafter, the etching process of the gate insulating layer 13 is performed using an etching solution.
  • Step 4 depositing an oxide semiconductor to form an active layer 14, the oxide semiconductor material may be IGZO, IZO, ZnO, ZTO or the like.
  • Step 5 forming an etch barrier layer 17, a source/drain metal layer including the source/drain 15/16, and a passivation layer 18 in sequence using a conventional method.
  • Step 1 an aluminum oxide film as the first transition layer 11 is formed on the substrate 10.
  • Oxygen gas (about 5%) was introduced into the sputtering pure aluminum chamber, and pure aluminum reactive sputtering was performed, and the sputtering thickness was 50-200 angstroms.
  • the film layer serves as the first transition layer 11, and the first transition layer 11 does not need to be patterned.
  • Step 2 directly sputtering the pure aluminum gate electrode 12 in the sputtering pure aluminum chamber (temperature selection 100-150 ° C), no oxygen is introduced into the sputtering chamber, and vacuum is again applied to avoid oxidation of pure aluminum. Patterning is then performed using a conventional method to etch a gate electrode pattern including the gate electrode 12.
  • Step 3 sputtering of an aluminum oxide film as the gate insulating layer 13 is performed at a low temperature. Ar and oxygen were introduced into the sputtered pure aluminum chamber, and the oxygen concentration was about 5%. The aluminum oxide film was sputter-deposited to a thickness of about 1000 to 2000 angstroms. Thereafter, the etching process of the gate insulating layer 13 is performed using an etching solution.
  • Step 4 Depositing an oxide semiconductor to form an active layer
  • the oxide semiconductor material may be IGZO, IZO, ZnO, ZTO or the like.
  • deposition of a high-oxygen oxide film is first performed, and then deposition of an oxide semiconductor thin film as the active layer 14 is directly performed in situ.
  • the high-oxygen oxide film has an oxygen content of about 50% to 80%, and the high-oxygen oxide film is basically an insulating film, which can be used as a transition layer between the gate insulating layer material and the oxide semiconductor material, and can be effective. The interface contact between the gate insulating layer and the oxide active layer is improved.
  • Step 5 forming an etch barrier layer 17, a source/drain metal layer including the source/drain 15/16, and a passivation layer 18 in sequence using a conventional method.
  • Step 1 as shown in FIG. 4, an aluminum oxide film as the first transition layer 11 is formed on the substrate 10, and oxygen (about 5%) is introduced into the sputtering pure aluminum chamber to perform pure aluminum reactive sputtering and sputtering.
  • the thickness is between 50 and 200 angstroms.
  • the film layer serves as the first transition layer 11, and the first transition layer 11 does not need to be patterned.
  • Step 2 directly sputtering the pure aluminum gate electrode 12 in the sputtering pure aluminum chamber (temperature selection 100-150 ° C), no oxygen is introduced into the sputtering chamber, and vacuum is again applied to avoid oxidation of pure aluminum. Patterning is then performed using a conventional method to etch a gate metal layer pattern including the gate electrode 12.
  • Step 3 sputtering of an aluminum oxide film as the gate insulating layer 13 is performed at a low temperature. Ar and oxygen were introduced into the sputtered pure aluminum chamber, and the oxygen concentration was about 5%. The aluminum oxide film was sputter-deposited to a thickness of about 1000 to 2000 angstroms. The gate insulating layer 13 is then patterned using an etching solution.
  • Step 4 depositing an oxide semiconductor to form an active layer 14, the oxide semiconductor material may be IGZO, IZO, ZnO, ZTO or the like.
  • Step 5 forming an etch barrier 17, an source/drain metal layer (including the source electrode 15 and the drain electrode 16), and a first transparent conductive layer in the structure of an IPS (In-Plane Switching) in-plane switching liquid crystal display device using a conventional method. 19.
  • Embodiment 4 is basically the same as Embodiment 3 except that in Embodiment 4, deposition of a high oxygen oxide thin film is first performed, and then deposition of an oxide semiconductor thin film as the active layer 14 is directly performed in situ.
  • the above high-oxygen oxide film has an oxygen content of about 50% to 80%, and the high-oxygen oxide film is basically an insulating film which can be used as a gate insulating layer material between the oxide semiconductor materials. The transition layer can effectively improve the interface contact between the gate insulating layer and the oxide active layer.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor, which can effectively reduce the generation of hillocks on the surface of the gate electrode film layer, improve the stability of the performance of the active layer, and reduce the power consumption of the product and improve the market competitiveness of the product.

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Abstract

一种薄膜晶体管及其制作方法、OLED背板和显示装置，能够有效减少铝膜表面小丘的产生，提高有源层性能的稳定性，并且降低产品的功耗。该薄膜晶体管包括：基板（10）和依次形成于基板（10）上方的栅电极（12）、栅绝缘层（13）、有源层（14）、源电极（15）和漏电极（16）。栅电极（12）形成于基板（10）和栅绝缘层（13）之间。薄膜晶体管还包括设置于基板（10）上且位于栅电极（12）和基板（10）之间的第一过渡层（11），第一过渡层（11）的材料的热膨胀系数介于基板和栅电极的材料的热膨胀系数之间，形成栅绝缘层的温度低于第一极限温度，第一极限温度指栅电极（12）的膜层受压缩应力而不形变的极限值对应的温度。

Description

薄膜晶体管及其制作方法、OLED背板和显示装置 技术领域
本发明实施例涉及一种薄膜晶体管及其制作方法、OLED背板和显示装置。
背景技术
薄膜晶体管是一种场效应晶体管，应用广泛。在显示领域，如OLED(Organic Light Emitting Diode，有机发光二极管)中，薄膜晶体管主要用于形成驱动电路，控制一个独立像素上显示信号的加载。
薄膜晶体管主要包括：有源层、栅电极、栅绝缘层、源电极和漏电极。目前，在OLED中，一般先在基板上沉积一层铝膜(金属铝或者铝合金薄膜，本文以下统称铝膜)用以形成栅电极；然后栅电极之上，使用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)方法沉积氧化硅作为栅绝缘层。但形成栅电极的铝膜再经该栅绝缘层沉积工序后，表面容易出现小丘(hillock)，变得不平整，影响栅绝缘层与后续形成的有源层之间的匹配性，导致薄膜晶体管的性能受到影响。
发明内容
本发明实施例提供一种薄膜晶体管及其制作方法、OLED背板和显示装置。根据本发明实施例，能够有效减少铝膜表面上小丘的产生，提高有源层性能的稳定性，并且降低产品的功耗，提高产品市场竞争力。
一方面，本发明的实施例提供一种薄膜晶体管，包括：基板，和依次形成于所述基板上方的栅电极、栅绝缘层、有源层、源电极和漏电极。所述栅电极形成于基板和所述栅绝缘层之间。薄膜晶体管还包括：设置于所述基板上，且位于所述栅电极和所述基板之间的第一过渡层，所述第一过渡层的材料的热膨胀系数介于所述基板的材料的热膨胀系数和所述栅电极的材料的热膨胀系数之间；且，形成所述栅绝缘层的温度低于第一极限温度，所述第一极限温度指所述栅电极的膜层受压缩应力而不形变的极限值对应的温度。
在一个示例中，所述栅电极的形成材料为铝，所述第一极限温度为150℃。
在一个示例中，所述基板为玻璃基板，所述第一过渡层的材料为氧化铝。
在一个示例中，所述第一过渡层的厚度为50～200nm。
在一个示例中，所述有源层的材料为氧化物半导体材料。
在一个示例中，所述栅绝缘层的材料为氧化铝。
进一步地，所述有源层和所述栅绝缘层之间还设置有第二过渡层，所述第二过渡层的材料为所述有源层形成材料的高氧氧化物。
在一个示例中，所述高氧氧化物中含氧量的质量百分比为50％～80％。
本发明还提供一种OLED背板，包括上述的薄膜晶体管。
本发明还提供一种显示装置，包括上述的薄膜晶体管，或者上述的OLED背板。
另一方面，本发明还提供一种薄膜晶体管的制作方法，包括：
在基板上形成第一过渡层，所述第一过渡层材料的热膨胀系数介于所述基板的材料的热膨胀系数和栅电极的材料的热膨胀系数之间；
在所述第一过渡层上形成包括栅电极的栅金属层图形；
在低于第一极限温度的条件下，在所述栅电极和所述第一过渡层上形成栅绝缘层；
在所述栅绝缘层上依次形成有源层、源电极和漏电极。
在一个示例中，所述形成包括所述栅电极在内的栅金属层图形，具体为：在所述第一过渡层上形成铝薄膜，并通过构图工艺形成包括栅电极的栅金属层图形；所述第一极限温度为150℃。
在一个示例中，所述基板为玻璃基板，所述第一过渡层的形成材料为氧化铝。
在一个示例中，所述在基板上形成第一过渡层为：采用溅射方法在基板上形成氧化铝薄膜；所述在所述第一过渡层上形成铝薄膜为：采用溅射方法在所述氧化铝薄膜上形成铝薄膜。
在一个示例中，所述有源层的形成材料为氧化物半导体材料；在形成有源层之前，所述制作方法还包括：在所述栅绝缘层上形成第二过渡层，所述第二过渡层的材料为所述有源层形成材料的高氧氧化物。
根据本发明实施例提供的薄膜晶体管及其制作方法、OLED背板和显示装置，在栅电极和基板之间设置热膨胀系数介于基板的材料的热膨胀系数和栅电极的材料的热膨胀系数之间的第一过渡层；且，改变栅绝缘层的材料或成膜方式以使栅绝缘层的材料的成膜温度低于栅电极材料内部承受的压缩应力的极 限值(栅电极形成材料如果为铝膜，则该极限值对应的温度在100～150℃之间，具体取值可以预先通过试验确定)，可以有效减小在栅绝缘层形成的高温工艺中由基板10与栅电极12的膜层的热膨胀系数差异导致的在栅电极12中的应力，从而在一定程度下减少小丘的产生，提高有源层性能的稳定性，并且降低产品的功耗，提高产品市场竞争力。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本发明实施例一提供的薄膜晶体管的的结构示意图；
图2为本发明实施例二提供的薄膜晶体管的结构示意图；
图3为本发明实施例三提供的薄膜晶体管的制作方法流程图；和
图4为本发明实施例四提供的IPS阵列基板的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本发明实施例提供一种薄膜晶体管及其制作方法、OLED背板和显示装置，能够有效减少铝膜表面小丘的产生，提高有源层性能的稳定性，并且降低 产品的功耗，提高产品市场竞争力。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
在薄膜晶体管的制作过程中，栅电极是在基板沉积一层铝膜(金属铝或铝合金)后通过刻蚀而形成；然后栅电极之上，使用PECVD方法沉积氧化硅(或氮化硅)作为栅绝缘层。本发明人发现：PECVD成膜温度较高(一般大于300℃)，而用以形成栅电极的铝膜再经该高温工艺，很容易造成铝膜的表面出现小丘问题。本发明人仔细研究后发现产生小丘的原因如下。由于基板(一般为玻璃基板)的热膨胀系数小于作为栅电极的铝膜的热膨胀系数，在高温工艺中，铝膜在与基板邻接的一侧的热膨胀受到限制。随温度的不断升高，铝膜的弹性形变增大。在第一极限温度下(对纯铝膜而言，大约在100～150℃之间)，铝膜内部所能承受的压缩应力达到极限，这时它将通过原子扩散的方式释放压缩应力，此时就会在薄膜表面就形成小丘。
本发明实施例一提供一种薄膜晶体管。如图1所示，该薄膜晶体管包括基板10和依次形成基板10上方的栅电极12、栅绝缘层13、有源层14、源电极15和漏电极16。栅电极12形成于基板10上方，栅绝缘层13形成于栅电极12和基板10之间。本实施例的薄膜晶体管还包括设置于基板10上且位于栅电极12和基板10之间的第一过渡层11。第一过渡层11的材料的热膨胀系数介于基板10的材料的热膨胀系数和栅电极12的材料的热膨胀系数之间；且，栅绝缘层13材料的成膜温度低于栅电极12的第一极限温度。如上所述，该第一极限温度指栅电极12的膜层受压缩应力而不形变的极限值对应的温度。当栅电极12承受的温度超过该第一极限温度，栅电极12的膜层将通过原子扩散的方式释放压缩应力，在栅电极12的薄膜表面形成小丘。
根据本发明实施例提供的薄膜晶体管，在栅电极和基板之间设置热膨胀系数介于基板的热膨胀系数和栅电极的热膨胀系数之间的第一过渡层，同时降低栅绝缘层的成膜温度，从而有效减小在栅绝缘层形成的高温工艺中由基板与栅电极的膜层的热膨胀系数差异导致的在栅电极中的应力，从而在一定程度下减少小丘的产生，提高有源层性能的稳定性，并且降低产品的功耗，提高产品市场竞争力。
上述实施例中栅电极12的材料目前一般为金属铝或者铝的合金，也可以是其他金属或合金材料。基板10一般为玻璃基板。材料的热膨胀系数规律为： 玻璃＜氧化物＜金属＜高聚物.因此第一过渡层11一般由热膨胀系数在玻璃和金属之间的氧化物形成。在一种具体实施方式中，基板10的材料为石英玻璃，栅电极12的材料为纯金属铝材料，第一过渡层11的材料为氧化铝，第一过度层的厚度为50～200nm。铝的热膨胀系数为23.6x10-6/K，石英玻璃的热膨胀系数为0.57×10-6/K；氧化铝的热膨胀系数为8.8x10-6/K。这可以有效减小在栅绝缘层形成的高温工艺中由基板10与栅电极12的膜层的热膨胀系数差异导致的在栅电极12中的应力，而且栅电极12的纯铝薄膜和第一过度层的氧化铝薄膜均可采用溅射方法在同一腔室内制备，中途无需更换制膜设备，工艺简单，成本低，不需额外的投入。
如果栅电极12的材料为纯铝，则第一极限温度在100～150℃之间。在本发明的实施例中，可以根据栅电极12的材料，通过实验或理论计算确定栅电极12的材料对应的第一极限温度的具体取值。
在该实施例中，有源层14的材料例如为氧化物半导体，所述氧化物半导体包括氧化锌ZnO、IGZO、IZO、ZTO等。
由于上述的将氧化物半导体作为有源层材料的氧化物薄膜晶体管比低温多晶硅(LTPS)薄膜晶体管的制作工艺简单，制作成本低，并且膜层大多形成为非晶结构，具有优异的大面积均匀性，非常适合高分辨的有源矩阵OLED(AMOLED)、柔性显示器等新型显示器的需求，尤其适用于大世代的产线。而且氧化物薄膜晶体管的制程与非晶硅薄膜晶体管(a-Si TFT)制程的兼容性好，因此可以在通过技术改造的原有a-Si TFT生产线上进行制作，可以大幅度节约设备投资，降低生产成本。但随着氧化物薄膜晶体管量产投入使用，有源层稳定性的问题越来越突出。氧化物半导体器件在高温或低温长期使用过程中出现电流电压特性(IV特性)中的阈值电压Vth偏移现象。目前最有可能的原因是氧化物半导体有源层与栅绝缘层材料直接接触，在性能上存在不匹配，因此易造成氧化物半导体陷阱态问题放大，引起电荷的聚集，导致IV特性的漂移。为解决这一问题，选择合适的栅绝缘层13以及改善栅绝缘层13和有源层14的界面接触就显得尤为重要。本实施例中选择带隙宽度能达到8.9ev的氧化铝作为栅绝缘层13，可使有源层14中的载流子不容易越过该势垒进入栅绝缘层13，避免造成有源层14不稳定。这实现了栅绝缘层13与作为有源层14的氧化物半导体的之间良好的接触，减少栅绝缘层13和有源层14之间的界面缺陷，提高有源层14中的载流子迁移率。
另外，栅绝缘层13材料的选择除考虑与氧化物半导体界面匹配性，以及在栅绝缘层13的形成过程中避免在栅电极的膜层中产生小丘之外，还需考虑栅绝缘层13的介电常数K。
常规的栅绝缘层材料一般使用SiO2。但一方面SiO2的PECVD成膜温度较高(＞300℃)，很容易造成在作为栅电极的纯铝薄膜中产生小丘的问题另一方面SiO2的介电常数低(SiO2的介电常数k≈3.9)，在作为栅极绝缘层时所形成的TFT电容率较低，工作电压较高，造成器件的功耗较大。在现今智能机发展的时代，由于受到电池容量的限制，低功耗是必须考虑的重要因素。降低功耗的其中一个途径就是选择高k值的栅极绝缘层材料来降低驱动电压，如像Al2O3、Y2O3、BaSrTiO、Ta2O5等高k值的材料。
在本实施例中栅绝缘层13形成材料优选为氧化铝(Al2O3)。一方面氧化铝具有较高的介电常数(k≈8.7)，能实现低工作电压、高输出电流，并且有良好的绝缘特性，使TFT器件有很低的泄露电流；另一方面，氧化铝同时能达到8.9eV的带隙宽度，有源层14的载流子不容易越过势垒进入栅绝缘层13，避免造成有源层14不稳定，从而实现与有源层14的氧化物半导体的良好接触，减少栅绝缘层13和有源层14之间的界面缺陷，提高载流子迁移率。同时，氧化铝薄膜可采用溅射方法制备，成膜温度低，可以避免栅电极膜层中小丘的产生。而且工艺简单，成本低，不需额外的投入。
图2为本发明实施例二提供的薄膜晶体管的结构示意图。如图2所示，为进一步地有效改善栅绝缘层与氧化物半导体有源层的界面接触，降低氧化物半导体有源层与栅绝缘层在性能的不匹配，本实施例的薄膜晶体管还包括在有源层14和栅绝缘层13之间设置的第二过渡层141。第二过渡层141的材料为有源层14材料的高氧氧化物。在一个示例中，在通过沉积氧化物半导体形成有源层之前，进行高氧氧化物薄膜的沉积，高氧氧化物的氧含量的质量百分比约为50％-80％。该薄膜基本为绝缘性薄膜，其可作为栅绝缘层到氧化物半导体材料之间的过渡层，有效的改善栅绝缘层与氧化物有源层的界面匹配。
本发明提供的薄膜晶体管，能够有效抑制铝膜表面小丘的产生，提高有源层性能的稳定性，并且降低产品的功耗，提高产品市场竞争力。
本发明实施例还提供一种OLED背板，其包括上述的薄膜晶体管。本实施例提供的OLED背板，有源层性能的稳定性提升，能在一定程度上消弱阈值电压Vth偏移现象，降低产品的功耗。
本发明实施例还提供一种显示装置，其包括上述的薄膜晶体管，或者上述的OLED背板。本实施例提供的显示装置有源层性能的稳定性提升，能在一定程度上消弱阈值电压Vth偏移现象，提高显示效果，同时所述显示装置驱动电压小，节能省电。所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
另一方面，本发明实施例还提供一种薄膜晶体管的制作方法，如图3所示，该制作方法包括以下步骤：
101、在基板10上形成第一过渡层11，第一过渡层11材料的热膨胀系数介于基板10的材料的热膨胀系数和栅电极12的材料的热膨胀系数之间；
102、在第一过渡层11上形成包括栅电极12在内的栅金属层图形；
103、在低于第一极限温度的条件下，在栅电极12和第一过渡层11上形成栅绝缘层13；
104、在栅绝缘层13上依次形成有源层14、源电极15和漏电极16。
根据本发明提供的薄膜晶体管的制作方法，在基板上先沉积热膨胀系数介于基板材料的热膨胀系数和栅电极材料的热膨胀系数之间的第一过渡层，改变栅绝缘层的材料或成膜方式以使栅绝缘层材料的成膜温度低于栅电极材料内部承受的压缩应力的极限值对应的第一极限温度，从而能够有效减少栅电极膜层的表面上小丘的产生，提高有源层性能的稳定性，并且降低产品的功耗，提高产品市场竞争力。
形成所述栅电极12在内的栅金属层图形的步骤102包括例如包括：在所述第一过渡层11上形成铝薄膜，并通过构图工艺形成包括栅电极12在内的栅金属层图形。在本实施例中，栅电极12的材料为铝，对应的第一极限温度为150℃。
本实施例中的基板10例如为玻璃基板，第一过渡层11的材料例如为氧化铝。在基板10上形成第一过渡层11的步骤101例如包括：采用溅射方法在基板10上形成氧化铝薄膜。步骤102例如包括：采用溅射方法在氧化铝薄膜上形成铝薄膜。氧化铝薄膜可采用溅射方法制备，成膜温度低，可以避免栅电极的膜层即铝薄膜表面上小丘的产生，而且工艺简单，成本低，不需额外的投入。
有源层14的材料例如为氧化物半导体材料。在形成有源层14之前，根据本发明的实施例的制作方法还包括：在栅绝缘层13上形成第二过渡层141，第 二过渡层141的材料为有源层14形成材料的高氧氧化物。例如，在沉积氧化物半导体形成有源层之前，直接在同一腔室内，在富氧气氛下，进行高氧氧化物薄膜的沉积。然后改变腔室内的气氛，再进行有源层的氧化物半导体膜层的沉积。该高氧氧化物薄膜的氧含量质量百分比约为50％-80％，该薄膜基本为绝缘性薄膜，可作为栅绝缘层到氧化物半导体材料之间的过渡层，有效的改善栅绝缘层与氧化物有源层的界面匹配。
为了本领域技术人员更好的理解本发明实施例提供的薄膜晶体管的制作方法，以下列举几种本发明的具体实施方案对本发明提供的制作方法进行详细说明。
实施方案一
步骤一、参看图1，在基板10上形成作为第一过渡层11的氧化铝薄膜。在溅射纯铝腔室中通入氧气(5％左右)，进行纯铝反应溅射，溅射厚度在50-200埃。该膜层作为第一过渡层11，第一过渡层11不需图形化。
步骤二、直接在溅射纯铝腔室中原位进行纯铝栅电极12的溅射(温度选择100～150℃)，溅射腔室中不通入氧气，并且重新抽真空以避免纯铝氧化，然后使用常规方法进行图形化，刻蚀出包括栅电极12的栅电极图形。
步骤三、在低温下进行作为栅绝缘层13的氧化铝薄膜的溅射。在溅射纯铝腔室中通入氩气Ar和氧气O2，氧气浓度在5％左右，进行氧化铝薄膜的溅射成膜，厚度约1000-2000埃。之后使用刻蚀液进行栅绝缘层13图形化的过程。
步骤四、沉积氧化物半导体，形成有源层14，该氧化物半导体材料可以为IGZO、IZO、ZnO、ZTO等材料。
步骤五、使用常规的方法依次形成刻蚀阻挡层17、包括源极/漏极15/16的源漏金属层、钝化层18。
实施方案二
步骤一、参看图2，在基板10上形成作为第一过渡层11的氧化铝薄膜。在溅射纯铝腔室中通入氧气(5％左右)，进行纯铝反应溅射，溅射厚度在50-200埃。该膜层作为第一过渡层11，第一过渡层11不需图形化。
步骤二、直接在溅射纯铝腔室中原位进行纯铝栅电极12的溅射(温度选择100～150℃)，溅射腔室中不通入氧气，并且重新抽真空以避免纯铝氧化，然后使用常规方法进行图形化，刻蚀出包括栅电极12的栅电极图形。
步骤三、在低温下进行作为栅绝缘层13的氧化铝薄膜的溅射。在溅射纯铝腔室中通入Ar和氧气，氧气浓度在5％左右，进行氧化铝薄膜的溅射成膜，厚度约1000-2000埃。之后使用刻蚀液进行栅绝缘层13图形化的过程。
步骤四、沉积氧化物半导体，形成有源层该氧化物半导体材料可以为IGZO、IZO、ZnO、ZTO等材料。与实施方案一不同的是，在实施方案二中，首先进行高氧氧化物薄膜的沉积，然后原位直接进行作为有源层14的氧化物半导体薄膜的沉积。上述高氧氧化物薄膜的氧含量约为50％～80％，该高氧氧化物薄膜基本为绝缘性薄膜，其可作为栅绝缘层材料到氧化物半导体材料之间的过渡层，可以有效的改善栅绝缘层与氧化物有源层的界面接触。
步骤五、使用常规的方法依次形成刻蚀阻挡层17、包括源极/漏极15/16的源漏金属层、钝化层18。
实施方案三
步骤一、如图4所示，在基板10上形成作为第一过渡层11的氧化铝薄膜，在溅射纯铝腔室中通入氧气(5％左右)，进行纯铝反应溅射，溅射厚度在50-200埃。该膜层作为第一过渡层11，第一过渡层11不需图形化。
步骤二、直接在溅射纯铝腔室中原位进行纯铝栅电极12的溅射(温度选择100～150℃)，溅射腔室中不通入氧气，并且重新抽真空以避免纯铝氧化，然后使用常规方法进行图形化，刻蚀出包括栅电极12的栅金属层图形。
步骤三、在低温下进行作为栅绝缘层13的氧化铝薄膜的溅射。在溅射纯铝腔室中通入Ar和氧气，氧气浓度在5％左右，进行氧化铝薄膜的溅射成膜，厚度约1000-2000埃。之后使用刻蚀液进行栅绝缘层13图形化过程。
步骤四、沉积氧化物半导体，形成有源层14，该氧化物半导体材料可以为IGZO、IZO、ZnO、ZTO等材料。
步骤五、使用常规的方法形成IPS(In-Plane Switching)面内切换型液晶显示装置结构中的刻蚀阻挡17、源漏金属层(包括源电极15和漏电极16)、第一透明导电层19、钝化层18、第二透明导电层20。
实施方案四
实施方案四与实施方案三基本相同，其不同之处在于在实施方案四中，首先进行高氧氧化物薄膜的沉积，然后原位直接进行作为有源层14的氧化物半导体薄膜的沉积。上述高氧氧化物薄膜的氧含量约为50％～80％，该高氧氧化物薄膜基本为绝缘性薄膜，其可作为栅绝缘层材料到氧化物半导体材料之间的 过渡层，可以有效的改善栅绝缘层与氧化物有源层的界面接触。
本发明实施例提供一种薄膜晶体管的制作方法，能够有效减少栅电极膜层的表面上小丘的产生，提高有源层性能的稳定性，并且降低产品的功耗，提高产品市场竞争力。
以上实施方式仅用于说明本公开，而并非对本公开的限制，有关技术领域的普通技术人员，在不脱离本公开的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本公开的范畴，本公开的专利保护范围应由权利要求限定。
本申请要求于2014年6月10日递交的中国专利申请第201410256092.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种薄膜晶体管，包括：基板，和依次形成于所述基板上方的栅电极、栅绝缘层、有源层、源电极和漏电极，
    其中所述栅电极形成于所述基板和所述栅绝缘层之间，
    所述薄膜晶体管还包括：
    设置于所述基板上，且位于所述栅电极和所述基板之间的第一过渡层，所述第一过渡层的材料的热膨胀系数介于所述基板的材料的热膨胀系数和所述栅电极的材料的热膨胀系数之间；且
    形成所述栅绝缘层的温度低于第一极限温度，所述第一极限温度指所述栅电极的膜层受压缩应力而不形变的极限值对应的温度。
  2. 根据权利要求1所述的薄膜晶体管，其中
    所述栅电极的材料为铝，所述第一极限温度为150℃。
  3. 根据权利要求2所述的薄膜晶体管，其中
    所述基板为玻璃基板，所述第一过渡层的材料为氧化铝。
  4. 根据权利要求3所述的薄膜晶体管，其中
    所述第一过渡层的厚度为50～200nm。
  5. 根据权利要求1-4中任一项所述的薄膜晶体管，其中
    所述有源层的材料为氧化物半导体材料。
  6. 根据权利要求5所述的薄膜晶体管，其中
    所述栅绝缘层的材料为氧化铝。
  7. 根据权利要求5所述的薄膜晶体管，还包括设置于所述有源层和所述栅绝缘层之间的第二过渡层，所述第二过渡层的材料为所述有源层的材料的高氧氧化物。
  8. 根据权利要求7所述的薄膜晶体管，其中
    所述高氧氧化物中含氧量的质量百分比为50％～80％。
  9. 一种OLED背板，包括：权利要求1-8任一项所述的薄膜晶体管。
  10. 一种显示装置，包括：权利要求1-8任一项所述的薄膜晶体管，或者权利要求9所述的OLED背板。
  11. 一种薄膜晶体管的制作方法，包括：
    在基板上形成第一过渡层，所述第一过渡层材料的热膨胀系数介于所述基 板的材料的热膨胀系数和栅电极的材料的热膨胀系数之间；
    在所述第一过渡层上形成包括栅电极的栅金属层图形；
    在低于第一极限温度的条件下，在所述栅电极和所述第一过渡层上形成栅绝缘层；
    在所述栅绝缘层上依次形成有源层、源电极和漏电极。
  12. 根据权利要求11所述的制作方法，其中所述形成包括所述栅电极的栅金属层图形为：在所述第一过渡层上形成铝薄膜，并通过构图工艺形成包括所述栅电极的栅金属层图形；
    所述第一极限温度为150℃。
  13. 根据权利要求12所述的制作方法，其中
    所述基板为玻璃基板，所述第一过渡层的形成材料为氧化铝。
  14. 根据权利要求13所述的制作方法，其中所述在基板上形成第一过渡层为：采用溅射方法在基板上形成氧化铝薄膜；
    所述在所述第一过渡层上形成铝薄膜为：采用溅射方法在所述氧化铝薄膜上形成铝薄膜。
  15. 根据权利要求11或12所述的制作方法，其中所述有源层的材料为氧化物半导体材料；在形成所述有源层之前，所述制作方法还包括：
    在所述栅绝缘层上形成第二过渡层，所述第二过渡层的材料为所述有源层的材料的高氧氧化物。
PCT/CN2014/086079 2014-06-10 2014-09-05 薄膜晶体管及其制作方法、oled背板和显示装置 WO2015188476A1 (zh)

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