WO2015096307A1 - 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法 - Google Patents

氧化物薄膜晶体管、显示器件、及阵列基板的制造方法 Download PDF

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WO2015096307A1
WO2015096307A1 PCT/CN2014/075507 CN2014075507W WO2015096307A1 WO 2015096307 A1 WO2015096307 A1 WO 2015096307A1 CN 2014075507 W CN2014075507 W CN 2014075507W WO 2015096307 A1 WO2015096307 A1 WO 2015096307A1
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Prior art keywords
electrode
layer pattern
photoresist
oxide
layer
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PCT/CN2014/075507
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English (en)
French (fr)
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王珂
刘圣烈
宁策
杨维
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京东方科技集团股份有限公司
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Priority to US14/416,227 priority Critical patent/US9502577B2/en
Publication of WO2015096307A1 publication Critical patent/WO2015096307A1/zh

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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an oxide thin film transistor, a display device, and a method of fabricating an array substrate.
  • a main component of the active layer is usually silicon such as amorphous silicon or polycrystalline silicon.
  • TTT (hereinafter referred to as amorphous silicon TFT) using amorphous silicon as an active layer is difficult to be used in applications requiring large current and fast response due to limitations of amorphous silicon characteristics such as mobility and on-state current. , such as organic light-emitting displays and displays of large size, high resolution, high refresh rate, etc.
  • a TFT using polysilicon as an active layer (hereinafter referred to as a polysilicon TFT) can be used for a case where a large current and a fast response are required because polysilicon characteristics are superior to amorphous silicon, but uniformity of polysilicon Poor performance, it is still difficult to prepare medium and large size panels. Therefore, a TFT using an oxide semiconductor as an active layer (hereinafter referred to as an oxide TFT) has been receiving increasing attention.
  • Oxide semiconductors such as Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO) as the active layer oxide TFT, mobility, on-state Current, switching characteristics, etc. are superior to amorphous silicon TFTs.
  • IGZO Indium Gallium Zinc Oxide
  • ITZO Indium Tin Zinc Oxide
  • mobility on-state Current, switching characteristics, etc.
  • the characteristics of the oxide TFT are not as good as those of the polysilicon TFT, it is still sufficient for a large current and a fast response.
  • the uniformity of the oxide semiconductor is good, there is no problem in uniformity compared with the polysilicon, and the active layer can be prepared by a method such as sputtering, deposition, etc., without adding additional equipment, and the cost is low.
  • the oxide TFT array substrate includes an oxide TFT 1 and a pixel electrode 7.
  • the oxide TFT 1 includes a gate electrode 2, a source electrode 3, a drain electrode 4, and an oxide active layer pattern 5, and the source electrode 3 and the drain electrode 4 are located above the oxide active layer pattern 5, and the drain electrode 4 and the pixel The electrodes 7 are connected.
  • the source electrode 3 and the drain electrode 4 are usually formed by a ffi wet engraved metal source/drain metal layer (not shown).
  • the pattern 5 also has an engraving effect, and thus the oxide active layer pattern 5 is destroyed.
  • an etch stop layer 20 is formed on the oxide active layer pattern 5 except for the region where the oxide active layer pattern 5 is in contact with the source electrode 3 and the drain electrode 4.
  • the protective oxide active layer pattern 5 is not destroyed.
  • at least one photolithography process needs to be added, so that the current manufacturing process of the oxide TFT array substrate basically requires 67 lithography processes, which increases the manufacturing cost.
  • the invention provides a method for manufacturing an oxide thin film transistor and an oxide thin film transistor array substrate, and ffi is used to solve the prior art to form an etch barrier layer between the source electrode, the drain electrode and the oxide active layer pattern to protect the oxidation.
  • ffi is used to solve the prior art to form an etch barrier layer between the source electrode, the drain electrode and the oxide active layer pattern to protect the oxidation.
  • the present invention also provides a display device which employs the above oxide thin film transistor to reduce production cost.
  • an oxide thin film transistor including a gate electrode, a gate insulating layer, an oxide active layer pattern, a source electrode, and a drain electrode, wherein the source electrode and the drain electrode are provided
  • the pole is located below the oxide active layer pattern; the gate electrode is located below the source electrode and the drain electrode; and the gate insulating layer is located between the gate electrode and the source electrode and the drain electrode.
  • an oxide thin film transistor display device comprising the oxide thin film transistor as described above.
  • a method of fabricating an oxide thin film transistor array substrate includes the steps of forming an oxide thin film transistor on a base substrate, wherein the oxide thin film transistor includes a gate electrode and a gate An insulating layer, an oxide active layer pattern, a source electrode and a drain electrode, wherein the step of forming an oxide thin film transistor on the base substrate comprises:
  • An oxide active layer pattern is formed on the base substrate on which the source electrode and the drain electrode are formed.
  • the beneficial effects of the above technical solution of the present invention are as follows:
  • the source electrode, the drain electrode and the gate electrode are formed under the oxide active layer pattern, and the cabinet electrode is located below the source electrode and the drain electrode, so that the etching process for forming the source electrode and the drain electrode does not occur. Destruction of the oxide active layer pattern.
  • the photolithography process for forming the etch barrier layer pattern is omitted, the mass productivity of the oxide thin film transistor display device is improved, and the production cost is reduced.
  • FIG. 1 is a schematic view showing a part of the structure of an oxide TFT array substrate in the prior art.
  • FIG. 2 is a schematic view showing a partial structure of an oxide TFT array substrate in an embodiment of the present invention.
  • FIG 3 is a schematic view showing a manufacturing process of an oxide TFT array substrate in an embodiment of the present invention.
  • the embodiment provides a method for fabricating an oxide TFT array substrate, including the step of forming an oxide TFT on a base substrate, wherein the oxide TFT includes a gate electrode, a gate insulating layer, an oxide active layer pattern, Source and drain electrodes.
  • the step of forming an oxide thin film transistor on the base substrate comprises:
  • An oxide active layer pattern is formed on the base substrate on which the source electrode and the drain electrode are formed.
  • the source electrode, the drain electrode, and the gate electrode are formed under the oxide active layer pattern, and the gate electrode is located under the source electrode and the drain electrode, so that the etching process for forming the source electrode and the drain electrode is not oxidized.
  • the active layer pattern creates damage.
  • the etching barrier layer is not required to be formed on the oxide active layer pattern, the photolithography process for forming the engraved barrier layer pattern is omitted, the mass production of the oxide thin film transistor display device is improved, and the production cost is lowered. .
  • the base substrate is made of a light-transmitting material and has good light transmittance, and may be usually a glass substrate, a quartz substrate or a transparent resin substrate.
  • the surfaces of the source electrode and the drain electrode may be subjected to plasma treatment in advance before the step of forming the oxide active layer pattern.
  • the plasma treatment for example, ⁇ nitrous oxide (N 2 0) of the source electrode and the surface of the drain electrode of the plasma treatment, in order to effectively reduce the leakage current of the TFT, to improve the phenomenon of the screen of the display device flicker, crosstalk and residual image, to improve display performance.
  • hydrogen ions enter the oxide active layer pattern, the oxygen vacancies of the oxide active layer pattern are changed, thereby affecting the performance and service life of the TFT, and therefore the oxide active layer pattern is generally annealed to dehydrogenate.
  • the annealing dehydrogenation treatment reduces the oxygen content of the oxide active layer pattern and affects its semiconductor characteristics.
  • the oxygen content of the source electrode and the drain electrode can be increased by the above-described plasma treatment, and the sufficient oxygen content of the source electrode and the drain electrode can supplement the oxygen element to the oxide active layer pattern, thereby ensuring the semiconductor characteristics of the oxide active layer pattern.
  • the manufacturing process of the oxide TFT array substrate of the ADS (or AD-SDS, Advanced Super Dimension Switch) mode display device is taken as an example to specifically describe the oxide TFT array substrate in this embodiment. Production method.
  • the ADS mainly forms a multi-dimensional electric field by the electric field generated by the edge of the slit pixel electrode in the same plane (that is, the slit having a plurality of slits extending in the pixel electrode) and the electric field generated between the slit pixel electrode layer and the plate-like common electrode layer. All of the aligned liquid crystal molecules between the slit pixel electrodes in the liquid crystal cell and directly above the pixel electrode can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of the display device, and has the advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura.
  • Step SI forming a pattern including the cabinet electrode 2 and the common electrode 6 on the base substrate 0, and forming an insulation layer 11 on the »electrode 2;
  • Step S2 forming a pattern including the source electrode 3 and the drain electrode 4 on the gate insulating layer 11;
  • Step S4 forming a passivation layer on the oxide active layer pattern 5, 2, forming a passivation layer via 9 on the passivation layer 12;
  • Step S5 A slit pixel electrode 7' is formed on the passivation layer via 9.
  • the fabrication of the oxide TFT array substrate of the ADS mode display device is completed by five photolithography processes, thereby saving cost and improving mass productivity.
  • step S1 is specifically:
  • a transparent conductive layer (not shown) and a gate metal layer (not shown) are sequentially formed on the base substrate.
  • a transparent conductive layer e.g., indium tin oxide, indium zinc oxide
  • a gate metal layer may be sequentially formed on the substrate 10 by, for example, coating, chemical deposition, sputtering, or the like.
  • a third buffer layer pattern (not shown) may be formed between the base metal layer and the transparent conductive layer, and in addition, the gate metal layer and the gate may be insulated.
  • a fourth buffer layer pattern (not shown) is formed between the layers U, and the third buffer layer and the fourth buffer layer are both disposed in contact with the gate metal layer and correspond to a region where the gate electrode 2 is located.
  • the material of the third buffer layer and the fourth buffer layer may be, for example, MoNb, MoW or MoTi.
  • a pattern including the gate electrode 2 and the common electrode 6 is formed by one patterning process using a halftone or gray tone mask.
  • a pattern including the gate electrode 2 and the common electrode 6 can be formed, for example, by the following process. First, after coating a layer of photoresist on the fourth buffer layer, the photoresist is exposed and developed by using a halftone or gray tone mask, so that the photoresist forms a photoresist-free region, and the photoresist Completely reserved area and photoresist semi-reserved area.
  • the photoresist completely reserved region includes a region where the gate electrode is located
  • the photoresist semi-reserved region includes a region where the common electrode is located
  • the photoresist non-reserved region corresponds to other regions.
  • the fourth buffer layer, the gate metal layer, the third buffer layer, and the transparent conductive layer of the photoresist non-retained region are completely engraved by the first etching process.
  • the first etching process etches the fourth buffer layer, the gate metal layer, the third buffer layer, and the transparent conductive layer, for example, by wet etching.
  • the photoresist semi-reserved region is removed by an ashing process
  • the photoresist exposes a fourth buffer layer of the region.
  • the fourth buffer layer and the gate metal layer of the semi-reserved region of the photoresist are completely etched away by the second etching process, so that the transparent conductive layer of the region forms a pattern including the common electrode 6.
  • the second etching process etches the fourth buffer layer and the gate metal layer, for example, by wet etching.
  • the remaining photoresist is stripped, specifically, the photoresist in the completely remaining region of the photoresist is stripped, so that the gate metal layer of the region forms a pattern including the cabinet electrode 2.
  • a pattern including the »electrode 2 and the common electrode 6 is simultaneously formed by one patterning process, which reduces the production cost.
  • a gate insulating layer 1 is formed on the gate electrode 2.
  • the gate insulating layer 11 can be formed on the gate electrode 2 by, for example, coating, chemical deposition, sputtering, or the like.
  • the insulating layer of the cabinet has a thickness of 150 300 nm, which may be a silicon dioxide layer, or a composite layer of any two of the silicon dioxide layer, the silicon oxynitride layer and the silicon nitride layer, or It may also be a composite layer of three film layers of a silicon dioxide layer, a silicon oxynitride layer and a silicon nitride layer.
  • the silicon dioxide layer is disposed close to the oxide active layer pattern because the H content in 0 2 is relatively small and does not affect the semiconductor characteristics of the oxide active layer pattern 5.
  • step S2 B is performed: the source electrode 3 and the drain electrode 4 of the oxide TFT are formed on the gate insulating layer 11.
  • step S2 is specifically:
  • a source/drain metal layer (not shown) is formed on the gate insulating layer 11 by a process such as coating, chemical deposition, sputtering, or the like.
  • the photoresist is exposed and developed by a common mask to form a photoresist-retained area and a photoresist-unretained area.
  • the coating may be, for example, spin coating
  • the photoresist retention region includes a region where the source electrode 3 and the drain electrode 4 are located, and the photoresist non-retention region corresponds to other regions.
  • the wet/drain method completely etches away the source/drain metal layer in the non-retained region of the photoresist. Finally, the remaining photoresist is peeled off to expose the source/drain metal layer of the photoresist remaining region, and the source/drain metal layer of the region forms a pattern including the source electrode 3 and the drain electrode 4.
  • a first buffer layer pattern 8 may be formed between the gate insulating layer 11 and the source electrode 3 and the drain electrode 4, and further, the source may be A second buffer layer pattern (not shown) is formed between the electrode 3, the drain electrode 4 and the oxide active layer pattern 5, and the first buffer layer pattern 8 and the second buffer layer pattern are both connected to the source Electrode 3 and The drain electrode 4 is in contact with the setting.
  • the material of the first buffer layer pattern 8 and the second buffer layer pattern may be, for example, MoNb, MoW or MoTi, and may be formed in the same patterning process as the source electrode 3 and the drain electrode 4, thereby saving cost. .
  • step S2 after the source electrode 3 and the drain electrode 4 are formed, the surfaces of the source electrode 3 and the drain electrode 4 are plasma-treated with a laughing gas (N 2 0) to improve the source electrode 3, the drain electrode 4, and the oxidation.
  • a laughing gas N 2 0
  • the contact resistance of the active layer pattern reduces the leakage current of the oxide TFT.
  • step S3 is performed, that is, the oxide active layer pattern 5 is formed on the source electrode 3 and the drain electrode 4.
  • step S3 is specifically:
  • an oxide active layer (not shown) is formed on the source electrode 3 and the drain electrode 4 by a magnetron sputtering film formation process. Then, the ffi ordinary mask is used to form the oxide active layer pattern 5 by a patterning process including coating of a photoresist, exposure, development, and etching.
  • step S4 is performed, gP forms a passivation layer 12 on the oxide active layer pattern 5, and in the passivation layer 12 A passivation layer via 9 is formed thereon.
  • step S4 is specifically:
  • a passivation layer 12 is formed on the oxide active layer pattern 5, i.e., the fabrication of the oxide TFT is completed.
  • a low-temperature high-density deposition method can be used to form the passivation layer 12, and the deposition temperature needs to be controlled to 200 ⁇ or less.
  • the material of the passivation layer 12 may be a composite layer of two layers of a silicon dioxide layer and a silicon oxynitride layer, or a composite layer of three layers of a silicon dioxide layer, a silicon oxynitride layer and a silicon nitride layer. .
  • the passivation layer 12 may be annealed at an annealing temperature of between 250 ⁇ and 350 ⁇ .
  • step S5 is performed, Bp: on the passivation layer via 9.
  • a slit pixel electrode 7' is formed.
  • step S5 is specifically as follows:
  • the via hole 9 of the passivation layer is connected to the drain electrode 4 of the oxide TFT1.
  • the material of the slit pixel electrode 7' may be, for example, a transparent conductive material (such as indium tin oxide or indium zinc oxide).
  • annealing may be performed after the oxide TTT array substrate is manufactured, and the annealing temperature may be 250. "C 300 ⁇ .
  • the manufacturing process of the oxide TFT array substrate of the ADS mode display device is taken as an example to specifically illustrate the technical solution of the present invention, which is not limited. All of the display devices using the oxide array substrate, such as a ⁇ mode display device, an IPS mode display device, etc., can be fabricated using the technical solution of the present invention.
  • the oxide TFT1 includes a »electrode 2, a gate insulating layer 1], an oxide active layer pattern 5, a source electrode 3, and a drain electrode 4.
  • the source electrode 3 and the drain electrode 4 are located below the oxide active layer pattern 5, the gate electrode 2 is located below the source electrode 3 and the drain electrode 4, and the gate insulating layer 1 is located at the germanium electrode 2 and the source electrode 3 and the drain electrode 4
  • the source electrode 3, the drain electrode 4, and the gate electrode 2 are formed under the oxide active layer pattern 5, and the electrode 2 is located under the source electrode 3 and the drain electrode 4, so that the source electrode 3 is formed.
  • the etching process of the drain electrode 4 does not cause damage to the oxide active layer pattern 5. And, since it is not necessary to form an etch barrier layer on the oxide active layer pattern 5, the photolithography process for forming the etch barrier layer pattern is omitted, and the mass productivity of the oxide thin film transistor array substrate is improved, and the etching is lowered. Cost of production.
  • a first buffer layer pattern 8 is formed between the *insulating layer U and the source electrode 3 and the drain electrode 4.
  • the first buffer layer pattern 8 corresponds to the region where the source electrode 3 and the drain electrode 4 are located, and The source electrode 3 and the drain electrode 4 are provided in contact with each other for improving the adhesion and diffusibility of the source electrode 3 and the drain electrode 4.
  • a second buffer layer pattern (not shown) may be formed between the source electrode 3, the drain electrode 4 and the oxide active layer pattern 5, and is placed in contact with the source electrode 3 and the drain electrode 4.
  • the material of the first buffer layer pattern 8 and the second buffer layer pattern may be, for example, MoNb, MoW or MoTi.
  • Embodiment 3 provides an oxide TFT display device which is a device including an oxide thin film transistor such as an oxide TFT array substrate, an oxide TFT display device, or the like.
  • the oxide TFT display device includes an oxide thin film transistor 1 formed on a base substrate 10, the oxide thin film transistor 1 including a cabinet electrode 2, a gate insulating layer, and an oxide active Layer pattern 5, source electrode 3 and drain electrode 4.
  • the source electrode 3 and the drain electrode 4 are located below the oxide active layer pattern 5, the »electrode 2 is located below the source electrode 3 and the drain electrode 4, and the cabinet insulating layer 1 is located at the gate electrode 2 and the source electrode 3 and the drain electrode 4. between.
  • the source electrode 3, the drain electrode 4, and the gate electrode 2 are formed under the oxide active layer pattern 5, and the electrode 2 is located under the source electrode 3 and the drain electrode 4, so that a source is formed
  • the etching process of the electrode 3 and the drain electrode 4 does not cause damage to the oxide active layer pattern 5.
  • the photolithography process for forming the etch barrier layer pattern is omitted, the mass productivity of the oxide thin film transistor array substrate is improved, and the production is lowered. cost.
  • a first buffer layer pattern 8 is formed between the *insulating layer U and the source electrode 3 and the drain electrode 4.
  • the first buffer layer pattern 8 corresponds to the region where the source electrode 3 and the drain electrode 4 are located, and The source electrode 3 and the drain electrode 4 are provided in contact with each other for improving the adhesion and diffusibility of the source electrode 3 and the drain electrode 4.
  • a second buffer layer pattern (not shown) may be formed between the source electrode 3, the drain electrode 4 and the oxide active layer pattern 5, and is placed in contact with the source electrode 3 and the drain electrode 4.
  • the material of the first buffer layer pattern 8 and the second buffer layer pattern may be, for example, MoNb, MoW or MoTi, and the thickness of the source electrode 3 and the drain electrode 4 may be, for example, 200-300 ⁇ m.
  • a third buffer layer pattern (not shown) is formed between the base substrate 10 and the gate electrode 2, the third buffer layer pattern corresponding to the gate The region where the electrode 2 is located is disposed in contact with the gate electrode 2.
  • a fourth buffer layer pattern (not shown) may be formed between the gate electrode 2 and the gate insulating layer 11 and placed in contact with the gate electrode 2.
  • the material of the third buffer layer pattern and the fourth buffer layer pattern may be, for example, MoNb, MoW or MoTi, and the thickness of the germanium electrode 2 may be, for example, 200 to 300 nm.
  • the thickness of the gate insulating layer 11 may be, for example, 150 to 300 nm, and the insulating layer 11 may be a silicon dioxide layer, or may be any two of the silicon dioxide layer, the silicon oxynitride layer, and the silicon nitride layer.
  • the composite layer or alternatively, may be a silicon dioxide layer, a silicon oxynitride layer, and a silicon nitride layer. Composite layer.
  • the silicon dioxide layer is disposed close to the oxide active layer pattern 5 because
  • the H content in Si0 2 is relatively small, and does not affect the semiconductor characteristics of the oxide active layer pattern 5.
  • the oxide active layer pattern 5 may have a thickness of, for example, 40 to 50 nm, and the material thereof is an oxide semiconductor such as indium tin oxide or indium zinc oxide.
  • the oxide TFT array substrate further includes a common electrode 6, a slit pixel electrode 7', and a passivation layer 12, wherein the slit pixel electrode 7' passes through the passivation layer via 9 and the oxide TFT leakage Extreme 4 connection.
  • the thickness of the common electrode 6 is about 70 nrn, and corresponds to the position of the slit pixel electrode 7', and under the control of the oxide TFT 1, the edge of the slit pixel electrode 7' is made.
  • the electric field generated between and the electric field generated between the slit pixel electrode 7' and the plate-like common electrode 6 forms a multi-dimensional electric field for driving the rotation of the liquid crystal molecules.
  • the gate electrode 2 and the common electrode 6 of the oxide TTT1 are simultaneously formed, for example, by one patterning process, thereby reducing the production cost and improving the mass productivity.

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Abstract

提供一种氧化物薄膜晶体管及采用其的显示器件、以及氧化物薄膜晶体管阵列基板的制造方法。该氧化物薄膜晶体管的氧化物有源层图案（5）位于源电极（3）、漏电极（4）和栅电极（2）的下方，且栅电极（2）位于源电极（3）和漏电极（4）的下方，使得形成源电极（3）和漏电极（4）的刻蚀工艺不会对氧化物有源层图案（5）产生破坏。并且，由于不需要在氧化物有源层图案（5）上形成刻蚀阻挡层，从而省略了形成刻蚀阻挡层图案的光刻工序，提高了氧化物薄膜晶体管显示器件的量产性，降低了生产成本。

Description

本发明涉及显示技术领域， 特别是涉及一种氧化物薄膜晶体管、 显示器 件、 及阵列基板的制造方法。
目前， 在液晶显示器的薄膜晶体管（Thin Film Transistor, 简称 TFT)中， 作为有源层的主要成分通常为硅， 如非晶硅或多晶硅。 采用非晶硅作为有源 层的 TTT (以下称为非晶硅 TFT) , 因受到非晶硅特性， 如迁移率、 开态电流 等的限制， 难以用于需要较大电流和快速响应的场合， 如有机发光显示器和 大尺寸、 高分辨率、 高刷新频率的显示器等。 另一方面， 釆用多晶硅作为有 源层的 TFT (以下称为多晶硅 TFT)， 虽然因多晶硅特性优于非晶硅而可以用 于需要较大电流和快速响应的场合， 但是， 因多晶硅的均匀性较差， 制备中、 大尺寸的面板仍有困难。 因此， 采用氧化物半导体作为有源层的 TFT (以下 称为氧化物 TFT) 日益受到重视。
采用氧化物半导体， 如铟镓锌氧化物 （Indium Gallium Zinc Oxide, 简称 IGZO)、 铟锡锌氧化物（Indium Tin Zinc Oxide, 简称 ITZO)作为有源层的氧 化物 TFT， 其迁移率、 开态电流、 开关特性等均优于非晶硅 TFT。 此外， 虽 然氧化物 TFT特性不如多晶硅 TFT， 但是仍足以) ¾于需要较大电流和快速响 应的应 ^中。 而— ， 由于氧化物半导体的均匀性好， 因此， 与多晶硅相比， 没有均匀性方面的问题， 可以采用澱射、 沉积等方法制备有源层， 不需要增 加额外的设备， 成本较低。
图 1为现有技术中氧化物 TFT阵列基板的结构示意图。 如图 1所示， 氧 化物 TFT阵列基板包括氧化物 TFT 1和像素电极 7。 其中， 氧化物 TFT 1包 括栅电极 2、 源电极 3、 漏电极 4和氧化物有源层图案 5， 源电极 3和漏电极 4位于氧化物有源层图案 5的上方， 漏电极 4与像素电极 7连接。 在氧化物 TFT阵列基板的制造工艺中， 通常采 ffi湿法刻烛源漏金属层 （图中未示出） 来形成源电极 3和漏电极 4。 由于刻蚀液对源漏金属层下面的氧化物有源层 图案 5也具有刻馊作用， 因此会破坏该氧化物有源层图案 5。 为了解决上述 问题， 现有技术中， 除了氧化物有源层图案 5与源电极 3、 漏电极 4接触的 区域外， 在氧化物有源层图案 5上都会制作一层刻蚀阻挡层 20， 以保护氧化 物有源层图案 5不被破坏。 但是， 这样一来， 需要增加至少一道光刻工序， 使得目前的氧化物 TFT阵列基板的制造工艺基本都需要 6 7道光刻工艺， 增 加了制造成本。
本发明提供一种氧化物薄膜晶体管及氧化物薄膜晶体管阵列基板的制造 方法， ffi以解决现有技术中在源电极、 漏电极和氧化物有源层图案之间形成 刻蚀阻挡层来保护氧化物有源层图案不被破坏时， 需要增加光刻工序， 造成 生产成本增加的问题。
同时， 本发明还提供一种显示器件， 其采用上述的氧化物薄膜晶体管， 于降低生产成本。
为解决上述技术问题， 在本发明的一个实施例中， 提供一种氧化物薄膜 晶体管， 包括栅电极、 栅绝缘层、 氧化物有源层图案、 源电极和漏电极， 其 中， 源电极和漏电极位于氧化物有源层图案的下方； 栅电极位于源电极和漏 电极的下方； 栅绝缘层位于栅电极和源电极、 漏电极之间。
同时， 在本发明的另一个实施例中， 提供一种氧化物薄膜晶体管显示器 件， 其包括如上所述的氧化物薄膜晶体管。
在本发明的再一实施例中， 提供一种氧化物薄膜晶体管阵列基板的制造 方法， 包括在衬底基板上形成氧化物薄膜晶体管的步骤， 其中， 所述氧化物 薄膜晶体管包括栅电极、 栅绝缘层、 氧化物有源层图案、 源电极和漏电极， 其中， 所述在衬底基板上形成氧化物薄膜晶体管的步骤包括：
在衬底基板上形成栅电极；
在形成了栅电极的衬底基板上形成栅绝缘层；
在形成了櫥绝缘层的衬底基板上形成源电极和漏电极； 以及
在形成了源电极和漏电极的衬底基板上形成氧化物有源层图案。
本发明的上述技术方案的有益效果如下： 上述技术方案中， 通过在氧化物有源层图案的下方形成源电极、 漏电极 和栅电极， 且櫥电极位于源电极和漏电极的下方， 使得形成源电极和漏电极 的刻蚀工艺不会对氧化物有源层图案产生破坏。 同时， 由于不需要在氧化物 有源层图案上形成刻蚀阻挡层，因而省略了形成刻蚀阻挡层图案的光刻工序， 提高了氧化物薄膜晶体管显示器件的量产性， 降低了生产成本
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅汉是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动性的前提下， 还可以根据这些 i†图获得其他的 i†图。
图 1为现有技术中氧化物 TFT阵列基板的部分结构的示意图。
图 2为本发明实施例中氧化物 TFT阵列基板的部分结构的示意图。
图 3图 6为本发明实施例中氧化物 TFT阵列基板的制造过程的示意图。
下面将结合附图和实施例，对本发明的具体实施方式作进一步详细描述。 以下实施例用于说明本发明， 但不用来限制本发明的范围。
需要说明的是， 本发明实施例中的 "上" "下"只是参考 图对本发明实 施例进行说明， 不作为限定用语。
实施例一
本实施例提供一种氧化物 TFT阵列基板的制造方法， 包括在衬底基板上 形成氧化物 TFT的步骤， 其中， 所述氧化物 TFT包括栅电极、 栅绝缘层、 氧 化物有源层图案、 源电极和漏电极。 本实施例中， 在衬底基板上形成氧化物 薄膜晶体管的步骤包括：
在衬底基板上形成栅电极；
在形成了櫥电极的衬底基板上形成栅绝缘层；
在形成了栅绝缘层的衬底基板上形成源电极和漏电极； 以及
在形成了源电极和漏电极的衬底基板上形成氧化物有源层图案。 本实施例通过在氧化物有源层图案的下方形成源电极、漏电极和栅电极， 且栅电极位于源电极和漏电极的下方， 使得形成源电极和漏电极的刻蚀工艺 不会对氧化物有源层图案产生破坏。 时， 由于不需要在氧化物有源层图案 上形成刻蚀阻挡层， 因而省略了形成刻馊阻挡层图案的光刻工序， 提高了氧 化物薄膜晶体管显示器件的量产性， 降低了生产成本。
其中， 衬底基板由透光 料制成， 具有良好的透光性， 通常可以为玻璃 基板、 石英基板或透明树脂基板。
为了改善源电极、 漏电极与氧化物有源层图案的接触电阻， 可以在形成 氧化物有源层图案的步骤之前， 预先对源电极和漏电极的表面进行等离子处 理。 所述等离子处理， 例如可以^笑气 （N20) 对源电极和漏电极的表面进 行等离子处理， 以有效降低 TFT的漏电流， 改善显示装置的画面闪烁、 串扰 和残像等现象， 提高显示性能。 此外， 若氢离子进入氧化物有源层图案， 会 使氧化物有源层图案的氧空位发生变化， 从而影响 TFT的性能和使用寿命， 因此一般会对氧化物有源层图案进行退火去氢处理， 以防止氢离子进入氧化 物有源层图案。 但是， 该退火去氢处理会降低氧化物有源层图案的氧含量， 影响其半导体特性。 而通过上述等离子处理能够提高源电极和漏电极的氧含 量， 源电极和漏电极充足的氧含量可以为氧化物有源层图案补充氧元素， 从 而能够保证氧化物有源层图案的半导体特性。
下面以 ADS (或称 AD- SDS， Advanced Super Dimension Switch , 高级超 维场转换技术） 模式显示装置的氧化物 TFT阵列基板的制造过程为例， 来具 体说明本实施例中氧化物 TFT阵列基板的制造方法。
ADS主要是通过同一平面内狭缝像素电极 （即像素电极上具有多个延伸 方向不同的狭缝） 边缘所产生的电场以及狭缝像素电极层与板状公共电极层 间产生的电场形成多维电场， 使液晶盒内的狭缝像素电极间、 像素电极正上 方的所有取向液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大了 透光效率。 高级超维场转换技术可以提高显示装置的画面品质， 具有高分辨 率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波紋（push Mura) 等优点。
下面， 结合图 2-图 6说明氧化物 TFT阵列基板的制造方法。 该制造方法 包括：
步骤 SI : 在衬底基板】 0上形成包括櫥电极 2和公共电极 6的图案， 在 »电极 2上形成 »绝缘层 11 ;
步骤 S2: 在栅绝缘层 11上形成包括源电极 3和漏电极 4的图案； 步骤 S3 : 在源电极 3和漏电极 4上形成氧化物有源层图案 5;
步骤 S4: 在氧化物有源层图案 5上形成钝化层】2, 在钝化层 12上形成 钝化层过孔 9;
步骤 S5: 在钝化层过孔 9上形成狭缝像素电极 7'。
上述步骤中， 通过 5道光刻工艺即完成了 ADS模式显示装置的氧化物 TFT阵列基板的制造， 从而节约了成本， 提高了量产性。
其中， 结合图 3所示， 步骤 S1具体为：
首先， 在衬底基板】 0上依次形成透明导电层（图中未示出）和栅金属层 (图中未示出）。 具体地， 例如可以通过涂覆、 化学沉积、 溅射等工艺在衬底 基板 10上依次形成透明导电层（如： 氧化铟锡、 氧化铟锌）和栅金属层。 进 而， 为了改善栅电极 2的粘 性和扩散性， 还可以在欐金属层与透明导电层 之间形成第三缓冲层图案（图中未示出）， 此外， 还可以在栅金属层与栅绝缘 层 U 之间形成第四缓冲层图案 （图中未示出）， 所述第三缓冲层和所述第四 缓冲层均与栅金属层接触设置， 并对应栅电极 2所在的区域。 其中， 所述第 三缓冲层和所述第四缓冲层的材料例如可以为 MoNb、 MoW或 MoTi。
然后， 采用半色调或灰色调掩膜版， 通过一次构图工艺形成包括栅电极 2和公共电极 6 的图案。 具体地， 例如可以通过如下过程形成包括栅电极 2 和公共电极 6的图案。 首先， 在第四缓冲层上涂覆一层光刻胶后， 采 半色 调或灰色调掩膜版对光刻胶进行曝光、 显影， 使光刻胶形成光刻胶不保留区 域、 光刻胶完全保留区域和光刻胶半保留区域。 其中， 所述光刻胶完全保留 区域包括栅电极所在的区域， 所述光刻胶半保留区域包括公共电极所在的区 域， 所述光刻胶不保留区域对应于其它区域。 然后， 通过第一次刻蚀工艺完 全刻烛掉光刻胶不保留区域的第四缓冲层、 栅金属层、 第三缓冲层和透明导 电层。 所述第一次刻蚀工艺例如采 ^湿刻法对第四缓冲层、 栅金属层、 第三 缓冲层和透明导电层进行刻蚀。 接着， 通过灰化工艺去除光刻胶半保留区域 的光刻胶， 暴露出该区域的第四缓冲层。 然后， 通过第二次刻蚀工艺完全刻 蚀掉光刻胶半保留区域的第四缓冲层和栅金属层， 使该区域的透明导电层形 成包括公共电极 6的图案。 所述第二次刻蚀工艺例如采用湿刻法对第四缓冲 层和栅金属层进行刻蚀。 最后， 剥离剩余的光刻胶， 具体为， 剥离光刻胶完 全保留区域的光刻胶， 使该区域的栅金属层形成包括櫥电极 2的图案。 本步 骤中通过一次构图工艺同时形成包括 »电极 2和公共电极 6的图案， 降低了 生产成本。
最后， 在栅电极 2上形成栅绝缘层 1】。 具体地， 例如可以通过涂覆、 化 学沉积、溅射等工艺在栅电极 2上形成栅绝缘层 11。其中， 櫥绝缘层】1的厚 度为 150 300nm， 其可以为二氧化硅层， 也可以为二氧化硅层、 氮氧化硅层 和氮化硅层中的任意两个膜层的复合层， 或者， 还可以为二氧化硅层、 氮氧 化硅层和氮化硅层三个膜层的复合层。 并且， 例如将二氧化硅层靠近氧化物 有源层图案设置， 这是因为 02中的 H含量比较小， 不会对氧化物有源层图 案 5的半导体特性产生影响。
本实施例中， 在衬底基板 10上形成欐电极 2和欐绝缘层 11后， 执行步 骤 S2， B : 在栅绝缘层 11上形成氧化物 TFT的源电极 3和漏电极 4。
结合图 4所示， 步骤 S2具体为：
首先， 通过涂覆、 化学沉积、 溅射等工艺在栅绝缘层 11上形成源漏金属 层（图中未示出）。 之后， 在源漏金属层上涂覆一层光刻胶后， 采 普通掩膜 版对光刻胶进行曝光、 显影， 使光刻胶形成光刻胶保留区域和光刻胶不保留 区域。 其中， 所述涂覆例如可以为旋涂， 所述光刻胶保留区域包括源电极 3 和漏电极 4所在的区域， 所述光刻胶不保留区域对应于其它区域。 然后， 采 )¾湿刻法完全刻蚀掉光刻胶不保留区域的源漏金属层。 最后， 剥离剩余的光 刻胶， 暴露出光刻胶保留区域的源漏金属层， 该区域的源漏金属层形成包括 源电极 3和漏电极 4的图案。
进一步地， 为了改善源电极 3和漏电极 4的粘附性和扩散性， 可以在栅 绝缘层 11与源电极 3、 漏电极 4之间形成第一缓冲层图案 8， 此外， 还可以 在源电极 3、 漏电极 4与氧化物有源层图案 5之间形成第二缓冲层图案 （图 中未示出），且所述第一缓冲层图案 8和所述第二缓冲层图案均与源电极 3及 漏电极 4接触设置。 其中， 所述第一缓冲层图案 8和所述第二缓 ^层图案的 材料例如可以为 MoNb、 MoW或 MoTi， 还可以与源电极 3、漏电极 4在同一 构图工艺中形成， 从而节约成本。
在步骤 S2中， 在形成源电极 3和漏电极 4之后， 用笑气 （N20) 对源电 极 3和漏电极 4的表面进行等离子处理， ^于改善源电极 3、 漏电极 4与氧 化物有源层图案的接触电阻， 降低氧化物 TFT的漏电流。
本实施例中， 在栅绝缘层】1上形成源电极 3和漏电极 4之后， 执行步骤 S3 , 即： 在源电极 3和漏电极 4上形成氧化物有源层图案 5。
结合图 5所示， 步骤 S3具体为：
首先， 通过磁控溅射成膜工艺在源电极 3、 漏电极 4上形成氧化物有源 层（图中未示出）。 然后， 采 ffi普通掩膜版通过一次构图工艺（包括涂覆光刻 胶、 曝光、 显影、 刻蚀工艺） 形成氧化物有源层图案 5。
本实施例中， 在源电极 3和漏电极 4上形成氧化物有源层图案 5之后， 执行步骤 S4， gP 在氧化物有源层图案 5上形成钝化层 12， 并在钝化层 12 上形成钝化层过孔 9。
结合图 6所示， 步骤 S4具体为：
首先， 在氧化物有源层图案 5上形成钝化层 12， 即完成氧化物 TFT的制 作。 为了防止形成钝化层 12时破坏氧化物有源层图案 5， 例如可以使 低温 高密度的沉积方法形成钝化层 12， 沉积温度需要控制在 200Ό以下。 钝化层 12的村料可以为二氧化硅层和氮氧化硅层两个膜层的复合层， 也可以为二氧 化硅层、 氮氧化硅层和氮化硅层三个膜层的复合层。
然后， 在漏电极 4的上方形成钝化层过孔 9。 并且， 为了提高 TFT器件 的稳定性， 在钝化层过孔 9制作结束后， 还可以对钝化层 12进行退火处理， 退火温度可以在 250Ό- 350Ό之间。
本实施例中， 在氧化物有源层图案 5上形成钝化层 12， 并在钝化层 12 上形成钝化层过孔 9之后， 执行步骤 S5， Bp : 在钝化层过孔 9上形成狭缝像 素电极 7'。
结合图 2所示， 歩骤 S5具体为：
在钝化层过 9上形成阵列基板的狭缝像素电极 7'， 使狭缝像素电极 T 通过钝化层过孔 9与氧化物 TFTl的漏电极 4连接。 其中， 狭缝像素电极 7' 的材料例如可以为透明导电材料 （如氧化铟锡、 氧化铟锌）。
此外， 本实施例中， 为了提高氧化物 TFT阵列基板的稳定性， 并降低狭 缝像素电极 7'的电阻率， 还可以在氧化物 TTT阵列基板制造完成后进行退火 处理， 退火温度可以为 250 "C 300Ό。
本实施例仅是以 ADS模式显示装置的氧化物 TFT阵列基板的制造过程 为例来具体说明本发明的技术方案， 并不是一种限定。 所有使用氧化物 ΤΤΤ 列基板的显示装置， 如： ΤΝ模式的显示装置、 IPS模式的显示装置等， 都 可以使用本发明的技术方案来制造氧化物 TTT阵列基板。
实施例二
本实施例提供一种氧化物 TFT。如图 2所示， 本实施例中， 氧化物 TFT1 包括 »电极 2、 栅绝缘层 1】、 氧化物有源层图案 5、 源电极 3和漏电极 4。 其 中， 源电极 3和漏电极 4位于氧化物有源层图案 5的下方， 栅电极 2位于源 电极 3和漏电极 4的下方， 栅绝缘层 1位于欐电极 2和源电极 3、 漏电极 4
Z间
本实施例的氧化物 TFT1 ,通过在氧化物有源层图案 5的下方形成源电极 3、 漏电极 4和栅电极 2， 电极 2位于源电极 3和漏电极 4的下方， 使得 形成源电极 3和漏电极 4的刻蚀工艺不会对氧化物有源层图案 5产生破坏。 并— ， 由于不需要在氧化物有源层图案 5上形成刻蚀阻挡层， 从而省略了形 成刻蚀阻挡层图案的光刻工序，提高了氧化物薄膜晶体管阵列基板的量产性， 降低了生产成本。
本实施例中， 在 *绝缘层 U与源电极 3、 漏电极 4之间形成有第一缓冲 层图案 8， 第一缓冲层图案 8对应于源电极 3及漏电极 4所在的区域， 并与 源电极 3及漏电极 4接触设置， 用于改善源电极 3和漏电极 4的粘附性和扩 散性。 此外， 在源电极 3、 漏电极 4与氧化物有源层图案 5之间也可以形成 有第二缓冲层图案 （图中未示出）， 并使其与源电极 3及漏电极 4接触设置。 其中， 所述第一缓冲层图案 8 和所述第二缓 ^层图案的^料例如可以为 MoNb、 MoW或 MoTi。
实施例三 本实施例提供一种氧化物 TFT显示器件，所述氧化物 TFT显示器件为如 氧化物 TFT阵列基板、氧化物 TFT显示装置等包括氧化物薄膜晶体管的器件。 如图 2所示， 所述氧化物 TFT显示器件包括形成在衬底基板 10上的氧化物 薄膜晶体管 1， 所述氧化物薄膜晶体管 1包括櫥电极 2、 栅绝缘层〗1、 氧化 物有源层图案 5、 源电极 3和漏电极 4。 其中， 源电极 3和漏电极 4位于氧化 物有源层图案 5的下方， »电极 2位于源电极 3和漏电极 4的下方， 櫥绝缘 层 1位于栅电极 2和源电极 3、 漏电极 4之间。
本实施例的氧化物 TFT显示器件， 通过在氧化物有源层图案 5的下方形 成源电极 3、漏电极 4和栅电极 2， 电极 2位于源电极 3和漏电极 4的下 方， 使得形成源电极 3和漏电极 4的刻蚀工艺不会对氧化物有源层图案 5产 生破坏。 并且， 由于不需要在氧化物有源层图案 5上形成刻蚀阻挡层， 从而 省略了形成刻蚀阻挡层图案的光刻工序， 提高了氧化物薄膜晶体管阵列基板 的量产性， 降低了生产成本。
本实施例中， 在 *绝缘层 U与源电极 3、 漏电极 4之间形成有第一缓冲 层图案 8， 第一缓冲层图案 8对应于源电极 3及漏电极 4所在的区域， 并与 源电极 3及漏电极 4接触设置， 用于改善源电极 3和漏电极 4的粘附性和扩 散性。 此外， 在源电极 3、 漏电极 4与氧化物有源层图案 5之间也可以形成 有第二缓冲层图案 （图中未示出）， 并使其与源电极 3及漏电极 4接触设置。 其中， 所述第一缓冲层图案 8 和所述第二缓冲层图案的材料例如可以为 MoNb、 MoW或 MoTi， 源电极 3和漏电极 4的厚度例如可以为 200- 300iim。
进而， 为了改善栅电极 2的粘險性和扩散性， 在衬底基板 10与栅电极 2 之间形成有第三缓冲层图案（图中未示出）， 该第三缓冲层图案对应于栅电极 2所在的区域， 并与栅电极 2接触设置。 此外， 在栅电极 2与栅绝缘层 11之 间也可以形成有第四缓冲层图案（图中未示出），并使其与栅电极 2接触设置。 其中， 所述第三缓冲层图案和所述第四缓冲层图案的材料例如可以为 MoNb、 MoW或 MoTi, 欐电极 2的厚度例如可以为 200- 300nm。
此外， 栅绝缘层 11 的厚度例如可以为 150- 300nm， 極绝缘层 11可以为 二氧化硅层， 也可以为二氧化硅层、 氮氧化硅层和氮化硅层中任意两个膜层 的复合层， 或者， 还可以为二氧化硅层、 氮氧化硅层和氮化硅层三个膜层的 复合层。 并且， 例如将二氧化硅层靠近氧化物有源层图案 5设置， 这是因为
Si02中 H含量比较小， 不会对氧化物有源层图案 5的半导体特性产生影响。 氧化物有源层图案 5的厚度例如可以为 40- 50nm， 其材料为氧化铟锡或氧化 铟锌等氧化物半导体。
下面， 进一步以 ADS模式显示装置的氧化物 TFT阵列基板为例进行说 明。 如图 2所示， 氧化物 TFT阵列基板还包括公共电极 6、 狭缝像素电极 7' 和钝化层 12， 其中，狭缝像素电极 7'通过钝化层过孔 9与氧化物 TFT的漏电 极 4连接。 本实施例中， 公共电极 6的厚度为 70nrn左右， 并使其与狭缝像 素电极 7'的位置相对应， 丛而在氧化物 TFT 1的控制下， 使在狹缝像素电极 7'的边缘之间产生的电场以及在狭缝像素电极 7'与板状的公共电极 6之间产 生的电场形成多维电场， 用于驱动液晶分子的旋转。 本实施例中， 例如通过 一次构图工艺同时形成氧化物 TTT1的栅电极 2和公共电极 6，从而降低生产 成本， 提高量产性。
以上所述仅是本发明的几种实施方式， 应当指出， 对于本技术领域的普 通技术人员来说， 在不脱离本发明技术原理的前提下， 还可以做出若干改进 和替换， 这些改进和替换也应视为本发明的保护范围。

Claims

1 . 一种氧化物薄膜晶体管， 包括 »电极、栅绝缘层、氧化物有源层图案、 源电极和漏电极， 其特征在于， 源电极和漏电极位于氧化物有源层图案的下 方； 栅电极位于源电极和漏电极的下方； »绝缘层位于 »电极和源电极、 漏 电极之间。
2. 一种氧化物薄膜晶体管显示器件， 包括形成在衬底基板上的氧化物薄 膜晶体管， 所述氧化物薄膜晶体管包括栅电极、 櫥绝缘层、 氧化物有源层图 案、 源电极和漏电极， 其特征在于， 源电极和漏电极位于氧化物有源层图案 的下方； 栅电极位于源电极和漏电极的下方； »绝缘层位于栅电极和源电极、 漏电极之间。
3. 根据权利要求 2所述的氧化物薄膜晶体管显示器件， 其特征在于， 在 »绝缘层与源电极、 漏电极之间形成有第一缓冲层图案， 所述第一缓冲层图 案对应于源电极和漏电极所在的区域；
在源电极、 漏电极与氧化物有源层图案之间形成有第二缓冲层图案， 所 述第二缓冲层图案对应于源电极和漏电极所在的区域；
所述第一缓冲层图案和所述第二缓祌层图案与源电极及漏电极接触设 置。
4. 根据权利要求 3所述的氧化物薄膜晶体管显示器件， 其特征在于， 所 述第一缓冲层图案和所述第二缓祌层图案的村料为 MoNb、 MoW或 MoTi。
5. 根据权利要求 2所述的氧化物薄膜晶体管显示器件， 其特征在于， 在 栅电极与衬底基板之间形成有第三缓冲层图案， 所述第三缓冲层图案对应于 »电极所在的区域；
在栅电极与栅绝缘层之间形成有第四缓冲层图案， 所述第四缓冲层图案 对应于栅电极所在的区域；
所述第三缓冲层图案和所述第四缓冲层图案与栅电极接触设置。
6. 根据权利要求 5所述的显示器件， 其特征在于， 所述第三缓冲层图案 和所述第四缓冲层图案的材料为 MoNb、 MoW或 MoTi。
7. 根据权利要求 2 6任一项所述的氧化物薄膜晶体管显示器件， 其特征 在于， 所述栅绝缘层为二氧化硅层， 或者为二氧化硅层、 氮氧化硅层和氮化 硅层中任意两个膜层的复合层， 或者为二氧化硅层、 氮氧化硅层和氮化硅层 三个膜层的复合层。
8. 根据权利要求 7所述的氧化物薄膜晶体管显示器件， 其特征在于， 二 氧化硅层靠近氧化物有源层图案设置。
9. 一种氧化物薄膜晶体管阵列基板的制造方法， 包括在衬底基板上形成 氧化物薄膜晶体管的步骤， 其中， 所述氧化物薄膜晶体管包括 »电极、 栅绝 缘层、 氧化物有源层图案、 源电极和漏电极， 其特征在于， 所述在衬底基板 上形成氧化物薄膜晶体管的步骤包括：
在衬底基板上形成栅电极；
在形成了栅电极的衬底基板上形成栅绝缘层；
在形成了栅绝缘层的衬底基板上形成源电极和漏电极； 以及
在形成了源电极和漏电极的衬底基板上形成氧化物有源层图案。
10. 根据权利要求 9 所述的制造方法， 其特征在于， 所述制造方法还包 括：
在低于 200Ό环境下， 在氧化物有源层图案上形成钝化层。
11. 根据权利要求 9 所述的制造方法， 其特征在于， 所述在形成了源电 极和漏电极的衬底基板上形成氧化物有源层图案的步骤之前， 还包括如下歩 骤：
对源电极和漏电极的表面进行等离子处理。
12. 根据权利要求 11所述的制造方法， 其特征在于， 采) ¾笑气对源电极 和漏电极的表面进行等离子处理。
13. 根据权利要求 9- 12任一项所述的制造方法， 其特征在于， 还包括在 衬底基板上形成栅电极的同时， 在衬底基板上形成公共电极的歩骤， 包括： 在衬底基板上依次形成透明导电层和栅金属层；
在栅金属层上涂覆一层光刻胶；
采用半色调或灰色调掩膜版对光刻胶进行曝光、 显影， 使光刻胶形成光 刻胶不保留区域、 光刻胶完全保留区域和光刻胶半保留区域； 其中， 所述光 刻胶完全保留区域包括栅电极所在的区域， 所述光刻胶半保留区域包括公共 电极所在的区域， 所述光刻胶不保留区域对应于其它区域；
通过第一次刻馊工艺完全刻馊掉光刻胶不保留区域的栅金属层和透明导 甲 j¾
通过灰化工艺去除光刻胶半保留区域的光刻胶；
通过第二次刻蚀工艺完全刻蚀掉光刻胶半保留区域的栅金属层， 形成包 括公共电极的图案； 以及
剥离剩余的光刻胶， 形成包括栅电极的图案。
14. 根据权利要求 9-12任一项所述的制造方法， 其特征在于， 所述在形 成了櫥绝缘层的衬底基板上形成源电极和漏电极的步骤包括：
在衬底基板上依次形成第一缓冲层、 源漏金属层和第二缓冲层； 在所述第二缓冲层上涂覆光刻胶；
对光刻胶进行曝光、 显影， 形成光刻胶保留区域和光刻胶不保留区域， 其中， 所述光刻胶保留区域包括源电极和漏电极所在的区域， 所述光刻胶不 保留区域对应于其它区域；
通过第四次刻蚀工艺完全刻蚀掉光刻胶不保留区域的第二缓祌层、 源漏 金属层和第一缓祌层； 以及
剥离剩余的光刻胶， 形成包括源电极和漏电极的图案。
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