WO2016173012A1 - 薄膜晶体管阵列基板及其制作方法 - Google Patents

薄膜晶体管阵列基板及其制作方法 Download PDF

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WO2016173012A1
WO2016173012A1 PCT/CN2015/079421 CN2015079421W WO2016173012A1 WO 2016173012 A1 WO2016173012 A1 WO 2016173012A1 CN 2015079421 W CN2015079421 W CN 2015079421W WO 2016173012 A1 WO2016173012 A1 WO 2016173012A1
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layer
gate
source
oxide semiconductor
gate insulating
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PCT/CN2015/079421
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French (fr)
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吕晓文
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深圳市华星光电技术有限公司
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Priority to US14/763,818 priority Critical patent/US9806106B2/en
Publication of WO2016173012A1 publication Critical patent/WO2016173012A1/zh

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Definitions

  • the present invention relates to the field of flat panel displays, and in particular to a thin film transistor array substrate and a method of fabricating the same.
  • the active matrix flat panel display has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the flat panel display devices on the existing market include a liquid crystal display (LCD) and an organic light-emitting diode (OLED).
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • the LCD includes a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates, and control the liquid crystal molecules to change direction by energizing or not the glass substrate, and refract the light of the backlight module to produce a picture.
  • OLED has many characteristics such as self-illumination, high brightness, wide viewing angle, high contrast, flexibility, low energy consumption, etc., and has been widely concerned as a new generation of display mode, has gradually replaced the traditional liquid crystal display, is widely used in mobile phones. Screen, computer monitor, full color TV, etc.
  • OLED display technology is different from traditional liquid crystal display technology. It does not require a backlight. It uses a very thin coating of organic materials and a glass substrate. When there is current, these organic materials will emit light.
  • Thin Film Transistor Array substrates are widely used in LCDs and OLEDs, and generally include a glass substrate and a thin film transistor and a storage capacitor formed on the glass substrate.
  • the storage capacitor plays a important role in maintaining the potential of the coupling capacitor in the thin film transistor array substrate. In general, we hope that the capacitor is better.
  • the storage capacitor is generally made of a metal-interposed insulating layer, the metal electrode is opaque, and the larger the storage capacitance, the lower the aperture ratio.
  • Reducing the thickness of the insulating layer can increase the size of the storage capacitor, and on the basis of this, the relative area of the metal plate can be appropriately reduced, which is a method for increasing the storage capacitance and increasing the aperture ratio.
  • FIG. 1 is a cross-sectional structural diagram of a conventional thin film transistor array substrate, including a substrate 100 and a thin film transistor and a storage capacitor provided on the substrate 100.
  • the gate insulating layer 300 and the etch stop layer 500 are interposed between the first plate 310 and the second plate 320 of the storage capacitor. Since the gate insulating layer 300 and the etch stop layer 500 have a certain thickness, the insulating layer is formed. Thicker, resulting in smaller storage capacitors, requires a larger relative area to get the set capacitance value, resulting in lower device aperture.
  • the present invention provides a thin film transistor array substrate including a substrate, and a thin film transistor and a storage capacitor formed on the substrate;
  • the storage capacitor includes a first plate on the substrate, a gate insulating layer or an etch stop layer over the first plate, and a second plate over the gate insulating layer or the etch barrier.
  • the thin film transistor array substrate includes a substrate, a first gate and a second gate disposed on the substrate, and a first plate located on a side of the second gate away from the first gate.
  • a first gate electrode, a second gate electrode, a first electrode plate, and a gate insulating layer on the substrate respectively disposed on the gate insulating layer above the first gate electrode and the second gate electrode
  • a first via hole is disposed on the gate insulating layer corresponding to a side of the second gate adjacent to the first gate, and the passivation layer and the flat layer are corresponding to the second source.
  • a via, a third via is disposed on the pixel defining layer corresponding to the pixel electrode layer; the first source and the first drain are in contact with the first oxide semiconductor layer, and the second The source and the second drain are in contact with the second oxide semiconductor layer, the first source is in contact with the second gate via the first via, and the pixel electrode layer is via The second via is in contact with the second source, and the third via exposes a portion of the pixel electrode layer;
  • the first gate, the second gate, the gate insulating layer, the first oxide semiconductor layer, the second oxide semiconductor layer, the etch barrier layer, the first source, the first drain, the second source, And the second drain constitutes a thin film transistor; the first electrode plate, the second electrode plate, and the gate insulating layer between the first electrode plate and the second electrode plate constitute a storage capacitor.
  • the thin film transistor array substrate includes a substrate, a first gate and a second gate disposed on the substrate, and a first plate located on a side of the second gate away from the first gate.
  • a first via hole is disposed on the gate insulating layer corresponding to a side of the second gate adjacent to the first gate, and the passivation layer and the flat layer are corresponding to the second source.
  • a via, a third via is disposed on the pixel defining layer corresponding to the pixel electrode layer; the first source and the first drain are in contact with the first oxide semiconductor layer, and the second The source and the second drain are in contact with the second oxide semiconductor layer, the first source is in contact with the second gate via the first via, and the pixel electrode layer is via The second via is in contact with the second source, and the third via exposes a portion of the pixel electrode layer;
  • the first gate, the second gate, the gate insulating layer, the first oxide semiconductor layer, the second oxide semiconductor layer, the etch barrier layer, the first source, the first drain, the second source, And the second drain constitutes a thin film transistor; the first plate, the second plate, and the etch barrier layer between the first plate and the second plate constitute a storage capacitor.
  • the gate insulating layer is different from the material of the etch barrier layer.
  • the material of the gate insulating layer is Al 2 O 3
  • the material of the etching barrier layer is SiOx.
  • the material of the gate insulating layer is SiOx, and the material of the etch barrier layer is Al 2 O 3 .
  • the invention also provides a method for fabricating a thin film transistor array substrate, comprising the following steps:
  • Step 1 Providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first gate, a second gate, and the second gate a first plate away from a side of the first gate;
  • Step 2 depositing and patterning a gate insulating layer on the first metal layer to obtain a first via hole located on a side of the second gate adjacent to the first gate;
  • Step 3 depositing and patterning an oxide semiconductor layer on the gate insulating layer, respectively obtaining a first oxide semiconductor layer above the first gate and a second above the second gate An oxide semiconductor layer;
  • Step 4 depositing an etch barrier layer on the oxide semiconductor layer, and patterning the etch barrier layer to expose both side regions of the first oxide semiconductor layer and the second oxide semiconductor layer And simultaneously etching away the etch barrier layer above the first plate;
  • Step 5 depositing a second metal layer on the etch barrier layer and the gate insulating layer, and patterning the second metal layer to obtain a first source located above the first gate And a first drain, a second source above the second gate, and a second drain, a second plate above the first plate;
  • the first source and the first drain are in contact with both side regions of the first oxide semiconductor layer, and the second source, the second drain, and the second oxide semiconductor layer The two sides are in contact with each other, and the first source is in contact with the second gate via the first via;
  • Step 6 sequentially forming a passivation layer, a planarization layer, a pixel electrode layer, a pixel definition layer, and a photoresist spacer on the second metal layer and the etch barrier layer;
  • a second via hole is formed on the pixel defining layer corresponding to the second source, and a third via hole is formed on the pixel defining layer corresponding to the pixel electrode layer;
  • the second via is in contact with the second source, and the third via exposes a portion of the pixel electrode layer.
  • the gate insulating layer and the etch barrier layer are formed of different materials.
  • the gate insulating layer is formed using Al 2 O 3
  • the etch barrier layer is formed using SiO x .
  • the gate insulating layer is formed using SiOx, and the etch barrier layer is formed using Al 2 O 3 .
  • the invention also provides a method for fabricating a thin film transistor array substrate, comprising the following steps:
  • Step 1 Providing a substrate to deposit a first metal layer on the substrate, and patterning the first metal layer to obtain a first gate, a second gate, and a second gate a first plate on one side of the first gate;
  • Step 2 depositing and patterning a gate insulating layer on the first metal layer to obtain a first via hole located on a side of the second gate adjacent to the first gate;
  • Step 3 depositing and patterning an oxide semiconductor layer on the gate insulating layer, respectively obtaining a first oxide semiconductor layer above the first gate and a second above the second gate An oxide semiconductor layer;
  • Step 4 depositing an etch barrier layer on the oxide semiconductor layer, and the etch stop layer Performing a patterning process to expose both side regions of the first oxide semiconductor layer and the second oxide semiconductor layer, respectively, while etching the etch barrier layer over the first electrode plate;
  • Step 5 depositing a second metal layer on the etch barrier layer and the gate insulating layer, and patterning the second metal layer to obtain a first source located above the first gate And a first drain, a second source above the second gate, and a second drain, a second plate above the first plate;
  • the first source and the first drain are in contact with both side regions of the first oxide semiconductor layer, and the second source, the second drain, and the second oxide semiconductor layer The two sides are in contact with each other, and the first source is in contact with the second gate via the first via;
  • Step 6 sequentially forming a passivation layer, a planarization layer, a pixel electrode layer, a pixel definition layer, and a photoresist spacer on the second metal layer and the etch barrier layer;
  • a second via hole is formed on the pixel defining layer corresponding to the second source, and a third via hole is formed on the pixel defining layer corresponding to the pixel electrode layer;
  • the second via is in contact with the second source, and the third via exposes a portion of the pixel electrode layer;
  • the gate insulating layer and the etch barrier layer are formed of different materials
  • the gate insulating layer is formed of Al 2 O 3
  • the etching stopper layer is formed by using SiO x .
  • the capacitor in a thin film transistor array substrate, only one of a gate insulating layer or an etch barrier layer exists between two electrode plates of a storage capacitor, and the thickness of the insulating layer between the storage capacitors is relatively thick. Thin, the capacitor has a relatively small relative area and a high aperture ratio.
  • the method for fabricating the thin film transistor array substrate of the present invention when etching the etching stopper layer, the portion of the etching stopper layer above the first electrode plate of the storage capacitor is etched away, thereby reducing the thickness of the insulating layer between the storage capacitors and reducing The relative area of the capacitor is increased, and the aperture ratio is increased.
  • the etching gas is blunt to the gate insulating layer, and the lower layer is avoided during the etching of the etch barrier layer.
  • the gate insulating layer causes damage, thereby ensuring a better storage capacitor.
  • FIG. 1 is a schematic cross-sectional structural view of a conventional thin film transistor array substrate
  • FIG. 2 is a cross-sectional structural view showing a first embodiment of a thin film transistor array substrate of the present invention
  • FIG. 3 is a cross-sectional structural view showing a second embodiment of a thin film transistor array substrate of the present invention.
  • FIG. 4 is a flow chart of a method of fabricating a thin film transistor array substrate of the present invention.
  • the present invention provides a thin film transistor array substrate including a substrate 1 and a thin film transistor and a storage capacitor formed on the substrate 1 .
  • the storage capacitor includes a first electrode plate 31 on the substrate 1, a gate insulating layer 3 or an etch barrier layer 5 on the first electrode plate 31, and is located above the gate insulating layer 3 or the etch barrier layer 5. Second plate 32.
  • FIG. 2 is a schematic structural diagram of a first embodiment of a thin film transistor array substrate according to the present invention, including a substrate 1, a first gate 21, a second gate 22 disposed on the substrate 1, and located at the The second gate 22 is away from the first plate 31 on the first gate 21 side, the gate insulation provided on the first gate 21, the second gate 22, the first plate 31, and the substrate 1 a layer 3, a first oxide semiconductor layer 41 and a second oxide semiconductor layer 42 disposed on the gate insulating layer 3 above the first gate 21 and the second gate 22, respectively a second plate 32 disposed on the gate insulating layer 3 over the first plate 31, and disposed on the first oxide semiconductor layer 41, the second oxide semiconductor layer 42, and the gate insulating layer 3 An etch barrier layer 5, a first source 61, a first drain 62, a second source 63, and a first source 62 disposed on the etch barrier layer 5 above the first gate 21 and the second gate 22, respectively
  • the second drain 64 is disposed on the first source 61, the first drain 62,
  • a first via 51 is disposed on the gate insulating layer 3 corresponding to a side of the second gate 22 adjacent to the first gate 21, and the passivation layer 71 and the flat layer 72 correspond to the second source a second via hole 52 is disposed above the pole 63, and a third via hole 53 is disposed on the pixel defining layer 9 corresponding to the pixel electrode layer 81; the first source 61, the first drain 62 and the The first oxide semiconductor layer 41 is in contact, the second source 63, and the second drain 64 are in contact with the second oxide semiconductor layer 42, and the first source 61 is passed through the first
  • the hole 51 is in contact with the second gate 22,
  • the pixel electrode layer 81 is in contact with the second source 63 via the second via 52, and the third via 53 exposes a portion of the pixel electrode layer 81.
  • the pole 62, the second source 63, and the second drain 64 constitute a thin film transistor; the first plate 31, the second plate 32, and the first plate 31 and the second plate 32 are located between the first plate 31 and the second plate 32.
  • the gate insulating layer 3 constitutes a storage capacitor.
  • the thickness of the insulating layer between the storage capacitors is thin, the relative area of the capacitor is small, and the opening ratio is high.
  • the gate insulating layer 3 and the etch barrier layer 5 are formed of different materials; for example, the gate insulating layer 3 is formed of Al 2 O 3 (alumina), and the etch barrier layer 5 is made of SiOx ( Silicon oxide is formed, or the gate insulating layer 3 is formed of SiOx, and the etch barrier layer 5 is formed of Al 2 O 3 ; the portion of the etch barrier layer 5 above the first plate 31 is formed during fabrication. Etched off, since the gate insulating layer 3 and the etch barrier layer 5 are formed of different materials, the etching gas for etching the etch barrier layer 5 is insensitive to the gate insulating layer 3, and therefore, the etching stopper layer 5 is etched. In the process, the underlying gate insulating layer 3 is not damaged, thereby maintaining good device characteristics.
  • FIG. 3 is a schematic structural view of a second embodiment of a thin film transistor array substrate according to the present invention, including a substrate 1, a first gate 21, a second gate 22 disposed on the substrate 1, and located at the a first electrode plate 31 on a side of the second gate 22 away from the first gate 21, a gate insulating layer 3 disposed on the first gate 21, the second gate 22, and the substrate 1, respectively a first oxide semiconductor layer 41 and a second oxide semiconductor layer 42 disposed on the gate insulating layer 3 over the first gate 21 and the second gate 22, and the first oxide semiconductor layer 41.
  • the second drain 64 is provided on the first source 61, the first drain 62, the second source 63, the second drain 64, and the second plate 32 to cover the passivation layer 5 a flat layer 72 disposed on the passivation layer 71, a pixel electrode layer 81 disposed on the flat layer 72, a pixel defining layer 9 disposed on the flat layer 72 and the pixel electrode layer 81, and A photoresist spacer 91 disposed on the pixel defining layer 9.
  • a first via 51 is disposed on the gate insulating layer 3 corresponding to a side of the second gate 22 adjacent to the first gate 21, and the passivation layer 71 and the flat layer 72 correspond to the second source a second via 52 is disposed above the pole 63, and the pixel defining layer 9 is provided with a corresponding upper portion of the pixel electrode layer 81.
  • the first source 61 and the first drain 62 are in contact with the first oxide semiconductor layer 41, the second source 63, and the second drain 64 and the second
  • the oxide semiconductor layer 42 is in contact with each other, the first source 61 is in contact with the second gate 22 via the first via 51, and the pixel electrode layer 81 is connected to the second via 52 via the second via 52
  • the second source 63 is in contact, and the third via 53 exposes a portion of the pixel electrode layer 81.
  • the pole 62, the second source 63, and the second drain 64 constitute a thin film transistor; the first plate 31, the second plate 32, and the first plate 31 and the second plate 32 are located between the first plate 31 and the second plate 32.
  • the etch stop layer 5 constitutes a storage capacitor.
  • the portion of the gate insulating layer 3 above the first electrode plate 31 is etched away during the fabrication process, so the insulation between the storage capacitors is The layer thickness is thin, the relative area of the capacitor is small, and the aperture ratio is high.
  • the gate insulating layer 3 exists between the two electrode plates of the storage capacitor, that is, the first embodiment described above. Because, in the second embodiment, if the portion of the gate insulating layer 3 over the first plate 31 is etched away, the first plate 31 of the storage capacitor is not protected in the post-process, and is easily damaged, such as Corrosion, etc.
  • the gate insulating layer or the etch barrier layer exists between the two electrode plates of the storage capacitor, the insulating layer between the storage capacitors is thin, the relative area of the capacitor is small, and the film has a relatively high capacitance.
  • the aperture ratio is only one of the gate insulating layer or the etch barrier layer exists between the two electrode plates of the storage capacitor, the insulating layer between the storage capacitors is thin, the relative area of the capacitor is small, and the film has a relatively high capacitance.
  • the present invention further provides a method for fabricating a thin film transistor array substrate, comprising the following steps:
  • Step 1 Providing a substrate 1 , depositing a first metal layer on the substrate 1 , and patterning the first metal layer to obtain a first gate 21 , a second gate 22 , and The second gate 22 is away from the first plate 31 on the side of the first gate 21 .
  • the substrate 1 is a glass or plastic substrate.
  • Step 2 Depositing and patterning the gate insulating layer 3 on the first metal layer to obtain a first via 51 located above the side of the second gate 22 close to the first gate 21.
  • Step 3 depositing and patterning an oxide semiconductor layer on the gate insulating layer 3, respectively obtaining a first oxide semiconductor layer 41 over the first gate electrode 21, and located at the second gate electrode 22 The upper second oxide semiconductor layer 42.
  • Step 4 depositing an etch barrier layer 5 on the oxide semiconductor layer, and patterning the etch barrier layer 5 to expose the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42 respectively.
  • the two side regions at the same time, will etch the barrier layer 5 above the first plate 31 Partially etched away.
  • the etch barrier layer 5 and the gate insulating layer 3 are formed of different materials.
  • the gate insulating layer 3 is formed of Al 2 O 3
  • the etch barrier layer 5 is formed of SiO x
  • the gate insulating layer 3 is formed of SiOx
  • the etch barrier layer 5 is formed of Al 2 O 3 .
  • the etching gas for etching the etching stopper layer 5 is blunt to the gate insulating layer 3. Therefore, the underlying gate insulating layer 3 is not damaged during the etching of the etch barrier layer 5, thereby maintaining good device characteristics.
  • Step 5 depositing a second metal layer on the etch barrier layer 5 and the gate insulating layer 3, and patterning the second metal layer to obtain a first portion above the first gate electrode 21 a source 61 and a first drain 62, a second source 63 above the second gate 22, and a second drain 64, and a second plate 32 above the first plate 31 .
  • the first source 61 and the first drain 62 are in contact with both side regions of the first oxide semiconductor layer 41, the second source 63, and the second drain 64 and the second The side regions of the oxide semiconductor layer 42 are in contact with each other, and the first source 61 is in contact with the second gate 22 via the first via 51.
  • Step 6 Form a passivation layer 71, a flat layer 72, a pixel electrode layer 81, a pixel defining layer 9, and a photoresist spacer 91 on the second metal layer and the etching stopper layer 5 in this order.
  • the passivation layer 71 and the flat layer 72 are formed with a second via hole 52 corresponding to the second source 63, and a third via hole 53 is formed on the pixel defining layer 9 corresponding to the pixel electrode layer 81;
  • the pixel electrode layer 81 is in contact with the second source 63 via the second via 52, and the third via 53 exposes a portion of the pixel electrode layer 81.
  • the passivation layer 71, the planarization layer 72, the pixel electrode layer 81, the pixel definition layer 9, and the photoresist spacer 91 can be made by using the prior art.
  • the portion of the gate insulating layer 3 on the first plate 31 may be selectively etched so that only the etching barrier layer 5 exists between the two electrode plates of the storage capacitor.
  • An insulating layer reduces the thickness of the insulating layer between the storage capacitors, reduces the relative area of the capacitor, and increases the aperture ratio; however, the disadvantage of this method is that there is no protection on the first plate 31 of the storage capacitor in the post process. It is easily damaged, such as corrosion.
  • the portion of the etching stopper layer above the first electrode plate of the storage capacitor is etched away, thereby reducing the thickness of the insulating layer between the storage capacitors and reducing the capacitance.
  • the relative area increases the aperture ratio; and by using different materials for the gate insulating layer and the etch barrier layer, the etching gas is blunt to the gate insulating layer, thereby avoiding the gate to the lower layer during the etching of the etch barrier layer.
  • the pole insulation layer causes damage, thus ensuring a better storage capacitor.
  • the present invention provides a thin film transistor array substrate in which only one of the gate insulating layer or the etch barrier layer is present between the two electrode plates of the storage capacitor, and the insulating layer between the storage capacitors is thin.
  • the capacitance has a relatively small relative area and a high aperture ratio.
  • the method for fabricating the thin film transistor array substrate of the present invention when etching the etching stopper layer, the portion of the etching stopper layer above the first electrode plate of the storage capacitor is etched away, thereby reducing the thickness of the insulating layer between the storage capacitors and reducing The relative area of the capacitor is increased, and the aperture ratio is increased.
  • the etching gas is blunt to the gate insulating layer, and the lower layer is avoided during the etching of the etch barrier layer.
  • the gate insulating layer causes damage, thereby ensuring a better storage capacitor.

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Abstract

一种薄膜晶体管阵列基板及其制作方法，包括：基板(1)，及形成于基板(1)上的薄膜晶体管和存储电容；该存储电容包括位于基板(1)上的第一极板(31)，位于第一极板(31)之上的栅极绝缘层(3)或者蚀刻阻挡层(5)，位于栅极绝缘层(3)或者蚀刻阻挡层(5)之上的第二极板(32)；存储电容的两电极板之间只存在栅极绝缘层(3)或者蚀刻阻挡层(5)一层绝缘层，存储电容的绝缘层厚度较薄，电容相对面积较小，开口率较高。

Description

薄膜晶体管阵列基板及其制作方法 技术领域
本发明涉及平面显示器领域，尤其涉及一种薄膜晶体管阵列基板及其制作方法。
背景技术
主动矩阵平面显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有市场上的平面显示器装置包括液晶显示装置(Liquid Crystal Display，LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)。
LCD包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，通过玻璃基板通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
OLED具备自发光、高亮度、宽视角、高对比度、可挠曲、低能耗等特性，因此受到广泛的关注，并作为新一代的显示方式，已开始逐渐取代传统液晶显示器，被广泛应用在手机屏幕、电脑显示器、全彩电视等。OLED显示技术与传统的液晶显示技术不同，无需背光灯，采用非常薄的有机材料涂层和玻璃基板，当有电流通过时，这些有机材料就会发光。
薄膜晶体管阵列基板(Thin Film Transistor Array substrate)在LCD和OLED中被广泛应用，一般包括玻璃基板及形成于玻璃基板上的薄膜晶体管及存储电容。
存储电容在薄膜晶体管阵列基板中扮演着保持电位，降低耦合电容分压等重要作用，一般而言，我们希望电容大点比较好。电容大小的计算公式为C＝εS/D其中S代表面积，D代表绝缘层厚度，改变存储电容的大小，一般有以下几种方法，1.选用介电常数较大的绝缘材料。2.增大面积。3.降低绝缘层厚度。
一般来说，增大两金属板的相对面积会增大电容，但是由于存储电容一般以金属夹置绝缘层制成，金属电极是不透光的，存储电容越大，开口率就越低。而降低绝缘层厚度，既能增大存储电容大小，同时在此基础上，可以适当减小金属板相对面积，是较好的增加存储电容，提高开口率的方法。
请参阅图1，为一种现有薄膜晶体管阵列基板的剖面结构示意图，包括 基板100、及设于所述基板100上的薄膜晶体管和存储电容。存储电容的第一极板310与第二极板320中间夹置有栅极绝缘层300和蚀刻阻挡层500，因为栅极绝缘层300和蚀刻阻挡层500都有一定的厚度，就使得绝缘层比较厚，造成存储电容较小，需要较大的相对面积才能得到设定的电容值，造成器件开口率降低。
发明内容
本发明的目的在于提供一种薄膜晶体管阵列基板，具有较大存储电容的同时，具有较高开口率。
本发明的目的在于提供一种薄膜晶体管阵列基板的制作方法，可以增大存储电容的同时，提高开口率。
为实现上述目的，本发明提供一种薄膜晶体管阵列基板，包括基板，及形成于基板上的薄膜晶体管和存储电容；
所述存储电容包括位于基板上的第一极板，位于第一极板之上的栅极绝缘层或者蚀刻阻挡层，位于栅极绝缘层或者蚀刻阻挡层之上的第二极板。
所述薄膜晶体管阵列基板包括基板、设于所述基板上的第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板、设于所述第一栅极、第二栅极、第一极板、及基板上的栅极绝缘层、分别位于所述第一栅极与第二栅极上方设于所述栅极绝缘层上的第一氧化物半导体层与第二氧化物半导体层、位于所述第一极板上方设于所述栅极绝缘层上的第二极板、设于所述第一氧化物半导体层、第二氧化物半导体层、及栅极绝缘层上的蚀刻阻挡层、分别位于所述第一栅极与第二栅极上方设于所述蚀刻阻挡层上的第一源极、第一漏极、第二源极、及第二漏极、设于所述第一源极、第一漏极、第二源极、第二漏极、及第二极板上方覆盖所述蚀刻阻挡层的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的像素电极层、设于所述平坦层与像素电极层上的像素定义层、及设于所述像素定义层上的光阻间隙物；
所述栅极绝缘层上对应所述第二栅极靠近第一栅极一侧的上方设有第一过孔，所述钝化层与平坦层对应所述第二源极上方设有第二过孔，所述像素定义层上对应所述像素电极层上方设有第三过孔；所述第一源极、第一漏极与所述第一氧化物半导体层相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触，所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层；
所述第一栅极、第二栅极、栅极绝缘层、第一氧化物半导体层、第二氧化物半导体层、蚀刻阻挡层、第一源极、第一漏极、第二源极、及第二漏极构成薄膜晶体管；所述第一极板、第二极板、及位于所述第一极板与第二极板之间的栅极绝缘层构成存储电容。
所述薄膜晶体管阵列基板包括基板、设于所述基板上的第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板、设于所述第一栅极、第二栅极、及基板上的栅极绝缘层、分别位于所述第一栅极与第二栅极上方设于所述栅极绝缘层上的第一氧化物半导体层与第二氧化物半导体层、设于所述第一氧化物半导体层、第二氧化物半导体层、栅极绝缘层、及第一极板上的蚀刻阻挡层、位于所述第一极板上方设于所述蚀刻阻挡层上的第二极板、分别位于所述第一栅极与第二栅极上方设于所述蚀刻阻挡层上的第一源极、第一漏极、第二源极、及第二漏极、设于所述第一源极、第一漏极、第二源极、第二漏极、及第二极板上方覆盖所述蚀刻阻挡层的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的像素电极层、设于所述平坦层与像素电极层上的像素定义层、及设于所述像素定义层上的光阻间隙物；
所述栅极绝缘层上对应所述第二栅极靠近第一栅极一侧的上方设有第一过孔，所述钝化层与平坦层对应所述第二源极上方设有第二过孔，所述像素定义层上对应所述像素电极层上方设有第三过孔；所述第一源极、第一漏极与所述第一氧化物半导体层相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触，所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层；
所述第一栅极、第二栅极、栅极绝缘层、第一氧化物半导体层、第二氧化物半导体层、蚀刻阻挡层、第一源极、第一漏极、第二源极、及第二漏极构成薄膜晶体管；所述第一极板、第二极板、及位于所述第一极板与第二极板之间的蚀刻阻挡层构成存储电容。
所述栅极绝缘层与蚀刻阻挡层的材料不同。
所述栅极绝缘层的材料为Al2O3，所述蚀刻阻挡层的材料为SiOx。
所述栅极绝缘层的材料为SiOx，所述蚀刻阻挡层的材料为Al2O3。
本发明还提供一种薄膜晶体管阵列基板的制作方法，包括以下步骤：
步骤1、提供一基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板；
步骤2、在所述第一金属层上沉积并图案化栅极绝缘层，得到位于所述第二栅极靠近第一栅极一侧的上方的第一过孔；
步骤3、在所述栅极绝缘层上沉积并图案化氧化物半导体层，分别得到位于所述第一栅极上方的第一氧化物半导体层、及位于所述第二栅极上方的第二氧化物半导体层；
步骤4、在所述氧化物半导体层上沉积蚀刻阻挡层，对所述蚀刻阻挡层进行图案化处理，分别暴露出所述第一氧化物半导体层、及第二氧化物半导体层的两侧区域，同时将位于第一极板上方的蚀刻阻挡层部分刻蚀掉；
步骤5、在所述蚀刻阻挡层、及栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，分别得到位于所述第一栅极上方的第一源极、及第一漏极、位于所述第二栅极上方的第二源极、及第二漏极、位于所述第一极板上方的第二极板；
所述第一源极、及第一漏极与所述第一氧化物半导体层的两侧区域相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层的两侧区域相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触；
步骤6、依次在所述第二金属层、及蚀刻阻挡层上形成钝化层、平坦层、像素电极层、像素定义层、及光阻间隙物；
所述钝化层与平坦层对应所述第二源极上方形成有第二过孔，所述像素定义层上对应所述像素电极层上方形成有第三过孔；所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层。
所述栅极绝缘层与蚀刻阻挡层采用不同的材料形成。
所述栅极绝缘层采用Al2O3形成，所述蚀刻阻挡层采用SiOx形成。
所述栅极绝缘层采用SiOx形成，所述蚀刻阻挡层采用Al2O3形成。
本发明还提供一种薄膜晶体管阵列基板的制作方法，包括以下步骤：
步骤1、提供一基板在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板；
步骤2、在所述第一金属层上沉积并图案化栅极绝缘层，得到位于所述第二栅极靠近第一栅极一侧的上方的第一过孔；
步骤3、在所述栅极绝缘层上沉积并图案化氧化物半导体层，分别得到位于所述第一栅极上方的第一氧化物半导体层、及位于所述第二栅极上方的第二氧化物半导体层；
步骤4、在所述氧化物半导体层上沉积蚀刻阻挡层，对所述蚀刻阻挡层 进行图案化处理，分别暴露出所述第一氧化物半导体层、及第二氧化物半导体层的两侧区域，同时将位于第一极板上方的蚀刻阻挡层刻蚀掉；
步骤5、在所述蚀刻阻挡层、及栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，分别得到位于所述第一栅极上方的第一源极、及第一漏极、位于所述第二栅极上方的第二源极、及第二漏极、位于所述第一极板上方的第二极板；
所述第一源极、及第一漏极与所述第一氧化物半导体层的两侧区域相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层的两侧区域相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触；
步骤6、依次在所述第二金属层、及蚀刻阻挡层上形成钝化层、平坦层、像素电极层、像素定义层、及光阻间隙物；
所述钝化层与平坦层对应所述第二源极上方形成有第二过孔，所述像素定义层上对应所述像素电极层上方形成有第三过孔；所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层；
其中，所述栅极绝缘层与蚀刻阻挡层采用不同的材料形成；
其中，所述栅极绝缘层采用Al2O3形成，所述蚀刻阻挡层采用SiOx形成。
本发明的有益效果：本发明提供的一种薄膜晶体管阵列基板，存储电容的两电极板之间只存在栅极绝缘层或者蚀刻阻挡层之中的一层绝缘层，存储电容间绝缘层厚度较薄，电容相对面积较小，具有较高的开口率。本发明的薄膜晶体管阵列基板的制作方法，在对蚀刻阻挡层进行蚀刻时，将蚀刻阻挡层位于存储电容的第一极板上方的部分蚀刻掉，从而降低了存储电容间绝缘层厚度，减小了电容相对面积，提高了开口率；并通过对栅极绝缘层和蚀刻阻挡层采用不同的材料，使蚀刻气体对栅极绝缘层呈钝性，避免了在蚀刻蚀刻阻挡层的过程中对下层的栅极绝缘层造成破坏，从而保证得到较理想的存储电容。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有薄膜晶体管阵列基板的剖面结构示意图；
图2为本发明薄膜晶体管阵列基板第一实施例的剖面结构示意图；
图3为本发明薄膜晶体管阵列基板第二实施例的剖面结构示意图；
图4为本发明薄膜晶体管阵列基板制作方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2至图3，本发明提供一种薄膜晶体管阵列基板，包括基板1，及形成于基板1上的薄膜晶体管和存储电容。
所述存储电容包括位于基板1上的第一极板31，位于第一极板31之上的栅极绝缘层3或者蚀刻阻挡层5，位于栅极绝缘层3或者蚀刻阻挡层5之上的第二极板32。
如图2所示，为本发明的薄膜晶体管阵列基板第一实施例的结构示意图，包括基板1、设于所述基板1上的第一栅极21、第二栅极22、及位于所述第二栅极22远离第一栅极21一侧的第一极板31、设于所述第一栅极21、第二栅极22、第一极板31、及基板1上的栅极绝缘层3、分别位于所述第一栅极21与第二栅极22上方设于所述栅极绝缘层3上的第一氧化物半导体层41与第二氧化物半导体层42、位于所述第一极板31上方设于所述栅极绝缘层3上的第二极板32、设于所述第一氧化物半导体层41、第二氧化物半导体层42、及栅极绝缘层3上的蚀刻阻挡层5、分别位于所述第一栅极21与第二栅极22上方设于所述蚀刻阻挡层5上的第一源极61、第一漏极62、第二源极63、及第二漏极64、设于所述第一源极61、第一漏极62、第二源极63、第二漏极64、及第二极板32上方覆盖所述蚀刻阻挡层5的钝化层71、设于所述钝化层71上的平坦层72、设于所述平坦层72上的像素电极层81、设于所述平坦层72与像素电极层81上的像素定义层9、及设于所述像素定义层9上的光阻间隙物91。
所述栅极绝缘层3上对应所述第二栅极22靠近第一栅极21一侧的上方设有第一过孔51，所述钝化层71与平坦层72对应所述第二源极63上方设有第二过孔52，所述像素定义层9上对应所述像素电极层81上方设有第三过孔53；所述第一源极61、第一漏极62与所述第一氧化物半导体层41相接触，所述第二源极63、及第二漏极64与所述第二氧化物半导体层42相接触，所述第一源极61经由所述第一过孔51与所述第二栅极22相接触， 所述像素电极层81经由所述第二过孔52与所述第二源极63相接触，所述第三过孔53暴露出部分像素电极层81。
所述第一栅极21、第二栅极22、栅极绝缘层3、第一氧化物半导体层41、第二氧化物半导体层42、蚀刻阻挡层5、第一源极61、第一漏极62、第二源极63、及第二漏极64构成薄膜晶体管；所述第一极板31、第二极板32、及位于所述第一极板31与第二极板32之间的栅极绝缘层3构成存储电容。
由于存储电容的两电极板之间只存在栅极绝缘层3一层绝缘层，因此存储电容间绝缘层厚度较薄，电容相对面积较小，具有较高的开口率。
具体地，所述栅极绝缘层3与蚀刻阻挡层5采用不同的材料形成；比如，所述栅极绝缘层3采用Al2O3(氧化铝)形成，所述蚀刻阻挡层5采用SiOx(氧化硅)形成，或者，所述栅极绝缘层3采用SiOx形成，所述蚀刻阻挡层5采用Al2O3形成；在制作过程中，蚀刻阻挡层5在第一极板31之上的部分被刻蚀掉，由于所述栅极绝缘层3与蚀刻阻挡层5采用不同的材料形成，蚀刻蚀刻阻挡层5的蚀刻气体对栅极绝缘层3呈钝性，因此，在蚀刻蚀刻阻挡层5的过程中就不会对下层的栅极绝缘层3造成破坏，从而保持良好的器件特性。
如图3所示，为本发明的薄膜晶体管阵列基板第二实施例的结构示意图，包括基板1、设于所述基板1上的第一栅极21、第二栅极22、及位于所述第二栅极22远离第一栅极21一侧的第一极板31、设于所述第一栅极21、第二栅极22、及基板1上的栅极绝缘层3、分别位于所述第一栅极21与第二栅极22上方设于所述栅极绝缘层3上的第一氧化物半导体层41与第二氧化物半导体层42、设于所述第一氧化物半导体层41、第二氧化物半导体层42、栅极绝缘层3、及第一极板31上的蚀刻阻挡层5、位于所述第一极板31上方设于所述蚀刻阻挡层5上的第二极板32、分别位于所述第一栅极21与第二栅极22上方设于所述蚀刻阻挡层5上的第一源极61、第一漏极62、第二源极63、及第二漏极64、设于所述第一源极61、第一漏极62、第二源极63、第二漏极64、及第二极板32上方覆盖所述蚀刻阻挡层5的钝化层71、设于所述钝化层71上的平坦层72、设于所述平坦层72上的像素电极层81、设于所述平坦层72与像素电极层81上的像素定义层9、及设于所述像素定义层9上的光阻间隙物91。
所述栅极绝缘层3上对应所述第二栅极22靠近第一栅极21一侧的上方设有第一过孔51，所述钝化层71与平坦层72对应所述第二源极63上方设有第二过孔52，所述像素定义层9上对应所述像素电极层81上方设有第 三过孔53；所述第一源极61、第一漏极62与所述第一氧化物半导体层41相接触，所述第二源极63、及第二漏极64与所述第二氧化物半导体层42相接触，所述第一源极61经由所述第一过孔51与所述第二栅极22相接触，所述像素电极层81经由所述第二过孔52与所述第二源极63相接触，所述第三过孔53暴露出部分像素电极层81。
所述第一栅极21、第二栅极22、栅极绝缘层3、第一氧化物半导体层41、第二氧化物半导体层42、蚀刻阻挡层5、第一源极61、第一漏极62、第二源极63、及第二漏极64构成薄膜晶体管；所述第一极板31、第二极板32、及位于所述第一极板31与第二极板32之间的蚀刻阻挡层5构成存储电容。
由于存储电容的两电极板之间只存在蚀刻阻挡层5一层绝缘层，在制作过程中，栅极绝缘层3在第一极板31之上的部分被刻蚀掉，因此存储电容间绝缘层厚度较薄，电容相对面积较小，具有较高的开口率。
优选的，存储电容的两电极板之间只存在栅极绝缘层3一层绝缘层，即上述第一实施例。因为，在第二实施例中，如果蚀刻掉在第一极板31之上的栅极绝缘层3部分，在后制程中存储电容的第一极板31上没有保护，很容易受到破坏，如腐蚀等。
上述薄膜晶体管阵列基板，存储电容的两电极板之间只存在栅极绝缘层或者蚀刻阻挡层之中的一层绝缘层，存储电容间绝缘层厚度较薄，电容相对面积较小，具有较高的开口率。
请参阅图4，并结合图2，本发明还提供一种薄膜晶体管阵列基板的制作方法，包括以下步骤：
步骤1、提供一基板1，在所述基板1上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极21、第二栅极22、及位于所述第二栅极22远离第一栅极21一侧的第一极板31。
具体地，所述基板1为玻璃或塑胶基板。
步骤2、在所述第一金属层上沉积并图案化栅极绝缘层3，得到位于所述第二栅极22靠近第一栅极21一侧的上方的第一过孔51。
步骤3、在所述栅极绝缘层3上沉积并图案化氧化物半导体层，分别得到位于所述第一栅极21上方的第一氧化物半导体层41、及位于所述第二栅极22上方的第二氧化物半导体层42。
步骤4、在所述氧化物半导体层上沉积蚀刻阻挡层5，对所述蚀刻阻挡层5进行图案化处理，分别暴露出所述第一氧化物半导体层41、及第二氧化物半导体层42的两侧区域，同时将位于第一极板31上方的蚀刻阻挡层5 部分刻蚀掉。
具体地，所述蚀刻阻挡层5与所述栅极绝缘层3采用不同的材料形成，例如，所述栅极绝缘层3采用Al2O3形成，所述蚀刻阻挡层5采用SiOx形成，或者，所述栅极绝缘层3采用SiOx形成，所述蚀刻阻挡层5采用Al2O3形成。刻蚀蚀刻阻挡层5的刻蚀气体对栅极绝缘层3呈钝性。因此，在蚀刻蚀刻阻挡层5的过程中就不会对下层的栅极绝缘层3造成破坏，从而保持良好的器件特性。
步骤5、在所述蚀刻阻挡层5、及栅极绝缘层3上沉积第二金属层，并对所述第二金属层进行图案化处理，分别得到位于所述第一栅极21上方的第一源极61、及第一漏极62、位于所述第二栅极22上方的第二源极63、及第二漏极64、位于所述第一极板31上方的第二极板32。
所述第一源极61、及第一漏极62与所述第一氧化物半导体层41的两侧区域相接触，所述第二源极63、及第二漏极64与所述第二氧化物半导体层42的两侧区域相接触，所述第一源极61经由所述第一过孔51与所述第二栅极22相接触。
步骤6、依次在所述第二金属层、及蚀刻阻挡层5上形成钝化层71、平坦层72、像素电极层81、像素定义层9、及光阻间隙物91。
所述钝化层71与平坦层72对应所述第二源极63上方形成有第二过孔52，所述像素定义层9上对应所述像素电极层81上方形成有第三过孔53；所述像素电极层81经由所述第二过孔52与所述第二源极63相接触，所述第三过孔53暴露出部分像素电极层81。
具体地，所述钝化层71、平坦层72、像素电极层81、像素定义层9、及光阻间隙物91均可以采用现有技术制得。
值得一提的是，制作上述薄膜晶体管阵列基板时，也可以选择蚀刻掉在第一极板31之上的栅极绝缘层3部分，使存储电容的两电极板之间只存在蚀刻阻挡层5一层绝缘层，从而降低存储电容间绝缘层厚度，减小电容相对面积，提高开口率；但是此种制作方法的弊端在于，在后制程中存储电容的第一极板31上没有保护，很容易受到破坏，如腐蚀等。
上述薄膜晶体管阵列基板的制作方法，在对蚀刻阻挡层进行蚀刻时，将蚀刻阻挡层位于存储电容的第一极板上方的部分蚀刻掉，从而降低了存储电容间绝缘层厚度，减小了电容相对面积，提高了开口率；并通过对栅极绝缘层和蚀刻阻挡层采用不同的材料，使蚀刻气体对栅极绝缘层呈钝性，避免了在蚀刻蚀刻阻挡层的过程中对下层的栅极绝缘层造成破坏，从而保证得到较理想的存储电容。
综上所述，本发明提供的一种薄膜晶体管阵列基板，存储电容的两电极板之间只存在栅极绝缘层或者蚀刻阻挡层之中的一层绝缘层，存储电容间绝缘层厚度较薄，电容相对面积较小，具有较高的开口率。本发明的薄膜晶体管阵列基板的制作方法，在对蚀刻阻挡层进行蚀刻时，将蚀刻阻挡层位于存储电容的第一极板上方的部分蚀刻掉，从而降低了存储电容间绝缘层厚度，减小了电容相对面积，提高了开口率；并通过对栅极绝缘层和蚀刻阻挡层采用不同的材料，使蚀刻气体对栅极绝缘层呈钝性，避免了在蚀刻蚀刻阻挡层的过程中对下层的栅极绝缘层造成破坏，从而保证得到较理想的存储电容。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种薄膜晶体管阵列基板，包括基板，及形成于基板上的薄膜晶体管和存储电容；
    所述存储电容包括位于基板上的第一极板位于第一极板之上的栅极绝缘层或者蚀刻阻挡层，位于栅极绝缘层或者蚀刻阻挡层之上的第二极板。
  2. 如权利要求1所述的薄膜晶体管阵列基板，其中，包括基板、设于所述基板上的第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板、设于所述第一栅极、第二栅极、第一极板、及基板上的栅极绝缘层、分别位于所述第一栅极与第二栅极上方设于所述栅极绝缘层上的第一氧化物半导体层与第二氧化物半导体层、位于所述第一极板上方设于所述栅极绝缘层上的第二极板、设于所述第一氧化物半导体层、第二氧化物半导体层、及栅极绝缘层上的蚀刻阻挡层、分别位于所述第一栅极与第二栅极上方设于所述蚀刻阻挡层上的第一源极、第一漏极、第二源极、及第二漏极、设于所述第一源极、第一漏极、第二源极、第二漏极、及第二极板上方覆盖所述蚀刻阻挡层的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的像素电极层、设于所述平坦层与像素电极层上的像素定义层、及设于所述像素定义层上的光阻间隙物；
    所述栅极绝缘层上对应所述第二栅极靠近第一栅极一侧的上方设有第一过孔，所述钝化层与平坦层对应所述第二源极上方设有第二过孔，所述像素定义层上对应所述像素电极层上方设有第三过孔；所述第一源极、第一漏极与所述第一氧化物半导体层相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触，所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层；
    所述第一栅极、第二栅极、栅极绝缘层、第一氧化物半导体层、第二氧化物半导体层、蚀刻阻挡层、第一源极、第一漏极、第二源极、及第二漏极构成薄膜晶体管；所述第一极板、第二极板、及位于所述第一极板与第二极板之间的栅极绝缘层构成存储电容。
  3. 如权利要求1所述的薄膜晶体管阵列基板，其中，包括基板、设于所述基板上的第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板、设于所述第一栅极、第二栅极、及基板上的栅极绝缘层、分别位于所述第一栅极与第二栅极上方设于所述栅极绝缘层上的第一氧化 物半导体层与第二氧化物半导体层、设于所述第一氧化物半导体层、第二氧化物半导体层、栅极绝缘层、及第一极板上的蚀刻阻挡层、位于所述第一极板上方设于所述蚀刻阻挡层上的第二极板、分别位于所述第一栅极与第二栅极上方设于所述蚀刻阻挡层上的第一源极、第一漏极、第二源极、及第二漏极、设于所述第一源极、第一漏极、第二源极、第二漏极、及第二极板上方覆盖所述蚀刻阻挡层的钝化层、设于所述钝化层上的平坦层设于所述平坦层上的像素电极层、设于所述平坦层与像素电极层上的像素定义层、及设于所述像素定义层上的光阻间隙物；
    所述栅极绝缘层上对应所述第二栅极靠近第一栅极一侧的上方设有第一过孔，所述钝化层与平坦层对应所述第二源极上方设有第二过孔，所述像素定义层上对应所述像素电极层上方设有第三过孔；所述第一源极、第一漏极与所述第一氧化物半导体层相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触，所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层；
    所述第一栅极、第二栅极、栅极绝缘层、第一氧化物半导体层、第二氧化物半导体层、蚀刻阻挡层、第一源极、第一漏极、第二源极、及第二漏极构成薄膜晶体管；所述第一极板、第二极板、及位于所述第一极板与第二极板之间的蚀刻阻挡层构成存储电容。
  4. 如权利要求2所述的薄膜晶体管阵列基板，其中，所述栅极绝缘层与蚀刻阻挡层的材料不同。
  5. 如权利要求3所述的薄膜晶体管阵列基板，其中，所述栅极绝缘层与蚀刻阻挡层的材料不同。
  6. 如权利要求4所述的薄膜晶体管阵列基板，其中，所述栅极绝缘层的材料为Al2O3，所述蚀刻阻挡层的材料为SiOx。
  7. 如权利要求4所述的薄膜晶体管阵列基板，其中，所述栅极绝缘层的材料为SiOx，所述蚀刻阻挡层的材料为Al2O3。
  8. 如权利要求5所述的薄膜晶体管阵列基板，其中，所述栅极绝缘层的材料为Al2O3，所述蚀刻阻挡层的材料为SiOx。
  9. 如权利要求5所述的薄膜晶体管阵列基板，其中，所述栅极绝缘层的材料为SiOx，所述蚀刻阻挡层的材料为Al2O3。
  10. 一种薄膜晶体管阵列基板的制作方法，包括以下步骤：
    步骤1、提供一基板在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极、第二栅极、及位于所述第二栅极远离 第一栅极一侧的第一极板；
    步骤2、在所述第一金属层上沉积并图案化栅极绝缘层，得到位于所述第二栅极靠近第一栅极一侧的上方的第一过孔；
    步骤3、在所述栅极绝缘层上沉积并图案化氧化物半导体层，分别得到位于所述第一栅极上方的第一氧化物半导体层、及位于所述第二栅极上方的第二氧化物半导体层；
    步骤4、在所述氧化物半导体层上沉积蚀刻阻挡层，对所述蚀刻阻挡层进行图案化处理，分别暴露出所述第一氧化物半导体层、及第二氧化物半导体层的两侧区域，同时将位于第一极板上方的蚀刻阻挡层刻蚀掉；
    步骤5、在所述蚀刻阻挡层、及栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，分别得到位于所述第一栅极上方的第一源极、及第一漏极、位于所述第二栅极上方的第二源极、及第二漏极、位于所述第一极板上方的第二极板；
    所述第一源极、及第一漏极与所述第一氧化物半导体层的两侧区域相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层的两侧区域相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触；
    步骤6、依次在所述第二金属层、及蚀刻阻挡层上形成钝化层、平坦层、像素电极层、像素定义层、及光阻间隙物；
    所述钝化层与平坦层对应所述第二源极上方形成有第二过孔，所述像素定义层上对应所述像素电极层上方形成有第三过孔；所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层。
  11. 如权利要求10所述的薄膜晶体管阵列基板的制作方法，其中，所述栅极绝缘层与蚀刻阻挡层采用不同的材料形成。
  12. 如权利要求10所述的薄膜晶体管阵列基板的制作方法，其中，所述栅极绝缘层采用Al2O3形成，所述蚀刻阻挡层采用SiOx形成。
  13. 如权利要求10所述的薄膜晶体管主动装置的制作方法，其中，所述栅极绝缘层采用SiOx形成，所述蚀刻阻挡层采用Al2O3形成。
  14. 一种薄膜晶体管阵列基板的制作方法，包括以下步骤：
    步骤1、提供一基板在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板；
    步骤2、在所述第一金属层上沉积并图案化栅极绝缘层，得到位于所述第二栅极靠近第一栅极一侧的上方的第一过孔；
    步骤3、在所述栅极绝缘层上沉积并图案化氧化物半导体层，分别得到位于所述第一栅极上方的第一氧化物半导体层、及位于所述第二栅极上方的第二氧化物半导体层；
    步骤4、在所述氧化物半导体层上沉积蚀刻阻挡层，对所述蚀刻阻挡层进行图案化处理，分别暴露出所述第一氧化物半导体层、及第二氧化物半导体层的两侧区域，同时将位于第一极板上方的蚀刻阻挡层刻蚀掉；
    步骤5、在所述蚀刻阻挡层、及栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化处理，分别得到位于所述第一栅极上方的第一源极、及第一漏极、位于所述第二栅极上方的第二源极、及第二漏极、位于所述第一极板上方的第二极板；
    所述第一源极、及第一漏极与所述第一氧化物半导体层的两侧区域相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层的两侧区域相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触；
    步骤6、依次在所述第二金属层、及蚀刻阻挡层上形成钝化层、平坦层、像素电极层、像素定义层、及光阻间隙物；
    所述钝化层与平坦层对应所述第二源极上方形成有第二过孔，所述像素定义层上对应所述像素电极层上方形成有第三过孔；所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层；
    其中，所述栅极绝缘层与蚀刻阻挡层采用不同的材料形成；
    其中，所述栅极绝缘层采用Al2O3形成，所述蚀刻阻挡层采用SiOx形成。
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