WO2004031939A1 - 情報処理装置および方法、並びにプログラム - Google Patents
情報処理装置および方法、並びにプログラム Download PDFInfo
- Publication number
- WO2004031939A1 WO2004031939A1 PCT/JP2003/009634 JP0309634W WO2004031939A1 WO 2004031939 A1 WO2004031939 A1 WO 2004031939A1 JP 0309634 W JP0309634 W JP 0309634W WO 2004031939 A1 WO2004031939 A1 WO 2004031939A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- output
- frequency
- unit
- clock
- Prior art date
Links
- 230000010365 information processing Effects 0.000 title claims abstract description 110
- 238000000034 method Methods 0.000 title abstract description 66
- 230000001360 synchronised effect Effects 0.000 claims abstract description 117
- 238000003672 processing method Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 description 46
- 238000010586 diagram Methods 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- 230000008859 change Effects 0.000 description 4
- 101150036056 ectA gene Proteins 0.000 description 4
- 101150102739 ectD gene Proteins 0.000 description 4
- 230000006854 communication Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 101150092716 ectB gene Proteins 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
- G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3884—Pipelining
Definitions
- the present invention relates to an information processing apparatus, method, and program, and in particular, to prevent a decrease in processing performance and suppress power consumption even when the frequency of a synchronous clock signal is variable, even if the frequency is low.
- the present invention relates to an information processing apparatus and method, and a program which can be executed. Background art
- CPU Central Processing Unit
- DSP Digital Signal Processor
- data processing devices such as filters
- information processing devices such as data exchange buses and data paths use synchronous clocks.
- Various processes are being executed in synchronization with the (system clock).
- a storage element such as a flip-flop circuit to store a state in the middle of the process, The element stores the state during the processing (for example, refer to Japanese Patent Application Laid-Open No. 2002-204224).
- Such processing is generally called a pipeline operation. Therefore, hereinafter, a device that stores a state in the middle of processing, such as the above-described flip-flop circuit, is referred to as a pipeline, and an arrangement location of the pipeline is referred to as a pipeline break.
- Pipeline breaks occur when there are few states or at the transition time of each circuit before and after that break (the time from when the data is input to the circuit, the specified processing is performed, and the circuit outputs) ) Often does not exceed the period of the synchronous clock.
- a pipeline is often configured (a break in the pipeline is determined) at the highest frequency. Therefore, when the frequency is low, the transition time of the circuit is much shorter than the period of the synchronous clock, and even when the optimal pipeline configuration is used at the highest frequency, when the frequency is low, There was a problem that the configuration of the pipeline was not always optimal.
- FIG. 1 illustrates a configuration example of a conventional information processing device that performs a pipeline operation.
- the information processing apparatus 1 includes a frequency control unit that varies the frequency of the synchronous clock signal CLK based on predetermined frequency information Infq, and outputs the synchronous clock signal CLK having the changed frequency. 11 and the rising edge or falling edge of the predetermined clock in the synchronous clock signal CLK output from the frequency control unit 11 is detected, the predetermined data is input and held, and the next clock rising edge is detected. Holding sections 12-1 to 12-4 for detecting rising or falling and outputting the held data are provided.
- the information processing device 1 also includes a signal processing unit 13 that performs a first process on the input signal (data) between the holding unit 12-1 and the holding unit 12-2 and outputs the signal (data).
- a signal processing unit 13 that performs a first process on the input signal (data) between the holding unit 12-1 and the holding unit 12-2 and outputs the signal (data).
- One force S between the holding unit 1 2—2 and the holding unit 1 2—3, the signal processing unit that performs the second processing on the input signal (data) and outputs it.
- the signal processing unit 13-3 which performs the third processing on the input signal (data) and outputs it, Is provided.
- the information processing device 1 is provided with four holding units 12-1 to 12-4 as a pipeline, and the breaks in the pipeline are signal processing units 13-1 to 13-3. 3 immediately before the input and immediately after the output. Next, the operation of the information processing device 1 will be described with reference to FIGS.
- a signal input to the information processing device 1, that is, a signal input to the holding unit 12-1 is a data sequence of (AO, BO, CO, DO), and a data sequence ( Each data of A0, BO, CO, DO) is assumed to be sequentially input for each clock in that order.
- the data AO is input to the holding unit 121 and held.
- the data AO is output and the data B0 is input and held in the holding unit 12-1.
- the data AO is subjected to the first processing by the signal processing unit 13-1, becomes data A1, and is input to and held by the holding unit 12-2 until the third clock is output.
- the data B0 is output and the data CO is input and held in the holding unit 12-1.
- the holding unit 12-2 while the data A1 is output, the data B0 output from the holding unit 12-1 is output by the signal processing unit 13-1 until the next fourth clock is output.
- the data is input as data B1, and the data B1 is held.
- the data A 1 is subjected to the second processing by the signal processing unit 13-2 to become data A 2, and is input to and held by the holding unit 12-3 until the fourth clock is output. You.
- the holding unit 12-1 At the fourth clock, in the holding unit 12-1, data C0 is output and data D0 is input and held.
- the data C0 output from the holding unit 12-1 is output by the signal processing unit 13-1 until the data B1 is output and the next fifth clock is output. Input as data C1 And the data CI is retained.
- the holding unit 12-3 while the data A2 is output, the data B1 output from the holding unit 12-2 and the signal processing unit 13-2 until the next fifth clock is output.
- the data is input as data B2, and the data B2 is held.
- the data A2 is subjected to the third processing by the signal processing unit 13-3 to become data A3, and is input to and held by the holding unit 12-4 until the fifth clock is output.
- each of the holding units 12-1 to 12-4 and the signal processing units 13-1 to 13-3 repeat the above-described processing.
- the fifth clock Data A3 output data B3 output at 6th clock, data C3 output data at 7th clock, and data D3 output S at 8th clock.
- the information processing device 1 inputs the data AO at the first clock, and at the fifth clock, each of the signal processing units 13-1 to 13-3. And outputs the data A3 processed by.
- one piece of data (any of data AO to DO) is input to the information processing device 1, subjected to predetermined processing, and output to the outside (data The time until the signal is output to the outside as any one of A3 to D3) is time T1.
- the frequency control unit 11 reduces the frequency of the synchronous clock signal CLK to half of the above-described maximum frequency (the frequency shown in FIG. 2). It is assumed that the frequency is changed and the synchronous clock signal CLK is output at the changed frequency.
- the synchronous clock signal CLK is as shown in FIG. 3 with respect to FIG.
- the operation of the information processing device 1 itself is basically the same as that when the frequency of the synchronous clock signal CLK is the highest frequency (the frequency shown in FIG. 2). That is, as shown in FIG. 3, the information processing device 1 The data AO is input, and at the fifth clock, the data A3 processed by each of the signal processing sections 13-1 to 13-3 is output to the outside.
- one data (one of the data AO to DO) is processed.
- the time T2 is twice as long as 2).
- the processing time (absolute time) of the information processing device 1 is doubled as compared with the case of the highest frequency. In other words, the processing capacity of the information processing device 1 is reduced to half of that at the highest frequency.
- the present invention has been made in view of such a situation, and when the frequency of a synchronous clock signal is variable, even if the frequency is set to be low, it is possible to prevent a decrease in processing performance and to suppress power consumption. Is what you can do.
- An information processing device is an information processing device that operates in synchronization with a synchronous clock having a predetermined frequency, and that changes a frequency of the synchronous clock and outputs a synchronous clock having the changed frequency.
- a predetermined first clock is output from the clock output means and the clock output means, predetermined data is input and held, and the next clock of the first clock is output from the clock output means.
- the holding unit that outputs the held data and the data are transmitted by bypassing the holding unit based on the frequency of the synchronous clock output from the synchronous clock output unit.
- the selection command generation means for generating the selection command and the selection command generated by the selection command generation means are such that the data is transmitted by bypassing the holding means, the data is not passed through the holding means.
- the selection command is provided with a bypass unit that outputs the data output from the holding unit.
- a plurality of sets in which the holding means and the bypass means are connected in that order may be provided, and each of the plurality of sets may be cascaded.
- Data processing means for performing predetermined processing on the data is further provided; the holding means inputs and holds the data processed by the data processing means and outputs the data; and the bypass means outputs a selection command and the holding means If the content is to be transmitted by bypassing the holding means, the data processed by the data processing means is output without passing through the holding means, and the selection command causes the data to be transmitted without bypassing the holding means. If the content is stored in the storage unit, the data is processed by the data processing unit, input and stored by the storage unit, and then the data output from the storage unit can be output.
- stop control means for controlling the processing of the holding means to be stopped is further provided. can do.
- the selection command generating means can further generate frequency information corresponding to the frequency of the synchronous clock output from the synchronous clock output means, and generate a selection command based on the generated frequency information.
- the selection command generating means receives the frequency information corresponding to the frequency of the synchronous clock output from the synchronous clock output means, which is supplied from the outside, and generates a selection command based on the received frequency information. be able to.
- An information processing method operates in synchronization with a synchronous clock of a predetermined frequency, changes the frequency of the synchronous clock, and outputs a synchronous clock of the changed frequency, and a clock output device.
- a predetermined first clock is output from the device
- a holding device that inputs and holds predetermined data and outputs the held data when a second clock subsequent to the first clock is output from the clock output device; and Input to the first input unit to input data output from the holding device, and input to one of the first input unit and the second input unit.
- An information processing method for an information processing apparatus comprising: a bypass device having an output unit for outputting data; and a bypass device that bypasses a holding device based on a frequency of a synchronous clock output from a synchronous clock output device.
- Selection command generation step for generating a selection command for instructing whether or not to transmit the transmission command, and the selection command generated by the processing of the selection command generation step for the bypass device, the holding device is transferred to the bypass device. If the content is to transmit data by bypassing, control is performed so that the data input to the first input unit is output from the output unit, and the selection command is transmitted without bypassing the holding device.
- the program of the present invention operates in synchronization with a synchronous clock having a predetermined frequency, changes the frequency of the synchronous clock, and outputs a synchronous clock having the changed frequency.
- a predetermined first clock is output from the output device, predetermined data is input and held, and a second clock subsequent to the first clock is output from the clock output device.
- a holding device that outputs the held data, a first input unit that inputs data as it is without passing through the holding device, a second input unit that inputs data output from the holding device, and A computer for controlling an information processing apparatus comprising: a bypass device having an output unit for outputting data input to one of the first input unit and the second input unit; Output A selection command generation step for generating a selection command for instructing whether to transmit data by bypassing the holding device based on a frequency of the mouthpiece; and a selection command generation step for the bypass device. If the selection command generated by the processing indicates that data is transmitted by bypassing the holding device, the first input When the selection command is to transmit the data without bypassing the holding device, the data input to the second input unit is output to the output unit. And a bypass control step of performing control to output more.
- a selection command for instructing whether to transmit data by bypassing the holding device is generated based on the frequency of the synchronization clock, and the generated selection command is generated. If the command is to transmit data by bypassing the holding device, and when a predetermined first clock is output, the input data is output as it is without passing through the holding device and generated. If the selected instruction is to transmit data without bypassing the holding device and the first clock is output, the input data is held by the holding device and the first clock is output. When the second clock subsequent to the first clock is output, the data held in the holding device is output.
- the information processing apparatus of the present invention may use, as input data, data generated by itself or data input from outside.
- the information processing device of the present invention may be a device that can use both a device generated by itself and a device input from the outside.
- the information processing apparatus of the present invention may output the output data to the outside or to another predetermined apparatus mounted on the information processing apparatus itself. Further, the information processing apparatus of the present invention may output the output data simultaneously to an external device and another predetermined apparatus mounted on the information processing apparatus itself. Furthermore, the number of other devices may be plural.
- FIG. 1 is a diagram illustrating a configuration example of a conventional information processing apparatus.
- FIG. 2 is a timing chart for explaining an operation example of the information processing apparatus of FIG. 1 when a synchronous clock signal of the highest frequency is output.
- FIG. 3 is a timing chart illustrating an operation example of the information processing apparatus of FIG. 1 when a synchronous clock signal having a half of the highest frequency is output.
- FIG. 4 is a diagram illustrating a configuration example of an information processing apparatus to which the present invention is applied.
- FIG. 5 is a diagram illustrating an example of an encoding method of frequency information input to the frequency control unit of the information processing device in FIG.
- FIG. 6 is a diagram illustrating another example of a method of encoding frequency information input to the frequency control unit of the information processing apparatus in FIG.
- FIG. 7 is a flowchart illustrating a process performed by the frequency control unit of the information processing apparatus in FIG.
- FIG. 8 is a diagram illustrating an example of a selection signal generated by a selector control unit and a mask enable / disable command generated by a CLK mask control unit in the frequency control unit of the information processing apparatus of FIG.
- FIG. 9 is a diagram illustrating another example of a selection signal generated by a selector control unit and a mask enable / disable command generated by a CLK mask control unit in the frequency control unit of the information processing apparatus in FIG.
- FIG. 10 is a diagram for explaining still another example of a selection signal generated by a selector control unit and a mask enable / disable command generated by a CLK mask control unit in the frequency control unit of the information processing apparatus of FIG. It is.
- FIG. 11 is a timing chart illustrating an operation example of the information processing device in FIG. 4 when the highest frequency synchronous clock signal is output.
- FIG. 12 is a timing chart illustrating an operation example of the information processing apparatus of FIG. 4 in the case where a synchronous clock signal having a half of the highest frequency is output.
- FIG. 13 is a timing chart illustrating an operation example of the information processing device in FIG. 4 when the highest frequency synchronous clock signal is output.
- FIG. 14 is a timing chart illustrating another operation example of the information processing apparatus in FIG. 4 when a synchronous clock signal having a half frequency of the highest frequency is output.
- FIG. 15 shows a configuration example of a personal computer on which the information processing device of Fig. 4 is mounted.
- FIG. 1 is a block diagram showing a preferred embodiment of the present invention.
- FIG. 4 shows a configuration example of an information processing apparatus to which the present invention is applied.
- the pipeline of the information processing device 21 and the breaks thereof have basically the same configuration as those of the above-described conventional information processing device 1 (FIG. 1). ing. That is, in the information processing apparatus 21, each of the signal processing units 13-1 to 13-3 having the same configuration as that of FIG. 1 is provided so that the processing is executed in that order. Before input and after output of each of the sections 13-1 to 13-3 (before input of the signal processing section 13-1 and between each of the signal processing sections 13-1 to 13_3, signal processing After the output of the unit 13_3), a corresponding one of the holding units 12-1 to 12-4 having the same configuration as that of FIG. 1 is provided as a pipeline.
- each of the holding units 12-1 to 12-4 is a flip-flop circuit, but may be a synchronous RAM or the like.
- the number of holding units and the number of signal processing units are the same in the example of FIG. 4 as in the example of the conventional information processing apparatus 1 (the example in FIG. 1) for comparison with the conventional example. It is not limited to the example of 4 (four holding units 12-1 to 12-4 and three signal processing units 13-1 to 13-13), and one or more holding units are sufficient. Also, the number of signal processing units may be any number including zero.
- the information processing device 21 can take various embodiments.
- the information processing device 21 can be configured as a data processing device such as a CPU, a DSP, or a filter.
- the information processing device 21 can be configured as a bus for exchanging data or a data path.
- the information processing device 21 is further provided with a block (part) not provided in the conventional information processing device 1 as described below.
- the same signal (data) as that input to the holding unit 12-1 is input to the information processing device 21 between the holding unit 12-1 and the signal processing unit 13-1.
- the first input unit (the input unit described as “0” in the figure) and the second input unit (the “input” in the figure) that inputs the signal (data) output from the holding unit 12-1 1) on the side described as “1”).
- a selection command selectA output from a selector control unit 42 described later a first input unit and a second input unit There is provided a selector unit 31-1 for selecting one of them and outputting data input to the selected input unit to the signal processing unit 13-1.
- the selection command selectA output from the selector control section 42 is not particularly limited as long as it is a signal indicating a command as to whether or not to transmit data by bypassing the holding section 12-1. In, “0” indicating a command to transmit data by bypassing the holding unit 12-1, or a command to transmit data after passing through the holding unit 12-1 (without bypassing) It is a signal corresponding to one of the values of “1”. The same applies to each of selection commands sel ectB to sel ect D described later.
- the holding unit 12 1-1 outputs the predetermined first clock of the synchronous clock signal CLK.
- the data output from the holding unit 12-1 (the side described as “1” in FIG. 4) Is output to the signal processing unit 13-1.
- the selector unit 3 1-1 obtains “0 j” as the selection command selectA
- the holding unit 1 2 The same data as the data input to 1 (the data input to the first input unit on the side described as “0” in FIG. 4) is sent to the signal processing unit 13-1. Output as it is. That is, when the selector unit 31-1 acquires “0” as the selection command selectA, the selector unit 31-1 bypasses the holding unit 12_1 and transmits data to the signal processing unit 13-1.
- the information processing device 21 also includes selectors 31-2 to 31-4 having the same configuration as the selector 31-1, respectively, among the holding units 12-2 to 12-4. Is provided after the output of the corresponding one.
- the selector 31-2 is provided between the holding unit 12-2 and the signal processing unit 13-2, and when “0” is acquired from the selector control unit 42 described later as the selection command selectB, the holding is performed. and bypass a part 1 2 2 transmit data to the signal processing unit 1 3 2.
- the selector 31_2 obtains “1” as the selection command selectB from the selector control unit 42 described later, the selector 31_2 converts the data output from the holding unit 12_2 into a signal processing unit. 1 Transmit to 3—2.
- the selector 3 1 3 set between the holding portion 1 2 3 a signal processing unit 1 3 3 vignetting were acquired from the selector control section 4 2, which will be described later to "0" as the selection instruction selectC In this case, the data is transmitted to the signal processing unit 13-3, bypassing the holding unit 12-3.
- the selector 31-3 acquires "1" as the selection command selectC from the selector control unit 42 described later, the selector 31-3 converts the data output from the holding unit 12-3 into the signal processing unit 13-3. Transmit to 3.
- the selector 31-4 is provided after the holding unit 12-4, and when "0" is obtained as the selection command selectD from the selector control unit 42 described later, the selector 31-4 bypasses the holding unit 12-4. Output data to the outside. On the other hand, when the selector 31-4 obtains "1" as the selection command selectD from the selector control unit 42 described later, the selector 31-4 outputs the data output from the holding unit 12-4 to the outside.
- the information processing apparatus 21 further includes a CLK mask section 3 for stopping the supply of the synchronous clock signal CLK to each of the holding sections 12-1 to 12-4 as necessary.
- a CLK mask section 3 for stopping the supply of the synchronous clock signal CLK to each of the holding sections 12-1 to 12-4 as necessary.
- each of the CLK mask units 32-1 to 32-4 corresponds to a CLK control unit 41 that outputs a synchronous clock signal CLK, which will be described later, and a holding unit 12-1 to 12-4.
- CLK mask units 32-1 to 32-4 is a holding unit based on the contents of the corresponding mask enable / disable command maskA to maskD output from the CLK mask control unit 43 described later. Control is performed to determine whether or not to supply the synchronous clock signal CLK output from the CLK control unit 41 to the corresponding one of 12-1 to 12-4.
- the mask enable / disable command maskA output from the CLK mask control unit 43 is not particularly limited as long as it is a signal representing a command for instructing whether to supply the synchronous clock signal CLK to the holding unit 12-1.
- "1" indicates a command to supply the synchronous clock signal CLK to the holding unit 12-1 or a command to prohibit the supply of the synchronous clock signal CLK to the holding unit 12_1 (mask command).
- the information processing device 21 includes the CLK mask units 32-1 to 32-4, the operation of the holding units 12-1 to 12-4 that do not require processing is performed. Can be stopped. Therefore, among the holding units 12-1 to 12-4, those that do not require processing do not consume power (or reduce the amount of consumption), so that the power consumption of the entire information processing device 21 is reduced. Suppression becomes possible.
- each of the CLK mask sections 32-1 to 32-4 does not need to process the corresponding one of the holding sections 12-1 to 12-4, that is, When the corresponding holding unit is bypassed, the supply of the synchronous clock signal CLK to the holding unit is stopped. Therefore, the contents of the selection commands sel ectA to sel ectD correspond to the contents of the mask enable / disable commands maskA to maskD, respectively.
- the selection command is “1”
- the corresponding mask enable / disable command is “1”
- the select command is “0”
- the corresponding mask enable / disable command is “0”. Become.
- each of the mask enable / disable commands maskA to maskD is output from the CLK mask control unit 43.
- the selector control unit 42 receives the selection commands selectA to selectA.
- each of the mask enable / disable commands tnaskA to raaskD may also be output.
- the selector control unit 42 supplies each of the selection commands selectA to selectD to the corresponding one of the selector units 311 to 311, and also outputs the mask enable / disable commands maskA to maskD, respectively. It may be supplied to the corresponding one of the CLK mask units 32-1 to 32-4.
- the information processing device 21 is also provided with a frequency control unit 33.
- the frequency control unit 33 changes the frequency based on the external frequency information Infq, and outputs a synchronous clock signal CLK of the changed frequency.
- the CLK control unit 4 1 (conventional frequency control unit 1 1
- the CLK control unit 41 corresponding to (FIG. 1) transmits each of the above-mentioned selection commands selectA to selectD based on the frequency of the synchronous clock signal CLK output by the CLK control unit 41 included in the frequency information Infq.
- the frequency information Infq input to the frequency control unit 33 is not limited as long as it indicates the frequency of the synchronous clock signal CLK output from the CLK control unit 41.
- the frequency information Infq indicates the frequency of the synchronous clock signal CLK. It can be expressed as a data bit.
- the frequency information Infq may indicate the current frequency of the synchronous clock signal CLK, or may indicate the frequency of the next clock prior to the change in the frequency of the synchronous clock signal CLK.
- the frequency information Infq is It may be a signal indicating only a change point.Furthermore, the future synchronous clock signal CLK is not limited to the signal of the next clock, and may indicate a frequency after a predetermined number of clocks. It may be.
- various methods can be considered and are not particularly limited.
- information coded as frequency information Infq is used, and It is a method of decoding and using.
- Figures 5 and 6 show two of these encoding methods in a table format, respectively.
- the encoding method is not limited to these, and another encoding method may be used.
- the encoding method shown in FIG. 5 is an example of a method in which 2 bits of data are respectively allocated according to the frequency of the variable synchronization clock signal CLK.
- CLK variable synchronization clock signal
- “1 1” force is assigned respectively.
- the frequency changes by a factor of 10 for example, when the frequency of the synchronous clock signal CLK changes from 100 MHz to 100 MHz, the data length remains at 2 bits, and The processing can be performed without complicating the load processing and the circuit configuration.
- the encoding method shown in FIG. 6 is an example of a method in which data is assigned according to the reciprocal of the frequency of the variable synchronous clock signal CLK.
- the reciprocal of the frequency of the synchronous clock signal CLK corresponds to one clock cycle at each frequency.
- "10" when the frequency of the synchronous clock signal CLK is 10MHz, "3" when the frequency is 33MHz, "2" when the frequency is 50MHz, and "100” when the frequency is 100MHz "1" is assigned at the time of.
- the value represented by the data itself corresponds to the period of one clock, so it is possible to form a waiting time or the like by simple multiplication.
- the frequency of the synchronous clock signal CLK is 10 MHz, 33 MHz, 50 MHz, and 100 MHz, respectively.
- the clock periods are 10 O ns, 3 O ns, 2 O ns, and 10 ns, respectively, and these can be easily calculated by multiplying the above data value by 1 O ns. It is possible.
- the frequency information Infq is supplied from outside the information processing device 21, but is not limited to the example of FIG. 4.
- the frequency control unit 33 itself generates the frequency information Infq. May be.
- each of the selector control unit 42 and the CLK mask control unit 4 3 selects one of the selection commands sel ectA to sel ectD based on the frequency information Infq, although each of the commands raaskA to maskD is generated, the present invention is not limited to the example in FIG. 4 .For example, information different from the frequency information Infq is input from the outside, and based on the information, the selection commands selectA to selectD are selected. Each of them and the mask enable / disable commands maskA to maskD may be generated. Next, the processing of the frequency control unit 33 in FIG. 4 will be described with reference to the flowchart in FIG.
- step S1 the CLK control unit 41 of the frequency control unit 33 outputs a synchronous clock signal CLK having a predetermined frequency.
- step S2 the frequency controller 33 determines whether or not the frequency information Infq has been input.
- step S2 If it is determined in step S2 that the frequency information Infq has not been input, the frequency control unit 31 returns the process to step S1 and repeats the subsequent processes. That is, until the frequency information Infq is input, the CLK control unit 41 of the frequency control unit 31 continues to output the synchronous clock signal CLK of a predetermined frequency.
- step S3 determines in step S3 whether the command is a frequency UP command.
- the frequency included in the frequency information Infq (in this example, for example, the frequency information Infq as shown in FIG. 5 or FIG. I) If the frequency is higher than the frequency of the synchronous clock signal CLK actually output at that time, it is determined in step S3 that the command is for the frequency UP. On the other hand, if the frequency included in the frequency information Infq is equal to or lower than the frequency of the synchronous clock signal CLK actually output at that time, in step S3, the command for the frequency UP is issued. Is not determined.
- step S4 the frequency control unit 33 stops the path of the information processing device 21. That is, the frequency control unit 33 outputs all the data held in the holding units 12-1 to 12-4 to the outside (the data is output from the selector unit 31-4). After that, data transmission between the holding unit 12_1 and the selector unit 31-4 is temporarily stopped.
- step S5 the selector control unit 42 of the frequency control unit 33, based on the frequency (frequency obtained by decoding the frequency information Infq) corresponding to the frequency information Infq input in the process of step S2, Select command selectA ⁇
- step S6 the selector control unit 42 receives the input of each of the selector units 31-1 to 31-4 based on each of the selection commands selectA to selectD generated in the process of step S5. Switch appropriately.
- step S2 if the frequency corresponding to the frequency information Infq input in the processing of step S2 is the highest frequency, and it is determined in step S3 that the command is the frequency UP, the frequency control is performed. As shown in FIG. 8, the unit 33 does not bypass any of the holding units 12-1 to 12-4 (data is transferred to all the holding units 12-1 to 12-4). Each pass).
- each of the selector sections 31-1 to 31-4 receives the corresponding one of the selection commands selectA to selectD, and in this case, any of the received selection commands is " 1 ”, the output of the holding unit that is located immediately before that of the holding units 12-1 to 12-4 is used as an input (Fig. 4 shows the side of the holding unit that is described as" 1 ").
- the setting is switched as follows.
- the CLK mask control unit 43 sets all the mask enable / disable commands raaskA to maskD to “1” in accordance with each of the select commands sel ectA to sel ectD. (“1” is generated) and supplied to the corresponding one of the CLK mask units 32-1 to 32-4.
- each of the CLK mask sections 32-1 to 32-4 receives the corresponding one of the mask enable / disable commands maskA to tnaskD, and in this case, any of the received mask enable / disable commands Is also “1”, so that the synchronous clock signal CLK from the CLK control unit 41 is controlled so as to be supplied to the corresponding holding unit among the holding units 12_1 to 12-4.
- step S7 the frequency control unit 33 restarts the path of the information processing device 21.
- step S8 the frequency control unit 33 sets the frequency of the synchronous clock signal CLK to the frequency input in the process of step S2. Increase to the frequency corresponding to information Infq (frequency obtained by decoding frequency information Infq).
- step S15 the frequency control unit 33 determines whether or not an instruction to end the process has been given.
- step S15 If it is determined in step S15 that the end of the process has been instructed, the frequency control unit 33 ends the process. On the other hand, if it is determined in step SI5 that the end of the process has not been instructed yet, the frequency control unit 33 returns the process to step S1 and repeats the subsequent processes.
- the CLK control unit 41 changes the setting (increases the value) in the processing of the immediately preceding step S8 until the next frequency information Infq is input (in this case, the highest frequency). Continue to output the synchronous clock signal CLK.
- step S2 since the synchronous control signal CLK having the highest frequency has already been output from the CLK control unit 41, the frequency control unit 33 determines in step S2 that the frequency information Infq has been input. Then, in the process of step S3, it is determined that the command is not the frequency UP command. Further, in step S9, frequency control section 33 determines that the command is not the command for frequency DOWN, returns the processing to step S1, and repeats the subsequent processing. That is, the CLK control unit 41 continues to output the synchronous clock signal CLK having the highest frequency until the next frequency information Infq is input.
- the frequency controller 33 determines in step S2 that the frequency information Infq has been input, determines in step S3 that the command is not the frequency UP command, and further determines in step S9 In processing, this time, it is determined that the command is a DO frequency book.
- step S10 the frequency control unit 33 stops the path of the information processing device 21 as in the process of step S4 described above.
- step S11 the selector control unit 42 of the frequency control unit 33, as in the process of step S5 described above, stores the frequency information input in the process of step S2.
- Frequency corresponding to Infq (In this case, frequency information Infq is decoded and obtained
- the selection commands selectA to selectD are generated based on the half of the highest frequency.
- step S12 the selector control unit 42, based on each of the selection commands selectA to selectD generated in the process of step SI1, performs the same operation as the process of step S6 described above. — Switch the input of 1 to 3 1-4 appropriately.
- the frequency control unit 33 bypasses one holding unit 12-2 (does not pass data to the holding unit 12 _ 2), Do not bypass each of the other holding sections 1 2—1, 1 2—3, and 1 2—4. (Data cannot be held by holding sections 1 2—1, 1 2—3, and 1 1 2—pass through each of 4).
- the selector control unit 42 sets the selection command selectB to “0” (generates “0”), and In the processing of 2, the data is transmitted to the selector section 3 1 1 2.
- the selector unit 31_2 upon receiving the selection command selectB (0), receives the output from the signal processing unit 13-1 as an input (bypasses the holding unit 12-2). Change that setting). That is, the selector unit 31-2 changes its setting so that the first input unit on the side described as "0" in FIG. 4 is used as an input.
- step SI1 the selector control section 42 sets each of the selection commands selectA, select and selectD to “1” (generates “1”), and proceeds to step S1.
- the data is transmitted to each of the selector section 31-1, the selector section 31-3, and the selector section 31_4.
- each of the selector section 3 1-1, the selector section 3 1-3, and the selector section 3 1-4 is provided with a selection command selectA (1), selectC (1), and selectD (1) Are received, the output of each of the holding unit 12-1 and the holding unit 12-3, ohio, and the holding unit 12-4 is used as an input (denoted as "1" in FIG. 4).
- the setting is switched as follows.
- the CLK mask control unit 43 sets the mask enable / disable command maskA to “1” and sets the mask enable / disable command maskB to “0” in response to each of the select commands selectA to selectD.
- the mask enable / disable command maskC is set to “1”
- the mask enable / disable command maskD is set to “1” (created). (: The corresponding one of the mask units 3 2 1 1 to 3 2-4 Send.
- the CLK mask section 32-2 supplies the synchronous clock signal CLK from the CLK control section 41 to the holding section 12-2. Is controlled to stop.
- 1 the mask section 32-1, the 1 (mask section 32-3, and the CLK mask section 32-4, respectively) have mask enable / disable commands maskA (1), maskC (1), and After receiving each of maskD and maskD (1), the synchronous clock signal CLK from the CLK control unit 41 is transferred to the holding unit 12-1, the holding unit 12-3, and the holding unit 12-4. Control to supply to
- the frequency control unit 33 bypasses each of the two holding units 12-2 and 12-3 (data is stored in the holding unit 12-2). _ 2 and the holding sections 1 2-3 are not passed through), and the other holding sections 1 2-1 and 1-2-4 are not bypassed (data is stored in the holding sections 1 2 1 1 And pass through each of the holding sections 12-4).
- the selector control unit 42 sets each of the selection commands selectB and selectC to “0” in the process of step S11 (“0”). Is generated) and transmitted to each of the selectors 31-2 and 31-3 in the processing of step S 12. As described above, each of the selector sections 3 1-2 and 3, and the selector sections 3 1-3
- the selector control unit 42 sets the setting of each of the selection commands selectA and selectD to “.1” (generates “1”), and selects the selector unit 3 1-1 and the selector unit 3. Send to each of 1-4.
- each of the selectors 3 1-1 and 3 1-4 receives the selection command selectA (1) and selectD (1).
- — 1 and the output of each of the holding units 1 2 — 4 are set as inputs (the second input unit on the side described as “1” in FIG. 4 is set as input). Switch.
- the CLK mask control unit 43 sets the mask enable / disable instruction inaskA to “1” and the mask enable / disable instruction maskB to “0” in response to each of the select instructions selectA to selectD.
- the mask enable / disable command maskC is set to “0”, and the mask enable / disable command maskD is set to “1” (created), and (the corresponding one of the mask units 32 1 1 to 3 2-4 is set). Supply.
- each of the CLK mask unit 32-2 and the CLK mask unit 32-3 receives the mask enable / disable command maskB (0) and the mask enable / disable command maskC (0), respectively. Then, control is performed so as to stop supplying the synchronous clock signal CLK from the CLK control unit 41 to each of the holding units 12-2 and 12-3.
- 1 mask unit 3 2-1 and CLK mask unit 3 2-4 receive the mask enable / disable command maskA (1) and maskD (1) respectively,
- the synchronous clock signal CLK from the unit 41 is controlled so as to be supplied to each of the holding unit 12-1 and the holding unit 12-4.
- step S13 the frequency control unit 33 restarts the path of the information processing device 21 in the same manner as the processing in step S7 described above, and in step S14, The frequency of the clock signal is converted to the frequency information input in step S2. To the frequency (frequency obtained by decoding the frequency information Infq).
- step S15 the frequency control unit 33 determines whether or not an instruction to end the process has been given.
- step S15 If it is determined in step S15 that the end of the process has not been instructed yet, the frequency control unit 33 returns the process to step S1 and repeats the subsequent processes.
- the CLK controller 41 changes the setting (decreases the value) in the processing of the immediately preceding step S14 until the next frequency information Infq is input. Continue to output synchronous clock signal CLK (half frequency).
- step S15 if it is determined in step S15 that the end of the process has been instructed, the frequency control unit 33 ends the process as described above.
- the subsequent processes that is, the above-described steps S4 to S8 Must be executed in that order.
- the subsequent processes that is, the processes of Steps S10 to S14 described above are: They need not necessarily be executed in that order. Specifically, each of the processes of steps S10 to S13 and the process of step S14 can be executed as a process independent of each other and in any order.
- the operation of the conventional information processing apparatus 1 (FIG. 1) described above is made to correspond to the operation of the information processing apparatus 1 (FIG. 1).
- the signal input to the holding unit 1 2 — 1 is a data sequence of (AO, BO, CO, DO), and each data of the data sequence (A0, B0, CO, DO) is It is assumed that the data is sequentially input every clock.
- the frequency control unit 33 performs the processes of steps S1 to S15 in FIG. 7 described above and outputs the highest-frequency synchronous clock signal CLK.
- none of the holding units 12-1 to 12-4 is bypassed (data is stored in all holding units 1 to 1).
- the operation of the information processing device 21 is as shown in FIG. 11.
- the operation of the information processing device 21 when the highest frequency synchronous clock signal CLK is output (FIG. 11) is based on the highest frequency synchronous clock.
- the operation is basically the same as the operation of the information processing device 1 when the signal CLK is output (FIG. 2). Therefore, description of the operation of the information processing device 21 when the highest frequency synchronous clock signal CLK is output is omitted. .
- frequency information Infq in which a half of the highest frequency is encoded is newly input to the frequency control unit 33, and the above-described processing of steps S1 to S15 in FIG. 7 is executed. Then, it is assumed that the synchronous clock signal CLK having a half frequency of the highest frequency is output. However, here, it is assumed that, as shown in FIG. 9, only one holding unit 12-2 is set to be bypassed (data does not pass through the holding unit 12-2).
- the operation of the information processing device 21 is, for example, as shown in FIG. That is, at the first clock, the data AO is input to the holding unit 12-1 and held.
- the data AO is output and the data B0 is input and held in the holding unit 12-1.
- the data AO passes through the selector unit 31-1 and is subjected to the first processing by the signal processing unit 13-1 to become data A1, and bypasses (does not pass) the holding unit 12_2.
- the signal passes through the selector unit 3 1-2 as it is, and is further processed by the signal processing unit 13-2 to be the data A2.
- the holding unit 1 2-3 is output until the third clock is output. Is entered and retained. Note that since the synchronous clock signal CLK is not supplied to the holding unit 12-2, (Because the supply stop is controlled by the CLK mask section 32-2), the data A1 is not held.
- the data B0 is output and the data CO is input and held in the holding unit 12-1.
- the data B0 output from the holding unit 12-1 passes through the selector unit 31-1 until the next fourth clock is output.
- the data is converted to data B1 by the signal processing unit 13-1, and is passed through the selector unit 31-2 by-passing (not passing through) the holding unit 12-2. Is input as data B2, and the data B2 is held.
- the data A2 passes through the selector section 31-3, is subjected to the third processing by the signal processing section 13-3 to become data A3, and is held until the fourth clock is output. Entered in 4 and held.
- each of the holding unit 12-1, the holding unit 12-3, and the holding unit 12_4, and each of the signal processing units 13_1 to 13-3 are described above.
- data A3 is output to the outside at the fourth clock, and although not shown, data B3 at the fifth clock
- Data C3 at the sixth clock and data C at the seventh clock D3 is output to the outside.
- the information processing device 21 sends the data AO to the first clock.
- the data A3 processed by each of the signal processing units 13-1 to 13-3 is output to the outside at the fourth clock.
- the conventional information processing apparatus 1 in the case where the frequency of the synchronous clock signal CLK is ⁇ of the highest frequency is, as described above (as shown in FIG. 3), the holding units 1 2 1 1 1 to 1 Since none of 1 2 _ 4 is bypassed (data is passed through all the holding units 1 2 _ 1 to 1 2 -4), it is converted into the data AO force data A 3 input at the first clock.
- the output timing is the fifth clock.
- the information processing device 21 in the case where the frequency of the synchronous clock signal CLK is ⁇ ⁇ of the highest frequency Since the unit 12-2 is bypassed, the timing of conversion to the data AO data A3 input at the first clock and output to the outside is the fourth clock which is one clock less than that of the conventional information processing device 1. It becomes.
- the information processing device 21 according to the present invention suppresses a decrease in the processing capability as compared with the conventional information processing device 1 even when the frequency of the synchronous clock signal CLK decreases, and achieves a certain processing capability or more. Can be maintained.
- the processing capability of the information processing device 21 of the present invention that operates with the low-frequency synchronization clock signal CLK is higher than that of the conventional information processing device 1.
- the holding unit 12-2 is The operation of 2 is stopped, and the power consumption of the holding unit 12_2 is suppressed.
- the power consumption of the information processing device 21 of the present invention that operates with the low-frequency synchronization signal CLK is suppressed (reduced) as compared with that of the conventional information processing device 1.
- each of the selection signals selectA to selectD is a signal independent of the others, it is determined whether to bypass each of the holding units 12-1 to 12-4. Can also be set independently of the others. That is, in the information processing device 21, the type and number of the holding units to be bypassed among the holding units 12-1 to 12-4 are not particularly limited as long as the processing can be performed within one clock, and are arbitrary. , And any number can be selected. Therefore, in order to further increase the processing capacity of the information processing device 21 and to suppress the power consumption, the number of holding units to be bypassed among the holding units 12-1 to 12-4 is set as follows. Simply increase it within the range that can be processed during one clock.
- the synchronous clock signal CLK of 1/2 of the highest frequency is output, and only one holding unit 12-2 is bypassed (data does not pass through the holding unit 122).
- the information processing device 21 causes each of the two holding units 12-2 and 2-3 to be bypassed (data is held by the holding unit 12-2 2, and the holders 1 2 and 3 are not allowed to pass through).
- FIG. 14 shows the case where such a synchronous clock signal CLK of 1/2 of the highest frequency is output and the two holding units 1 2-2 and 1-2-3 are bypassed.
- FIG. 13 shows the operation of the information processing device 21 when the highest frequency synchronous clock CLK is output for comparison with FIG. 14. It is the same figure as 1 1 (Fig. 2).
- the data AQ is input to the holding unit 12-1, and is held.
- the data AO is output and the data B0 is input and held in the holding unit 12-1.
- the data AO passes through the selector section 31-1, is subjected to the first processing by the signal processing section 13-1, and becomes data A1, and bypasses the holding section 12-2 (without passing through it).
- the light passes through the selector section 3 1-2 as it is.
- the data A1 is subjected to the second processing by the signal processing unit 13_2 to become the data A2, bypassing the holding unit 12-3, and passing the selector unit 31.3 as it is. pass. Soshi Then, the data A2 is subjected to the third processing by the signal processing unit 13-3 to become data A3, and is input to and held by the holding unit 12-4 until the third clock is output.
- each of the holding unit 12-1 and the holding unit 12_4, and each of the signal processing units 13-1 to 13-3 repeat the above-described processing.
- the data A3 is output to the outside at the third clock
- the data B3 is output at the fourth clock
- the data C3 is output at the fifth clock
- the data D3 is output to the sixth clock at the fifth clock.
- the information processing device 21 At the first clock, the data AO is input, and at the third clock, the data A3 processed by each of the signal processing units 13_1 to 13-3 is output to the outside.
- the timing at which the data input at the first clock is converted to the AO force data A3 and output to the outside is the fourth clock.
- the timing at which the data AO input at the first clock is converted to data A3 and output to the outside is when only one holding unit 12-2 is bypassed
- the third clock is one clock less than that of the third clock. Therefore, as described above (as shown in FIG. 12), when only one holding unit 12-2 is bypassed, the processing time is equal to the processing time T 1 at the highest frequency.
- the power consumption of the holding unit 12-3 as well as the holding unit 12-2 is suppressed. In other words, the power consumption of the information processing device 21 is further reduced (decreased).
- the holding units 12-1 to 12-4, the selector units 31-1 to 31-4, and the signal processing units 13-1 to 1 of the information processing apparatus 21 in FIG. 3-3 is, for example, the CPU (Central) of the personal computer 51 shown in FIG.
- the holding unit 12_1 to holding unit 12-4 of the information processing device 21 in FIG. 4 and the selector unit 31-1 to 31-4 can be configured as, for example, a bus 64 of one personal computer 51 or an input / output interface 65.
- the CPU 61 executes a program stored in a ROM (Read Only Memory) 62 or a program stored in a RAM (Random Access Memory) 63 3 Execute various processes.
- the RAM 63 also appropriately stores data necessary for the CPU 61 to execute various processes.
- modules corresponding to each of the frequency control unit 33 and the CLK mask units 32-1 to 32-4 in FIG. 4 are configured as such a program. .
- Each of these modules is one independent It has a specific algorithm and performs a specific operation according to the algorithm. That is, each of the modules is appropriately read and executed by the CPU 61.
- the CPU 61, the ROM 62, and the RAM 63 are interconnected via a bus 64.
- the bus 64 is also connected to an input / output interface 65.
- the input / output interface 65 includes an input unit 66 such as a keyboard, an output unit 67 such as a display, a storage unit 68 such as a hard disk, and a network (not shown) including the Internet.
- a communication unit 69 for executing a communication process with another device (not shown) through the communication unit is connected.
- a drive 70 is connected to the input / output interface 65 as necessary, and a removable recording medium 71 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is appropriately mounted on the input / output interface 65 and read therefrom.
- the stored computer program is installed in the storage unit 68 as necessary.
- a program for executing the above-described series of processing is installed from a network or a recording medium. As shown in FIG. 15, this recording medium is distributed separately from the main body of the apparatus to provide the program to the owner or the like, and is mounted on the drive 70 and stored on a magnetic disk ( Optical disk (CD-ROM (Compact Disk-Read Only Memory), DVD (Digital
- Versatile Disk magneto-optical disk (including MD (Mini-Disk)), or removable storage media (package media) such as semiconductor memory 71, as well as It is composed of an R0M 62 in which a program is recorded, which is provided to the user in a pre-installed state, and a hard disk included in the storage unit 68.
- the steps of executing the above-described series of processing include, in addition to the processing performed in chronological order in the order described, the processing is not necessarily performed in chronological order, but may be performed in parallel or individually. Also includes the processing executed in Industrial applicability As described above, according to the present invention, the frequency of the synchronous clock signal can be made variable. In particular, even if the frequency of the synchronous clock signal is set to a low frequency, it is possible to prevent a reduction in processing performance and suppress power consumption.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
- Executing Machine-Instructions (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/527,063 US7493508B2 (en) | 2002-09-30 | 2003-07-30 | Information processing device, method, and program |
EP03799074A EP1548574A4 (en) | 2002-09-30 | 2003-07-30 | INFORMATION PROCESSING DEVICE, METHOD AND PROGRAM |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002286524A JP4143907B2 (ja) | 2002-09-30 | 2002-09-30 | 情報処理装置および方法、並びにプログラム |
JP2002-286524 | 2002-09-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004031939A1 true WO2004031939A1 (ja) | 2004-04-15 |
Family
ID=32063575
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/009634 WO2004031939A1 (ja) | 2002-09-30 | 2003-07-30 | 情報処理装置および方法、並びにプログラム |
Country Status (4)
Country | Link |
---|---|
US (1) | US7493508B2 (ja) |
EP (1) | EP1548574A4 (ja) |
JP (1) | JP4143907B2 (ja) |
WO (1) | WO2004031939A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5388864B2 (ja) * | 2007-12-13 | 2014-01-15 | パナソニック株式会社 | クロック制御装置、クロック制御方法、クロック制御プログラム及び集積回路 |
JP4998519B2 (ja) * | 2009-05-29 | 2012-08-15 | 富士通株式会社 | 非同期インタフェース回路及び非同期データ転送方法 |
US9467410B2 (en) | 2012-12-20 | 2016-10-11 | Mcafee, Inc. | Just-in-time, email embedded URL reputation determination |
JP2019053413A (ja) * | 2017-09-13 | 2019-04-04 | カシオ計算機株式会社 | データ処理装置及びデータ処理方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08147163A (ja) * | 1994-11-24 | 1996-06-07 | Toshiba Corp | 演算処理装置及び方法 |
US20010056552A1 (en) * | 2000-06-16 | 2001-12-27 | International Business Machines Corporation | Latch structure for interlocked pipelined CMOS (IPCMOS) circuits |
JP2002297260A (ja) * | 2001-03-30 | 2002-10-11 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2001A (en) * | 1841-03-12 | Sawmill | ||
GB2288957B (en) | 1994-03-24 | 1998-09-23 | Discovision Ass | Start code detector |
JPH05313854A (ja) | 1992-05-08 | 1993-11-26 | Fujitsu Ltd | レジスタファイル |
JPH06295243A (ja) | 1993-04-08 | 1994-10-21 | Mitsubishi Electric Corp | データ処理装置 |
JP2738351B2 (ja) * | 1995-06-23 | 1998-04-08 | 日本電気株式会社 | 半導体集積論理回路 |
JPH09270677A (ja) * | 1995-09-05 | 1997-10-14 | Mitsubishi Electric Corp | フリップフロップ回路及びスキャンパス並びに記憶回路 |
US6247134B1 (en) * | 1999-03-31 | 2001-06-12 | Synopsys, Inc. | Method and system for pipe stage gating within an operating pipelined circuit for power savings |
WO2001033351A1 (fr) | 1999-10-29 | 2001-05-10 | Fujitsu Limited | Architecture de processeur |
US7131017B2 (en) * | 2002-08-16 | 2006-10-31 | Carnegie Mellon University | Programmable pipeline fabric having mechanism to terminate signal propagation |
US7058830B2 (en) * | 2003-03-19 | 2006-06-06 | International Business Machines Corporation | Power saving in a floating point unit using a multiplier and aligner bypass |
US6972998B1 (en) * | 2004-02-09 | 2005-12-06 | Integrated Device Technology, Inc. | Double data rate memory devices including clock domain alignment circuits and methods of operation thereof |
-
2002
- 2002-09-30 JP JP2002286524A patent/JP4143907B2/ja not_active Expired - Fee Related
-
2003
- 2003-07-30 US US10/527,063 patent/US7493508B2/en not_active Expired - Fee Related
- 2003-07-30 EP EP03799074A patent/EP1548574A4/en not_active Withdrawn
- 2003-07-30 WO PCT/JP2003/009634 patent/WO2004031939A1/ja not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08147163A (ja) * | 1994-11-24 | 1996-06-07 | Toshiba Corp | 演算処理装置及び方法 |
US20010056552A1 (en) * | 2000-06-16 | 2001-12-27 | International Business Machines Corporation | Latch structure for interlocked pipelined CMOS (IPCMOS) circuits |
JP2002297260A (ja) * | 2001-03-30 | 2002-10-11 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
Also Published As
Publication number | Publication date |
---|---|
EP1548574A1 (en) | 2005-06-29 |
US7493508B2 (en) | 2009-02-17 |
JP2004126714A (ja) | 2004-04-22 |
US20060010334A1 (en) | 2006-01-12 |
JP4143907B2 (ja) | 2008-09-03 |
EP1548574A4 (en) | 2007-09-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20120002732A1 (en) | Single-Wire Asynchronous Serial Interface | |
WO2004031939A1 (ja) | 情報処理装置および方法、並びにプログラム | |
US7512190B2 (en) | Data transmission apparatus using asynchronous dual-rail bus and method therefor | |
JP2008129616A (ja) | メモリ装置 | |
JP4612139B2 (ja) | 入力回路及びその入力回路を利用する半導体装置 | |
JPH11149444A (ja) | データ転送制御装置及びデータ転送制御システム並びにデータ転送制御方法 | |
JPH056335A (ja) | 装置間インタフエース方式 | |
JPH08340259A (ja) | 並直列変換回路 | |
JP2723828B2 (ja) | 二信号形式混合データ送信回路 | |
JP2599999B2 (ja) | 変復調装置 | |
JPH088514B2 (ja) | ディジタル相関装置 | |
JPWO2010134252A1 (ja) | 通信回路および通信方法 | |
JPS61171210A (ja) | 遅延回路 | |
EP1049024B1 (en) | Signal processing system and method | |
JP3921407B2 (ja) | データ転送におけるデータ監視システムおよびデータ監視方法 | |
JPH11289590A (ja) | オーディオデータ処理装置 | |
JP4494754B2 (ja) | オーディオ信号処理装置 | |
JP4290818B2 (ja) | ビット演算付加データの高速転送回路 | |
JP2567428B2 (ja) | データ転送速度変換装置 | |
JP2001167082A (ja) | 同期積算回路 | |
JPH03222539A (ja) | スタートビット検出回路 | |
JP2008234569A (ja) | スレーブ装置のフィルタ回路 | |
JP2002366349A (ja) | プログラム制御方法およびその装置 | |
JPH04336826A (ja) | 高速伝送路対応の情報伝送方式 | |
JPH07193844A (ja) | 時間スイッチ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
ENP | Entry into the national phase |
Ref document number: 2006010334 Country of ref document: US Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2003799074 Country of ref document: EP Ref document number: 10527063 Country of ref document: US |
|
WWP | Wipo information: published in national office |
Ref document number: 2003799074 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 10527063 Country of ref document: US |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 2003799074 Country of ref document: EP |