US20160225769A1 - Circuit design system and semiconductor circuit designed by using the system - Google Patents

Circuit design system and semiconductor circuit designed by using the system Download PDF

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Publication number
US20160225769A1
US20160225769A1 US15/014,436 US201615014436A US2016225769A1 US 20160225769 A1 US20160225769 A1 US 20160225769A1 US 201615014436 A US201615014436 A US 201615014436A US 2016225769 A1 US2016225769 A1 US 2016225769A1
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Prior art keywords
transistor
design
voltage
node
voltage level
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Abandoned
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US15/014,436
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English (en)
Inventor
Kyong-Taek Lee
Sang-Woo Pae
Hye-jin Kim
June-Kyun Park
Hyun-woo Lee
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of US20160225769A1 publication Critical patent/US20160225769A1/en
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, HYE-JIN, LEE, HYUN-WOO, LEE, KYONG-TAEK, PAE, SANG-WOO, PARK, JUNE-KYUN
Priority to US15/698,978 priority Critical patent/US10276571B2/en
Abandoned legal-status Critical Current

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    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • G—PHYSICS
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    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/06—Structured ASICs
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
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    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Definitions

  • Inventive concepts relate to a circuit design system and a semiconductor circuit designed using the system.
  • a circuit design system uses a transistor including a high-k dielectric film for reducing an area of the transistor while maintaining product reliability.
  • a circuit design method uses a transistor including a high-k dielectric film for reducing an area of the transistor while maintaining product reliability.
  • a computer-readable recording medium includes a program for executing a circuit design method using a transistor including a high-k dielectric film for reducing an area of the transistor while maintaining product reliability.
  • a semiconductor circuit uses a transistor including a high-k dielectric film for reducing an area of the transistor while maintaining product reliability.
  • a circuit design system including a processor; a storage in which a plurality of transistor designs are stored; and a design module designing a circuit based on the plurality of transistor designs according to defined requirements by the processor, wherein the plurality of transistor designs are designs for transistors each including a gate insulating film including a high-k dielectric layer, wherein the design module analyzes a circuit design including the plurality of transistor designs, selects a first transistor design among the plurality of transistor designs, the first transistor design operating in a region where a drain voltage is higher than a gate voltage, and substitutes a second transistor design having a smaller size than the first transistor design for the selected first transistor design, wherein a second drain-gate voltage of the second transistor design operating in an accumulation mode is higher than a first drain-gate voltage of the first transistor design operating in the accumulation mode.
  • a circuit design method including analyzing a semiconductor circuit plurality of transistors and selecting a first NMOS transistor among the plurality of transistors, the first NMOS transistor operating in a region where a drain voltage is higher than a gate voltage; and substituting a second NMOS transistor having a smaller size than the first NMOS transistor for the first NMOS transistor, wherein the first NMOS transistor includes a gate insulating film without a high-k dielectric layer and the second NMOS transistor includes a gate insulating film with a high-k dielectric layer, and a second drain-gate voltage of the second NMOS transistor operating in an accumulation mode is higher than a first drain-gate voltage of the first NMOS transistor operating in the accumulation mode.
  • a computer-readable recording medium including a program for executing a circuit design method, the circuit design method including analyzing a semiconductor circuit plurality of transistors and selecting a first NMOS transistor among the plurality of transistors, the first NMOS transistor operating in a region where a drain voltage is higher than a gate voltage; and substituting a second NMOS transistor having a smaller size than the first NMOS transistor for the first NMOS transistor, wherein the first NMOS transistor includes a gate insulating film without a high-k dielectric layer and the second NMOS transistor includes a gate insulating film with a high-k dielectric layer, and a second drain-gate voltage of the second NMOS transistor operating in an accumulation mode is higher than a first drain-gate voltage of the first NMOS transistor operating in the accumulation mode.
  • a semiconductor circuit including a first transistor gated to an inverted voltage level of a second node and supplying a power supply voltage to a first node; a second transistor connected in parallel to the first transistor, gated to an inverted voltage level of the first node and supplying the power supply voltage to the second node; a third transistor gated to a voltage level of an input signal and supplying a ground voltage; a fourth transistor connected in series to the third transistor, gated to the power supply voltage and transferring an output of the third transistor to the first node; a fifth transistor gated to an inverted voltage level of the input signal and supplying the ground voltage; and a sixth transistor connected in series to the fifth transistor, gated to the power supply voltage and transferring an output of the fifth transistor to the second node, wherein the first to sixth transistors include gate insulating films each including a high-k dielectric layer.
  • a circuit design system includes a processor, a storage in which a plurality of transistor designs are stored; and a design module designing a circuit based on the plurality of transistor designs according to defined requirements by the processor, wherein the plurality of transistor designs are designs for transistors each including a gate insulating film with a high-k dielectric layer, wherein the design module analyzes a circuit design, selects a first transistor design whereby the first transistor design operates within the circuit in a region where a drain voltage is higher than a gate voltage, and substitutes a second transistor design having a smaller size than the first transistor design for the selected first transistor design, wherein a second drain-gate voltage of the second transistor design operating in an accumulation mode is higher than a first drain-gate voltage of the first transistor design operating in the accumulation mode.
  • the second drain-gate voltage of the second transistor design is higher than the first drain-gate voltage of the first transistor design in the accumulation mode.
  • an area of the second transistor design is smaller than an area of the first transistor design.
  • a thickness of the gate insulating film of the second transistor design is smaller than a thickness of the gate insulating film of the first transistor design.
  • a threshold voltage the second transistor design is lower than a threshold voltage of the first transistor design.
  • a channel length of the second transistor design is smaller than of a channel length of the first transistor design.
  • a drain-source voltage of the second transistor design is lower than a drain-source voltage of the first transistor design.
  • each of the first transistor design and the second transistor design includes an NMOS transistor design.
  • the first transistor design includes a first sub transistor design and a second sub transistor design connected in series; the first sub transistor design and the second sub transistor design are NMOS transistor designs; a drain of the second sub transistor is connected to a source of the first sub transistor; and the design module substitutes a single second transistor design for the first sub transistor design and the second sub transistor design, wherein a second drain-gate voltage of the second transistor design operating in the accumulation mode is higher than a third drain-gate voltage of the first sub transistor design and a fourth drain-gate voltage of the second sub transistor design, operating in the accumulation mode.
  • the circuit includes a level shift or an electrostatic discharge (ESD) protection circuit.
  • ESD electrostatic discharge
  • a circuit design method includes analyzing a semiconductor circuit design including a plurality of transistors and selecting a first NMOS transistor design from among the plurality of transistors within the circuit design, the first NMOS transistor operating in a region where a drain voltage is higher than a gate voltage; and substituting a second NMOS transistor having a smaller size than the first NMOS transistor for the first NMOS transistor in the semiconductor circuit, wherein the first NMOS transistor includes a gate insulating film without a high-k dielectric layer and the second NMOS transistor includes a gate insulating film with a high-k dielectric layer, and a second drain-gate voltage of the second NMOS transistor operating in an accumulation mode is higher than a first drain-gate voltage of the first NMOS transistor operating in the accumulation mode.
  • a thickness of the gate insulating film of the second NMOS transistor is smaller than a thickness of the gate insulating film of the first NMOS transistor.
  • a channel length of the second NMOS transistor is smaller than of a channel length of the first NMOS transistor.
  • the first NMOS transistor includes a first sub NMOS transistor and a second sub NMOS transistor connected in series; the substituting of the second NMOS transistor for the first NMOS transistor comprises substituting a single second NMOS transistor for the first sub NMOS transistor and the second sub NMOS transistor; and a second drain-gate voltage of the second NMOS transistor operating in the accumulation mode is higher than a third drain-gate voltage of the first sub NMOS transistor and a fourth drain-gate voltage of the second sub NMOS transistor, operating in the accumulation mode.
  • a computer-readable recording medium includes a program for executing a circuit design method, the circuit design method circuit design method comprising analyzing a semiconductor circuit including a plurality of transistors and selecting a first NMOS transistor from among the plurality of transistors, the first NMOS transistor operating in a region where a drain voltage is higher than a gate voltage; and substituting a second NMOS transistor having a smaller size than the first NMOS transistor for the first NMOS transistor, wherein the first NMOS transistor includes a gate insulating film without a high-k dielectric layer and the second NMOS transistor includes a gate insulating film with a high-k dielectric layer, and a second drain-gate voltage of the second NMOS transistor operating in an accumulation mode is higher than a first drain-gate voltage of the first NMOS transistor operating in the accumulation mode.
  • a semiconductor circuit includes a first transistor gated to an inverted voltage level of a second node and supplying a power supply voltage to a first node; a second transistor connected in parallel to the first transistor, gated to an inverted voltage level of the first node and supplying the power supply voltage to the second node; a third transistor gated to a voltage level of an input signal and supplying a ground voltage; a fourth transistor connected in series to the third transistor, gated to the power supply voltage and transferring an output of the third transistor to the first node; a fifth transistor gated to an inverted voltage level of the input signal and supplying the ground voltage; and a sixth transistor connected in series to the fifth transistor, gated to the power supply voltage and transferring an output of the fifth transistor to the second node, wherein the first to sixth transistors include gate insulating films each including a high-k dielectric layer.
  • the third transistor is gated to the voltage level of the input signal and pulls down the first node
  • the second transistor is gated to the voltage level of the first node and pulls up the second node
  • drain-gate voltages of the third and fifth transistors operating in an accumulation mode are higher than drain-gate voltages of the fourth and sixth transistors operating in the accumulation mode.
  • thicknesses of the gate insulating films of the third and fifth transistors are smaller than thicknesses of the gate insulating films of the fourth and sixth transistors.
  • channel lengths of the third and fifth transistors are smaller than channel lengths of the fourth and sixth transistors.
  • a circuit design method includes analyzing a semiconductor circuit design including a plurality of MOS transistors and selecting a first transistor that operates within the circuit with its drain voltage higher than its gate voltage; and substituting in the circuit design a second, smaller transistor having a gate insulating film with a high-k dielectric layer, for the first transistor.
  • the first and second transistors are NMOS transistors.
  • the drain-gate voltage of the second transistor is higher than that of the first transistor when the transistors operate in an accumulation mode.
  • the second transistor has a thinner gate insulation layer than the first transistor.
  • the second transistor has a shorter channel length than the first transistor.
  • FIG. 1 is a schematic diagram for explaining a circuit design system according to an exemplary embodiment of inventive concepts
  • FIG. 2 is a schematic diagram for explaining three types of transistors used in the circuit design system shown in FIG. 1 ;
  • FIG. 3 is a schematic diagram for explaining an exemplary circuit design using the circuit design system shown in FIG. 1 ;
  • FIG. 4 is a schematic diagram for explaining another exemplary circuit design using the circuit design system shown in FIG. 1 ;
  • FIG. 5 is a schematic diagram for explaining still another exemplary circuit design using the circuit design system shown in FIG. 1 ;
  • FIG. 6 is a schematic diagram for explaining still another exemplary circuit design using the circuit design system shown in FIG. 1 ;
  • FIG. 7 is a schematic diagram for explaining an exemplary semiconductor circuit designed using the circuit design system shown in FIG. 1 ;
  • FIG. 8 is a timing diagram illustrating an operation of the semiconductor circuit shown in FIG. 7 ;
  • FIG. 9 is a flowchart illustrating a circuit design method according to an exemplary embodiment of inventive concepts.
  • FIG. 10 is a flowchart illustrating a circuit design method according to another exemplary embodiment of inventive concepts.
  • FIG. 11 is a block diagram of an electronic system including semiconductor circuits according to some exemplary embodiments of inventive concepts.
  • FIGS. 12 to 14 illustrate exemplary semiconductor systems to which semiconductor devices according to some exemplary embodiments of inventive concepts can be applied.
  • first”, “second”, “third”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of inventive concepts.
  • spatially relative terms such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer when referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • circuit design system according to an exemplary embodiment of inventive concepts will be described with reference to FIG. 1 .
  • FIG. 1 is a schematic diagram for illustrating an exemplary embodiment of a circuit design system in accordance with principles of inventive concepts.
  • unit means, but is not limited to, a software or hardware component, such as field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC), which performs certain tasks.
  • FPGA field-programmable gate array
  • ASIC application-specific integrated circuit
  • the “unit” or “module” is not limited to software or hardware.
  • a “unit” or “module” may advantageously be configured to reside on the addressable storage medium and configured to execute on one or more processors.
  • a “unit” or “module” may include, by way of example, components, such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program codes, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables.
  • the functionality provided for in the components and “units” or “modules” may be combined into fewer components and “units” or “modules” or further separated into additional components and “units” or “modules”.
  • a system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example.
  • a system and method in accordance with principles of inventive concepts may identify a MOS transistor operating with its drain voltage higher than its gate voltage and substitute a smaller transistor for it in the circuit design.
  • the smaller, substituted, transistor may be smaller in that it has a thinner gate insulation layer than the original transistor or in that it has a shorter channel length, for example, and it may include a high-k dielectric layer.
  • a single transistor having a high-k dielectric layer may be substituted for series-connected MOS to reduce the size of the circuit.
  • the drain-gate voltage, VDG, of the substituted transistor may be higher than that of the original transistor (that is, higher than that of the transistor which was swapped out of the design).
  • the original transistor may be susceptible to reduced reliability when operating in the accumulation mode (i.e., off-state), but, because the substituted transistor includes a high-k dielectric layer, it can maintain reliability by its physical band-gap offset while sustaining a higher drain-gate voltage.
  • a circuit implemented using a method and apparatus in accordance with principles of inventive concepts may provide improved reliability and reduced size.
  • the circuit design system 1 includes a processor 10 , a memory 20 , a design module 30 , a storage 40 and a bus 50 .
  • the processor 10 may be used for performing an arithmetic computation of the design module 30 , which will later be described in greater detail.
  • the processor 10 may include at least one of a central processing unit (CPU) and a graphics processing unit (GPU).
  • CPU central processing unit
  • GPU graphics processing unit
  • FIG. 1 only one processor 10 is illustrated, but aspects of the present inventive concept are not limited thereto.
  • a plurality of processors 10 may be provided.
  • the illustrated circuit design system 1 may vary in many ways so long as it can be driven in a multi-core environment. In such a manner, if the circuit design system 1 is driven in a multi-core environment, computational efficiency can be improved.
  • the processor 10 may further include cache memories L 1 , L 2 , etc.
  • the processor 10 may be a semiconductor device, such as a field programmable gate array (FPGA), for example.
  • FPGA field programmable gate array
  • the memory 20 stores data required for the design module 30 to perform a circuit design operation using the processor 10 .
  • the memory 20 may load a plurality of transistor designs stored in the storage 40 to be described in greater detail later to supply the loaded transistor designs to the processor 10 or may store circuit designs designed by the processor 10 to then transfer the circuit designs to the storage 40 .
  • the memory 20 may be a semiconductor memory including, for example, an arbitrary volatile memory, such as, a double data rate synchronous dynamic random access memory (DDR SDRAM), a single data rate synchronous dynamic random access memory (SDR SDRAM), a low power double data rate (LPDDR) SDRAM, or a direct rambus DRAM (RDRAM), but aspects of inventive concepts are not limited thereto.
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • SDR SDRAM single data rate synchronous dynamic random access memory
  • LPDDR SDRAM low power double data rate SDRAM
  • RDRAM direct rambus DRAM
  • the design module 30 designs a circuit using the processor 10 which employs the plurality of transistor designs stored in the storage 40 to be described later according to defined requirements.
  • the design module 30 analyzes a circuit design, including the plurality of transistor designs, and selects from among a plurality of transistor designs a first transistor design operating in a region where a drain voltage is higher than a gate voltage.
  • the design module 30 may receive a circuit design including the plurality of transistor designs stored in the storage 40 and may then identify operating voltages of the respective transistors of the circuit design. For example, in order to identify the operating voltages of the respective transistors, the design module may perform simulation on the circuit design in consideration of an input signal applied to the circuit design and control signals controlling the circuit design, thereby identifying the operating voltages of the respective transistors. After identifying the operating voltages of the respective transistors, the design module 30 selects the first transistor design operating in the region where a drain voltage is higher than a gate voltage.
  • the first transistor design may include an NMOS transistor.
  • the design module 30 substitutes a second transistor design for the selected first transistor design.
  • the second transistor design has a smaller size than the first transistor design.
  • size used herein may mean the overall size of a transistor device or may mean a thickness, breath or width of a particular region or feature size of the transistor device.
  • the second transistor design substituted for the first transistor design by the design module 30 may include a gate insulating film having a thickness smaller than that of a gate insulating film of the first transistor design.
  • the second transistor design substituted for the first transistor design by the design module 30 may have a channel length smaller than that of the first transistor design.
  • two first transistor designs may be selected by the design module 30 and one single second transistor design may be substituted for the selected two first transistor designs, for example.
  • a second drain-gate voltage V DG of the second transistor design operating in the accumulation mode is higher than a first drain-gate voltage V DG of the first transistor design operating in the accumulation mode.
  • a voltage applied to the gate insulating film of the first transistor design is 1 V and a voltage applied to a drain electrode of the first transistor design is 2 V. If the first transistor design operates in an inversion mode due to the voltage of 1 V applied to a gate electrode, the reliability of the first transistor design may not be compromised. However, if a gate-source voltage V GS of the first transistor design does not exceed a threshold voltage of the first transistor design so that the first transistor design operates in the accumulation mode, that is, in an off-state, the reliability of the first transistor design may be compromised. For example, if the voltage applied to the gate electrode of the first transistor design is 0 V, a drain-gate voltage V DG of the first transistor is 2 V, which, in this example, is beyond a voltage range within which the reliability of the first transistor design is maintained.
  • the second transistor substituted by the design module 30 when the second transistor substituted by the design module 30 operates in the accumulation mode, the second transistor has a higher drain-gate voltage V DG than the first transistor. Because, in exemplary embodiments, the second transistor includes a high-k dielectric layer, it is necessary for the second transistor to maintain the reliability in the voltage of 1 V when the second transistor operates in the inversion mode. However, when the second transistor operates in the accumulation mode, it can maintain the reliability by a physical bandgap offset while having a drain-gate voltage V DG of 2 V. Additionally, since the second transistor has a smaller size than the first transistor, an area of the circuit design can be reduced while maintaining the reliability. As a result, the thus-designed circuit may have improved performance and can reduce power consumption.
  • the design module 30 may be implemented in software, but aspects of inventive concepts are not limited thereto. In some exemplary embodiments of inventive concepts in which the design module 30 is implemented in software, it may be stored in the storage 40 in forms of codes or may be stored in another storage (not shown) separated from the storage 40 in forms of codes.
  • the storage 40 stores the plurality of transistor designs required for the design module 30 to perform a circuit design operation using the processor 10 .
  • the plurality of transistor designs stored in the storage 40 are designs of transistors including a high-k dielectric layer. That is, each of the plurality of transistor designs stored in the storage 40 may include a high-k dielectric layer in its gate insulating film.
  • the gate insulating film is formed on a substrate and may include an interface layer that prevents an interface failure between the substrate (e.g., a device isolation layer) and the gate insulating film and a high-k dielectric layer formed on the interface layer.
  • the interface layer may include a low-k material layer having a dielectric constant (k) of 9 or less, such as a silicon oxide layer (k ⁇ 4) or a silicon oxynitride layer (k ⁇ 4 ⁇ 8 according to concentrations of oxygen and nitrogen atoms), for example.
  • the interface layer may include silicate or a combination of layers listed above.
  • the high-k dielectric layer may include, for example, one selected from the group consisting of HfSiON, HfO 2 , ZrO 2 , Ta 2 O 5 , TiO 2 , SrTiO 3 , BaTiO 3 , and SrTiO 3 .
  • the gate insulating film may be formed to an appropriate thickness according to the kind of device to be formed, which will later be described in detail with reference to FIG. 2 .
  • the storage 40 may include, for example, a non-volatile memory device.
  • the non-volatile memory device may include NAND flash, NOR flash, MRAM, PRAM, RRAM, and so on, but aspects of the present inventive concept are not limited thereto.
  • the storage 10 may include a hard disk drive (HDD), a solid state drive (SSD), an optical drive, such as CD-ROM or DVD-ROM, and a magnetic memory.
  • the processor 10 , the memory 20 , the design module 30 and the storage 40 may exchange data through the bus 50 .
  • exemplary embodiments of the bus 50 may include a multi-layer advanced high-performance bus (AHB) or a multi-layer advanced eXtensible interface (AXI), but aspects of the present inventive concept are not limited thereto.
  • FIG. 2 is a schematic diagram for illustrating three types of transistors that may be used in exemplary embodiments of the circuit design system shown in FIG. 1 .
  • the storage 40 may store transistor designs for the first type transistor 100 , the second type transistor 120 and the third type transistor 140 , and the design module 30 may design a circuit by the processor 10 using three types of transistor designs pre-stored in the storage 40 .
  • the first type transistor 100 includes a gate electrode 102 , a source region 108 and a drain region 110 formed on the substrate, and a gate insulating film 104 formed between the substrate and the gate electrode 102 . If the first type transistor 100 is turned on, a channel 106 is formed between the source region 108 and the drain region 110 .
  • the configuration of the thus formed transistor is also applied to the second type transistor 120 and the third type transistor 140 , and repeated descriptions thereof will not be given.
  • the second type transistor 120 includes a gate insulating film 124 formed between the substrate and the gate electrode 122 .
  • a thickness d 2 of the gate insulating film 124 of the second type transistor 120 is greater than a thickness d 1 of the gate insulating film 104 of the first type transistor 100 .
  • the second type transistor 120 including the gate insulating film 124 thicker than the gate insulating film 104 of the first type transistor 100 may occupy a larger area, or volume, or, generally, size than the first type transistor.
  • the second type transistor 120 including the gate insulating film 124 thicker than the gate insulating film 104 of the first type transistor 100 may have a higher threshold voltage than the first type transistor 100 .
  • the third type transistor 140 may include a channel 146 formed between a source region 148 and a drain region 150 .
  • a thickness d 3 of a gate insulating film 144 of the third type transistor 140 is greater than the thickness d 1 of the gate insulating film 104 of the first type transistor 100 , and a length L 3 of the channel 146 of the third type transistor 140 is smaller than a length L 2 of the channel 126 of the second type transistor 120 .
  • the third type transistor 140 having the channel 146 shorter than the channel 126 of the second type transistor 120 may occupy a smaller area (or size) than the second type transistor 120 .
  • the third type transistor 140 having the channel 146 shorter than the channel 126 of the second type transistor 120 has a lower drain-source voltage V DS than the second type transistor 120 .
  • the first type transistor 100 may include a single gate (SG) transistor
  • the second type transistor 120 may include an enhanced gate (EG) transistor including a gate insulating film thicker than that of the SG transistor
  • the third type transistor 140 may include a gate insulating film thicker than that of the SG transistor and an EGV transistor having a smaller channel length than the EG transistor, but aspects of the present inventive concept are not limited thereto.
  • FIG. 3 is a schematic diagram for explaining an exemplary circuit design using the circuit design system shown in FIG. 1 .
  • the design module 30 of the circuit design system 1 analyzes a circuit design including a plurality of transistor designs and selects a second type transistor design Q 1 operating in a region where a drain voltage is higher than a gate voltage.
  • the design module 30 of the circuit design system 1 looks up the plurality of circuit designs stored in the storage 40 and fetches a transistor design for a first type transistor design Q 2 having a smaller size than the second type transistor design Q 1 .
  • the design module 30 of the circuit design system 1 may substitute the first type transistor design Q 2 fetched from the storage 40 for the second type transistor design Q 1 selected from the circuit design.
  • the first type transistor design Q 2 is a transistor design including a high-k dielectric layer and having a gate insulating film thicker than that of the second type transistor design Q 1 .
  • the first type transistor design Q 2 has a smaller area or size than the second type transistor design Q 1 and has a lower threshold voltage than the second type transistor design Q 1 .
  • a drain-gate voltage V DG of the first type transistor design Q 2 operating in an accumulation mode is higher than that of the second type transistor design Q 1 operating in the accumulation mode.
  • the second type transistor design Q 1 operating in a region where a drain voltage is lower than a gate voltage is substituted by the first type transistor design Q 2 including a gate insulating film including a high-k dielectric layer that is smaller than the second type transistor design Q 1 and, as a result, the area required for the circuit design may be reduced while maintaining the reliability of the circuit.
  • FIG. 4 is a schematic diagram for illustrating another exemplary circuit design using the circuit design system shown in FIG. 1 .
  • the circuit design system 1 analyzes a circuit design including the plurality of transistor designs and then selects a second type transistor design Q 1 operating in a region where a drain voltage is higher than a gate voltage.
  • the design module 30 of the circuit design system 1 looks up the plurality of circuit designs stored in the storage 40 and fetches a transistor design for the third type transistor design Q 3 having a smaller size than the first type transistor design Q 2 .
  • the design module 30 of the circuit design system 1 may substitute the third type transistor design Q 3 fetched from the storage 40 for the second type transistor design Q 1 selected by the circuit design.
  • the third type transistor design Q 3 is a transistor design including a high-k dielectric layer and its channel is shorter than that of the second type transistor design Q 1 .
  • a drain-source voltage V DS of the third type transistor design Q 3 is lower than that of the second type transistor design Q 1 .
  • the drain-gate voltage V DG of the third type transistor design Q 3 operating in an accumulation mode is higher than that of the second type transistor design Q 1 operating in the accumulation mode.
  • second type transistor design Q 1 operating in a region where a drain voltage is lower than a gate voltage is substituted by the third type transistor design Q 3 , which includes a gate insulating film including a high-k dielectric layer and is smaller than the second type transistor design Q 1 , thereby reducing an area of the circuit design while maintaining the reliability.
  • FIG. 5 is a schematic diagram for illustrating another exemplary circuit design using the circuit design system shown in FIG. 1 .
  • the circuit design system 1 analyzes a circuit design including a plurality of transistor designs and selects a transistor including two sub transistor designs Q 4 and Q 5 operating in a region where a drain voltage is higher than a gate voltage.
  • the two sub transistor designs Q 4 and Q 5 may be connected in series to each other.
  • the two sub transistor designs Q 4 and Q 5 may be NMOS transistors, and a drain of the sub transistor design Q 5 may be connected to a source of the sub transistor design Q 4 .
  • the design module 30 of the circuit design system 1 looks up the plurality of circuit designs stored in the storage 40 and fetches a transistor design Q 6 of the same type as the two sub transistor designs Q 4 and Q 5 .
  • the design module 30 of the circuit design system 1 may substitute one single transistor design Q 6 for the two sub transistor designs Q 4 and Q 5 connected in series.
  • a drain voltage of the substituted transistor design Q 6 may be the same as that of the sub transistor design Q 4 .
  • a drain-gate voltage V DG of the transistor design Q 6 operating in an accumulation mode is higher than that of each of the sub transistor designs Q 4 and Q 5 operating in the accumulation mode.
  • the two sub transistor designs Q 4 and Q 5 connected in series are substituted by the transistor design Q 6 , which includes a gate insulating film employing a high-k dielectric layer and having the same type as the two sub transistor designs Q 4 and Q 5 , thereby reducing an area of the circuit design while maintaining the reliability.
  • FIG. 6 is a schematic diagram for illustrating another exemplary circuit design using the circuit design system shown in FIG. 1 .
  • circuit design system 1 analyzes a circuit design including the plurality of transistor designs and then selects a transistor including two sub transistor designs Q 4 and Q 5 operating in a region where a drain voltage is higher than a gate voltage.
  • the two sub transistor designs Q 4 and Q 5 may be connected in series.
  • the two sub transistor designs Q 4 and Q 5 may be NMOS transistors, and a drain of the sub transistor design Q 5 may be connected to a source of the sub transistor design Q 4 .
  • the design module 30 of the circuit design system 1 looks up the plurality of circuit designs stored in the storage 40 and fetches a transistor design Q 7 of a different type from the two sub transistor designs Q 4 and Q 5 .
  • the transistor design Q 7 may include a gate insulating film thicker than that of each of the two sub transistor designs Q 4 and Q 5 .
  • the design module 30 of the circuit design system 1 may substitute one single transistor design Q 7 for the two sub transistor designs Q 4 and Q 5 connected in series, selected by the circuit design.
  • a drain voltage of the substituted transistor design Q 7 may be the same as that of the sub transistor design Q 4 .
  • the transistor design Q 7 is a transistor design including a high-k dielectric layer and a thickness of a gate insulating film of the transistor design Q 7 may be greater than that of each of the two sub transistor designs Q 4 and Q 5 .
  • a thickness of a gate insulating film of the transistor design Q 7 may be greater than that of each of the two sub transistor designs Q 4 and Q 5 .
  • an increased amount of the thickness of the gate insulating film is smaller than a decreased amount of the size of one single transistor design Q 7 substituted for the two sub transistor designs Q 4 and Q 5 . Accordingly, the transistor design Q 7 has a smaller size than the two sub transistor designs Q 4 and Q 5 .
  • a drain-gate voltage V DG of the transistor design Q 7 operating in an accumulation mode is higher than that of each of the sub transistor designs Q 4 and Q 5 operating in the accumulation mode.
  • the two sub transistor designs Q 4 and Q 5 connected in series are substituted by the transistor design Q 7 including a gate insulating film including a high-k dielectric layer and having a different type from the two sub transistor designs Q 4 and Q 5 , thereby reducing an area of the circuit design while maintaining the reliability.
  • the aforementioned transistor designs may include NMOS transistor designs, but aspects of the present inventive concept are not limited thereto.
  • the circuit designed by the circuit design system 1 may include a level shift or an electrostatic discharge (ESD) protection circuit, but aspects of inventive concepts are not limited thereto.
  • FIG. 7 is a schematic diagram for illustrating an exemplary semiconductor circuit designed using the circuit design system shown in FIG. 1 .
  • the semiconductor circuit 2 designed using the circuit design system includes transistors P 1 , P 2 , N 1 , N 2 , N 3 , and N 4 .
  • each of the transistors P 1 , P 2 , N 1 , N 2 , N 3 , and N 4 may include a gate insulating film including a high-k dielectric layer.
  • the first transistor P 1 is gated to a voltage level of a second node Z 2 and supplies a power supply voltage VDD to a first node Z 1
  • the second transistor P 2 is connected in parallel to the first transistor P 1 and is gated to a voltage level of the first node Z 1 , and supplies the power supply voltage VDD to the second node Z 2 .
  • the third transistor N 3 is gated to a voltage level of an input signal IN and supplies a ground voltage
  • the fourth transistor N 1 is connected in series to the third transistor N 3 and is gated to the power supply voltage VDD, and transfers an output of the third transistor N 3 to the first node Z 1 .
  • the fifth transistor N 4 is gated to an inverted voltage level of the input signal IN and supplies the ground voltage
  • the sixth transistor N 2 is connected in series to the fifth transistor N 4 and is gated to the power supply voltage VDD, and transfers an output of the fifth transistor N 4 to the second node Z 2 .
  • a drain-gate voltage V DG of each of the third and fifth transistors N 3 and N 4 operating in an accumulation mode may be higher than that of each of the fourth and sixth transistors N 1 and N 2 operating in the accumulation mode.
  • thicknesses of gate insulating films of the third and fifth transistors N 3 and N 4 may be less than the thicknesses of gate insulating films of the fourth and sixth transistors N 1 and N 2 .
  • channel lengths of the third and fifth transistors N 3 and N 4 may be less than the channel lengths of the fourth and sixth transistors N 1 and N 2 .
  • FIG. 8 is a timing diagram illustrating an operation of the semiconductor circuit shown in FIG. 7 .
  • the third transistor N 3 may be gated to the voltage level of the input signal IN and may pull down the first node Z 1
  • the second transistor P 2 may be gated to the voltage level of the first node Z 1 and may pull up the second node Z 2 .
  • the third transistor N 3 gated to the voltage level of the input signal IN and the fourth transistor N 1 gated by the power supply voltage VDD are turned on. Accordingly, the voltage level of the first node Z 1 becomes “LOW”, and the second transistor P 2 gated to the voltage of the first node Z 1 is turned on to supply the power supply voltage VDD to an output OUT.
  • the “HIGH” voltage level of the input signal IN Assuming that a voltage of a level “HIGH” of the input signal IN is VDD 1 and a power supply voltage connected to the source of the second transistor P 2 is VDD 2 , the “HIGH” voltage level of the input signal IN, which is input as the VDD 1 level in the period T 1 of FIG. 8 , is level-shifted to have the voltage level VDD 2 .
  • the fifth transistor N 4 may be gated to the inverted voltage level of the input signal IN and may pull down the second node Z 2
  • the first transistor P 1 may be gated to the voltage level of the second node Z 2 and may pull up the first node Z 1 .
  • the fifth transistor N 4 gated to the inverted voltage level of the input signal IN and the sixth transistor N 2 gated by the power supply voltage VDD are turned on. Accordingly, the voltage level of the second node Z 2 becomes “LOW”, and the first transistor P 1 gated to the voltage of the second node Z 2 is turned on to supply the power supply voltage VDD to the first node Z 1 . Therefore, the voltage level in the period T 2 of FIG. 8 becomes “LOW”, e.g., 0 V.
  • FIG. 9 is a flowchart illustrating a circuit design method according to an exemplary embodiment of inventive concepts.
  • the circuit design method includes analyzing a semiconductor circuit including a plurality of transistors (S 901 ), selecting a first transistor operating in a region where a drain voltage is higher than a gate voltage from among the plurality of transistors (S 903 ), and substituting a second transistor having a smaller size than the first transistor for the selected first transistor (S 905 ), and setting operating mode of the second transistor in accumulation mode (S 907 ).
  • the second transistor includes a gate insulating film including a high-k dielectric layer.
  • a thickness of the gate insulating film of the second transistor may be less than the thickness of the gate insulating film of the first transistor.
  • a channel length of the second transistor design may be shorter than the channel length of the first transistor design.
  • a second drain-gate voltage of the second transistor design operating in an accumulation mode is higher than a first drain-gate voltage of the first transistor design operating in the accumulation mode.
  • FIG. 10 is a flowchart illustrating a circuit design method according to another exemplary embodiment of inventive concepts.
  • the circuit design method includes analyzing a semiconductor circuit including a plurality of transistors (S 1001 ), selecting a first transistor including a first sub transistor and a second sub transistor connected in series, the first transistor operating in a region where a drain voltage is higher than a gate voltage, from among the plurality of transistors (S 1003 ), and substituting a single second transistor for the first sub transistor and the second sub transistor (S 1005 ), and setting operating mode of the second transistor in accumulation mode (S 1007 ).
  • the second transistor includes a gate insulating film including a high-k dielectric layer.
  • the first and second sub transistors and the second transistor may be transistors having the same type.
  • the second transistor may be a transistor including a thicker gate insulating film than the first sub transistor and the second sub transistor.
  • a second drain-gate voltage of the second transistor design operating in an accumulation mode may be higher than a third drain-gate voltage of the first sub transistor design and a fourth drain-gate voltage of the second sub transistor design, operating in the accumulation mode.
  • computer-readable recording medium may include a program for executing the circuit design methods shown in FIGS. 9 and 10 .
  • the computer-readable recording medium may correspond to the storage 40 of the circuit design system 1 , and the program may be executed on the processor 10 of the circuit design system 1 .
  • FIG. 11 is a block diagram of an electronic system including semiconductor circuits according to some exemplary embodiments of inventive concepts.
  • the electronic system 1100 may include a controller 1110 , an input/output device (I/O) 1120 , a memory device 1130 , an interface 1140 and a bus 1150 .
  • the controller 1110 , the I/O 1120 , the memory device 1130 , and/or the interface 1140 may be connected to each other through the bus 1150 .
  • the bus 1150 corresponds to a path through which data moves.
  • the controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of functions similar to those of these elements.
  • the I/O 1120 may include a key pad, a key board, a display device, and so on.
  • the memory device 1130 may store data and/or commands.
  • the interface 1140 may perform functions of transmitting data to a communication network or receiving data from the communication network.
  • the interface 1140 may be wired or wireless.
  • the interface 1140 may include an antenna or a wired/wireless transceiver, and so on.
  • the electronic system 1100 may further include high-speed DRAM and/or SRAM as the working memory for improving the operation of the controller 1110 .
  • a semiconductor device according to the exemplary embodiment of inventive concepts may be employed as the working memory.
  • a semiconductor circuit according to the exemplary embodiment of inventive concepts may be provided in the memory device 1130 or may be provided some components of the controller 1110 or the I/O 1120 , for example.
  • the electronic system 1100 may be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any type of electronic device capable of transmitting and/or receiving information in a wireless environment, for example.
  • PDA personal digital assistant
  • portable computer a portable computer
  • web tablet a wireless phone
  • mobile phone a mobile phone
  • digital music player a digital music player
  • memory card or any type of electronic device capable of transmitting and/or receiving information in a wireless environment, for example.
  • FIGS. 12 to 14 illustrate exemplary semiconductor systems to which semiconductor devices according to some exemplary embodiments of inventive concepts may be applied.
  • FIG. 12 illustrates an example in which a semiconductor device according to an exemplary embodiment of inventive concepts is applied to a tablet PC ( 1200 )
  • FIG. 13 illustrates an example in which a semiconductor device according to an exemplary embodiment of inventive concepts is applied to a notebook computer ( 1300 )
  • FIG. 14 illustrates an example in which a semiconductor device according to an exemplary embodiment of inventive concepts is applied to a smart phone ( 1400 ).
  • At least one of the semiconductor circuits according to some exemplary embodiments of inventive concepts can be employed to a tablet PC 1200 , a notebook computer 1300 , a smart phone 1400 , and the like.
  • the semiconductor system may be implemented as a computer, an ultra mobile personal computer (UMPC), a work station, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, an e-book, a portable multimedia player (PMP), a potable game console, a navigation device, a black box, a digital camera, a 3-dimensional (3D) television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, or the like.
  • UMPC ultra mobile personal computer
  • PDA personal digital assistant
  • PMP portable multimedia player
  • PMP portable multimedia player

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CN105843981B (zh) 2021-06-08
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US20180006034A1 (en) 2018-01-04
KR102315333B1 (ko) 2021-10-19
KR20160095748A (ko) 2016-08-12

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