TWI582918B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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Publication number
TWI582918B
TWI582918B TW104135794A TW104135794A TWI582918B TW I582918 B TWI582918 B TW I582918B TW 104135794 A TW104135794 A TW 104135794A TW 104135794 A TW104135794 A TW 104135794A TW I582918 B TWI582918 B TW I582918B
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Taiwan
Prior art keywords
chip package
hole
insulating layer
layer
blocking member
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TW104135794A
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English (en)
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TW201618250A (zh
Inventor
姚皓然
溫英男
劉建宏
李士儀
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精材科技股份有限公司
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Publication of TW201618250A publication Critical patent/TW201618250A/zh
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Description

晶片封裝體及其製造方法
本發明是有關一種晶片封裝體及其製造方法。
指紋感測裝置(finger print sensor)或射頻感測裝置(RF sensor)需利用平坦的感測面來偵測訊號。若感測面不平整，會影響感測裝置偵測時的準確度。舉例來說，當指頭按壓於指紋感測裝置的感測面時，若感測面不平整，將難以偵測到完整的指紋。
此外，上述的感測裝置在製作時，會先於晶圓中形成矽穿孔(Through Silicon Via；TSV)，使焊墊從矽穿孔裸露。接著，會以化學氣相沉積法(Chemical Vapor Deposition；CVD)在焊墊上與矽穿孔的壁面上形成絕緣層。之後，還需透過圖案化製程於焊墊上的絕緣層形成開口。一般而言圖案化製程包含曝光、顯影與蝕刻製程。在後續製程中，重佈線層便可形成在絕緣層上並電性連接絕緣層開口中的焊墊。
然而，化學氣相沉積與圖案化製程均需耗費大量的製程時間與機台的成本。
本發明之一技術態樣為一種晶片封裝體。
根據本發明一實施方式，一種晶片封裝體包含晶片、雷射阻擋件、絕緣層、重佈線層、阻隔層與導電結構。晶片具有焊墊、及相對的第一表面與第二表面。焊墊位於第一表面上。第二表面具有第一穿孔，使焊墊從第一穿孔裸露。雷射阻擋件位於第一穿孔中的焊墊上。絕緣層位於第二表面上與第一穿孔中。絕緣層具有相對第二表面的第三表面。絕緣層具有第二穿孔，使雷射阻擋件從第二穿孔裸露。重佈線層位於第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上。阻隔層位於第三表面上與重佈線層上。阻隔層具有開口，使重佈線層從開口裸露。導電結構位於開口中的重佈線層上，使導電結構電性連接焊墊。
本發明之一技術態樣為一種晶片封裝體的製造方法。
根據本發明一實施方式，一種晶片封裝體的製造方法包含下列步驟。(a)提供暫時接合的晶圓與支撐件，其中晶圓具有焊墊、及相對的第一表面與第二表面，焊墊位於第一表面，支撐件覆蓋第一表面與焊墊。(b)在晶圓之第二表面中形成第一穿孔，使焊墊從第一穿孔裸露。(c)電鍍雷射阻擋件於第一穿孔中的焊墊上。(d)形成絕緣層於晶圓之第二表面上與第一穿孔中，其中絕緣層具有相對第二表面的第三表面。(e)使用雷射貫穿絕緣層以形成第二穿孔，其中雷射由雷射阻擋件 阻擋，且雷射阻擋件從第二穿孔裸露。(f)電鍍重佈線層於絕緣層的第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上。
在本發明上述實施方式中，由於雷射阻擋件位於第一穿孔中的焊墊上，因此當雷射貫穿絕緣層時，雷射可由雷射阻擋件阻擋，並於絕緣層形成裸露雷射阻擋件的第二穿孔。待第二穿孔形成後，便可電鍍重佈線層於絕緣層的第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上，使得重佈線層可透過雷射阻擋件電性連接焊墊。本發明之晶片封裝體及其製造方法可省略習知化學氣相沉積絕緣層與圖案化絕緣層的製程，能節省製程的時間與機台的成本。此外，晶片的第一表面未經額外的加工，因此平坦性佳，可提升晶片封裝體偵測時的準確度。
100‧‧‧晶片封裝體
110‧‧‧晶片
110a‧‧‧晶圓
112‧‧‧焊墊
113‧‧‧第一表面
114‧‧‧第二表面
115‧‧‧第一穿孔
120‧‧‧雷射阻擋件
121‧‧‧側絕緣層
122‧‧‧第四表面
130‧‧‧絕緣層
132‧‧‧第三表面
133‧‧‧第二穿孔
134‧‧‧壁面
140‧‧‧重佈線層
150‧‧‧阻隔層
152‧‧‧開口
160‧‧‧導電結構
170‧‧‧空穴
180‧‧‧阻障層
210‧‧‧支撐件
2-2‧‧‧線段
D1~D2‧‧‧孔徑
D3~D5‧‧‧厚度
L1‧‧‧線段
L2‧‧‧線段
S1~S6‧‧‧步驟
第1圖繪示根據本發明一實施方式之晶片封裝體的俯視圖。
第2圖繪示第1圖之晶片封裝體沿線段2-2的剖面圖。
第3圖繪示第2圖之晶片封裝體的局部放大圖。
第4圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。
第5圖繪示根據本發明一實施方式之晶圓與支撐件的剖面圖。
第6圖繪示第5圖之晶圓形成第一穿孔後的剖面圖。
第7圖繪示第6圖之焊墊上形成雷射阻擋件後的剖面圖。
第8圖繪示第7圖之晶圓的第二表面上與第一穿孔中形成絕緣層後的剖面圖。
第9圖繪示第8圖之絕緣層形成第二穿孔後的剖面圖。
第10圖繪示第9圖之絕緣層的第三表面、第二穿孔的壁面與雷射阻擋件上形成重佈線層後的剖面圖。
第11圖繪示第10圖之絕緣層與重佈線層上形成阻隔層後的剖面圖。
第12圖繪示第11圖之重佈線層上形成導電結構後的剖面圖。
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1圖繪示根據本發明一實施方式之晶片封裝體100的俯視圖。第2圖繪示第1圖之晶片封裝體100沿線段2-2的剖面圖。同時參閱第1圖與第2圖，晶片封裝體100包含感測晶片110、雷射阻擋件120、絕緣層130、重佈線層 140(Redistribution Layer；RDL)、阻隔層150與導電結構160。晶片110具有焊墊112、及相對的第一表面113與第二表面114。第一表面113為感測面。焊墊112位於第一表面113上。第二表面114具有第一穿孔115，使焊墊112從第一穿孔115裸露。雷射阻擋件120位於第一穿孔115中的焊墊112上。絕緣層130位於晶片110的第二表面114上與第一穿孔115中。絕緣層130具有相對晶片110第二表面114的第三表面132。絕緣層130具有第二穿孔133，使雷射阻擋件120從第二穿孔133裸露。重佈線層140位於絕緣層130的第三表面132上、第二穿孔133的壁面上與第二穿孔133中的雷射阻擋件120上。阻隔層150位於絕緣層130的第三表面132上與重佈線層140上。阻隔層150具有開口152，使重佈線層140從開口152裸露。導電結構160位於開口152中的重佈線層140上，使導電結構160可透過重佈線層140與雷射阻擋件120電性連接焊墊112。此外，晶片封裝體100還可包含側絕緣層121。側絕緣層121位於第一穿孔115的壁面上，且側絕緣層121位於雷射阻擋件120與晶片110之間，可防止雷射阻擋件120與晶片110直接接觸而造成短路。
在本實施方式中，晶片封裝體100可以為指紋感測裝置(finger print sensor)或射頻感測裝置(RF sensor)，但並不用以限制本發明。晶片110的材質可以包含矽。雷射阻擋件120的材質可以包含金或銅，可採用電鍍的方式形成。重佈線層140的材質可以包含銅，亦可採用電鍍的方式形成。絕緣層130的材質可以包含環氧樹脂(epoxy)。
第3圖繪示第2圖之晶片封裝體100的局部放大圖。雷射阻擋件120具有朝向重佈線層140的第四表面122。第二穿孔133可利用雷射貫穿絕緣層130而形成。藉由雷射的使用，第二穿孔133的孔徑D2可小於第一穿孔115的孔徑D1，對於微小化設計有所助益。由於第二穿孔133由雷射形成，因此第二穿孔133的壁面134與雷射阻擋件120的第四表面122均為粗糙面。第二穿孔133的壁面134為絕緣層130朝向第二穿孔133的表面。
由於雷射阻擋件120位於焊墊112上，因此當雷射貫穿絕緣層130時，雷射可由雷射阻擋件120阻擋，並於絕緣層130形成裸露雷射阻擋件120的第二穿孔133。待第二穿孔133形成後，便可以化鍍加電鍍重佈線層140於絕緣層130的第三表面132上、第二穿孔133的壁面134上與第二穿孔133中的雷射阻擋件120上，使得重佈線層140可電性連接焊墊112。
此外，由於重佈線層140係以電鍍的方式形成，因此重佈線層140在絕緣層130之第三表面132上的厚度D3大於重佈線層140在第二穿孔133的壁面134上的厚度D4，且重佈線層140在第二穿孔133的壁面134上的厚度D4大於重佈線層140在雷射阻擋件120上的厚度D5。
在本實施方式中，晶片封裝體100還具有空穴170，且空穴170位於阻隔層150與第二穿孔133中的重佈線層140之間。晶片封裝體100還可具有阻障層180。阻障層180位於焊墊112與雷射阻擋件120之間。阻障層180用以提升雷射阻擋件120在焊墊112的附著力。當雷射阻擋件120的材質包含金 時，阻障層180的材質可包含鎳；當雷射阻擋件120的材質包含銅時，阻障層180的材質可包含鈦。
在以下敘述中，將說明晶片封裝體100的製造方法。
第4圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。晶片封裝體的製造方法包含下列步驟。在步驟S1中，提供暫時接合的晶圓與支撐件，其中晶圓具有焊墊、及相對的第一表面與第二表面，焊墊位於第一表面，支撐件覆蓋第一表面與焊墊。接著在步驟S2中，在晶圓之第二表面中形成第一穿孔，使焊墊從第一穿孔裸露。之後在步驟S3中，電鍍雷射阻擋件於第一穿孔中的焊墊上。接著在步驟S4中，形成絕緣層於晶圓之第二表面上與第一穿孔中，其中絕緣層具有相對第二表面的第三表面。之後在步驟S5中，使用雷射貫穿絕緣層以形成第二穿孔，其中雷射由雷射阻擋件阻擋，且雷射阻擋件從第二穿孔裸露。最後在步驟S6中，電鍍重佈線層於絕緣層的第三表面上、第二穿孔的壁面上與第二穿孔中的雷射阻擋件上。在以下敘述中，將說明上述步驟。
第5圖繪示根據本發明一實施方式之晶圓110a與支撐件210的剖面圖。晶圓110a意指切割後可形成複數個第2圖的晶片110的半導體基板。首先，可提供暫時接合的晶圓110a與支撐件210，其中晶圓110a具有焊墊112、及相對的第一表面113與第二表面114，焊墊112位於第一表面113，支撐件210覆蓋第一表面113與焊墊112。支撐件210可提供晶圓110a支撐力，防止晶圓110a在後續製程中因受力而破裂。待 接合支撐件210於晶圓110a後，可研磨晶圓110a之第二表面114，以減薄晶圓110a的厚度。
第6圖繪示第5圖之晶圓110a形成第一穿孔115後的剖面圖。同時參閱第5圖與第6圖，接著，可在晶圓110a之第二表面114中形成第一穿孔115，使焊墊112從第一穿孔115裸露。在此步驟中，可採用蝕刻製程在晶圓110a中形成第一穿孔115，例如乾蝕刻製程。
第7圖繪示第6圖之焊墊112上形成雷射阻擋件120後的剖面圖。同時參閱第6圖與第7圖，待第一穿孔115形成後，可形成側絕緣層121於第一穿孔115的壁面上。接著，電鍍雷射阻擋件120於第一穿孔115中的焊墊112上，使得雷射阻擋件120與晶圓110a之間由側絕緣層121隔開。此外，為了提升雷射阻擋件120在焊墊112的附著力，還可先電鍍阻障層180(見第3圖)於焊墊112上後，接著才電鍍雷射阻擋件120。
第8圖繪示第7圖之晶圓110a的第二表面114上與第一穿孔115中形成絕緣層130後的剖面圖。待雷射阻擋件120形成後，便可形成絕緣層130於晶圓110a之第二表面114上與第一穿孔115中，其中絕緣層130具有相對第二表面114的第三表面132。在此步驟中，絕緣層130可採用印刷的方式形成於晶圓110a之第二表面114上與第一穿孔115中。接著，設計者可以塗佈、研磨、壓印、製模方式處理絕緣層130之第三表面132，以減薄絕緣層130的厚度。
第9圖繪示第8圖之絕緣層130形成第二穿孔133後的剖面圖。同時參閱第8圖與第9圖，待第8圖的結構形成後， 可使用雷射貫穿絕緣層130以形成第二穿孔133。雷射可由焊墊112上的雷射阻擋件120阻擋，使雷射阻擋件120從第二穿孔133裸露。此外，雷射係對準第一穿孔115與雷射阻擋件120發射，因此第二穿孔133可由第一穿孔115環繞。
第10圖繪示第9圖之絕緣層130的第三表面132、第二穿孔133的壁面與雷射阻擋件120上形成重佈線層140後的剖面圖。同時參閱第9圖與第10圖，待第二穿孔133形成於絕緣層130中後，可電鍍重佈線層140於絕緣層130的第三表面132上、第二穿孔133的壁面上與第二穿孔133中的雷射阻擋件120上。
第11圖繪示第10圖之絕緣層130與重佈線層140上形成阻隔層150後的剖面圖。同時參閱第10圖與第11圖，待第10圖的結構形成後，可形成阻隔層150於絕緣層130的第三表面132上與重佈線層140上。接著，可圖案化阻隔層150以形成開口152，使部分的重佈線層140可從阻隔層150的開口152裸露。
第12圖繪示第11圖之重佈線層140上形成導電結構160後的剖面圖。同時參閱第11圖與第12圖，待阻隔層150的開口152形成後，可形成導電結構160於開口152中的重佈線層140上，使得導電結構160可透過重佈線層140與雷射阻擋件120電性連接焊墊112。在此步驟後，便可移除晶圓110a之第一表面113上的支撐件210。
最後，可沿線段L1、L2切割晶圓110a、絕緣層130與阻隔層150，以形成第2圖之晶片封裝體100。
本發明之晶片封裝體及其製造方法可省略習知化學氣相沉積絕緣層與圖案化絕緣層的製程，能節省製程的時間與機台的成本。此外，晶片的第一表面未經額外的加工，因此平坦性佳，可提升晶片封裝體偵測時的準確度。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧晶片封裝體
110‧‧‧晶片
112‧‧‧焊墊
113‧‧‧第一表面
114‧‧‧第二表面
115‧‧‧第一穿孔
120‧‧‧雷射阻擋件
121‧‧‧側絕緣層
130‧‧‧絕緣層
132‧‧‧第三表面
133‧‧‧第二穿孔
140‧‧‧重佈線層
150‧‧‧阻隔層
152‧‧‧開口
160‧‧‧導電結構
170‧‧‧空穴

Claims (22)

  1. 一種晶片封裝體，包含：一晶片，具有一焊墊、及相對的一第一表面與一第二表面，其中該焊墊位於該第一表面上，該第二表面具有一第一穿孔，使該焊墊從該第一穿孔裸露；一雷射阻擋件，位於該第一穿孔中與該焊墊上，其中該雷射阻擋件的寬度小於該焊墊的寬度；一絕緣層，位於該第二表面上與該第一穿孔中，該絕緣層具有相對該第二表面的一第三表面，該絕緣層具有一第二穿孔，使該雷射阻擋件從該第二穿孔裸露；一重佈線層，位於該第三表面上、該第二穿孔的一壁面上與該第二穿孔中的該雷射阻擋件上；一阻隔層，位於該第三表面上與該重佈線層上，該阻隔層具有一開口，使該重佈線層從該開口裸露；以及一導電結構，位於該開口中的該重佈線層上，使該導電結構電性連接該焊墊。
  2. 如請求項1所述之晶片封裝體，其中該第二穿孔的孔徑小於該第一穿孔的孔徑。
  3. 如請求項1所述之晶片封裝體，具有一空穴，且該空穴位於該阻隔層與該第二穿孔中的該重佈線層之間。
  4. 如請求項1所述之晶片封裝體，其中該第二穿孔的該壁面為一粗糙面。
  5. 如請求項1所述之晶片封裝體，其中該雷射阻擋件具有朝向該重佈線層的一第四表面，且該第四表面為一粗糙面。
  6. 如請求項1所述之晶片封裝體，其中該重佈線層在該絕緣層之該第三表面上的厚度大於該重佈線層在該第二穿孔的該壁面上的厚度。
  7. 如請求項1所述之晶片封裝體，其中該重佈線層在該第二穿孔的該壁面上的厚度大於該重佈線層在該雷射阻擋件上的厚度。
  8. 如請求項1所述之晶片封裝體，其中該絕緣層的材質包含環氧樹脂。
  9. 如請求項1所述之晶片封裝體，更包含：一阻障層，位於該焊墊與該雷射阻擋件之間。
  10. 如請求項9所述之晶片封裝體，其中該阻障層的材質包含鎳，該雷射阻擋件的材質包含金。
  11. 如請求項9所述之晶片封裝體，其中該阻障層的材質包含鈦，該雷射阻擋件的材質包含銅。
  12. 如請求項1所述之晶片封裝體，更包含：一側絕緣層，位於該第一穿孔的壁面上，且該側絕緣層位於該雷射阻擋件與該晶片之間。
  13. 一種晶片封裝體的製造方法，包含：(a)提供暫時接合的一晶圓與一支撐件，其中該晶圓具有一焊墊、及相對的一第一表面與一第二表面，該焊墊位於該第一表面，該支撐件覆蓋該第一表面與該焊墊；(b)在該晶圓之該第二表面中形成一第一穿孔，使該焊墊從該第一穿孔裸露；(c)電鍍一雷射阻擋件於該第一穿孔中與該焊墊上，其中該雷射阻擋件的寬度小於該焊墊的寬度；(d)形成一絕緣層於該晶圓之該第二表面上與該第一穿孔中，其中該絕緣層具有相對該第二表面的一第三表面；(e)使用一雷射貫穿該絕緣層以形成一第二穿孔，其中該雷射由該雷射阻擋件阻擋，且該雷射阻擋件從該第二穿孔裸露；以及(f)電鍍一重佈線層於該絕緣層的該第三表面上、該第二穿孔的一壁面上與該第二穿孔中的該雷射阻擋件上。
  14. 如請求項13所述之晶片封裝體的製造方法，更包含：形成一阻隔層於該絕緣層的該第三表面上與該重佈線層上；以及 圖案化該阻隔層以形成一開口，使該重佈線層從該開口裸露。
  15. 如請求項14所述之晶片封裝體的製造方法，更包含：形成一導電結構於該開口中的該重佈線層上。
  16. 如請求項14所述之晶片封裝體的製造方法，更包含：切割該晶圓、該絕緣層與該阻隔層，以形成該晶片封裝體。
  17. 如請求項13所述之晶片封裝體的製造方法，更包含：研磨該晶圓之該第二表面。
  18. 如請求項13所述之晶片封裝體的製造方法，其中該步驟(d)包含：印刷該絕緣層於該晶圓之該第二表面上與該第一穿孔中。
  19. 如請求項13所述之晶片封裝體的製造方法，更包含：壓印、塗佈、製模、研磨該絕緣層之該第三表面。
  20. 如請求項13所述之晶片封裝體的製造方法，更包含：移除該晶圓的該第一表面上的該支撐件。
  21. 如請求項13所述之晶片封裝體的製造方法，更包含：電鍍一阻障層於該焊墊上。
  22. 如請求項13所述之晶片封裝體的製造方法，更包含：形成一側絕緣層於該第一穿孔的壁面上。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201131724A (en) * 2010-03-04 2011-09-16 Unimicron Technology Corp Package substrate and fabrication method thereof
TW201232684A (en) * 2011-01-17 2012-08-01 Xintec Inc Method for forming chip package

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000323516A (ja) * 1999-05-14 2000-11-24 Fujitsu Ltd 配線基板の製造方法及び配線基板及び半導体装置
JP2003068806A (ja) * 2001-08-29 2003-03-07 Hitachi Ltd 半導体装置及びその製造方法
US7091124B2 (en) * 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
CN1838406A (zh) * 2005-03-24 2006-09-27 矽统科技股份有限公司 封装结构与其封装方法
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US8791549B2 (en) * 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
CN103094479B (zh) * 2013-02-21 2016-01-20 吉林大学 一种在有机电子器件薄膜封装过程中保护电极的方法
TWI581325B (zh) * 2014-11-12 2017-05-01 精材科技股份有限公司 晶片封裝體及其製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201131724A (en) * 2010-03-04 2011-09-16 Unimicron Technology Corp Package substrate and fabrication method thereof
TW201232684A (en) * 2011-01-17 2012-08-01 Xintec Inc Method for forming chip package

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