JP6317475B2 - ウェーハレベルパッケージングのためのダイシング方法、およびウェーハレベルパッケージングに適応したダイシング構造を有する半導体チップ - Google Patents
ウェーハレベルパッケージングのためのダイシング方法、およびウェーハレベルパッケージングに適応したダイシング構造を有する半導体チップ Download PDFInfo
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
テープ層14と反対の基板側17に施されるのが好ましい。ダイシング箔16は、テープ層14を除去することにより半導体チップが解放されるときに半導体チップを固定する。テープ層14が除去されたときには、ダイシング箔16により、かつトレンチ7の上方および特に切断分界9を形成する間隙の間に存在するポリイミド層8の部分18により、半導体チップ間に残る唯一の接続が形成される。ダイシング箔16は、ポリイミド層8を部分18で分断できるように十分な可撓性を有するのが好ましい。
2 配線層
3 第1のパッシベーション層
4 第2のパッシベーション層
5 コンタクトパッド
6 スクライブライン
7 トレンチ
8 ポリイミド層
9 切断分界
10 導電層
11 カバー層
12 アンダーバンプメタライゼーション
13 バンプコンタクト
14 テープ層
15 キャビティ
16 ダイシング箔
17 テープ層と反対の基板側
18 ポリイミド層の部分
19 ポリイミド層の残部
20 集積回路部品
d 深さ
w 幅
Claims (9)
- 半導体基板(1)に集積回路領域(2、20)を設けるステップと、
前記基板(1)の前記集積回路領域(2、20)間にトレンチ(7)を形成するステップと、
前記集積回路領域(2、20)の上方および前記トレンチ(7)の上方にテープ層(14)を施すステップと、
前記トレンチ(7)を開けることにより前記基板(1)のダイシングが行われるまで、前記テープ層(14)と反対の基板側(17)から前記基板(1)の層部分を除去するステップと、
前記テープ層(14)を除去するステップと、を含むウェーハレベルパッケージングのためのダイシング方法であって、
前記トレンチ(7)の形成後、前記テープ層(14)が施される前に、ポリイミド層(8)が前記集積回路領域(2、20)の上方および前記トレンチ(7)の上方に施され、
前記テープ層(14)が除去されるときに、前記ポリイミド層(8)が前記トレンチ(7)の上方で分断される、ことを特徴とするダイシング方法。 - 前記ポリイミド層(8)は、前記トレンチ(7)にまたがるドライフィルムとして施される、請求項1に記載のダイシング方法。
- 前記ポリイミド層(8)は、前記トレンチ(7)の近傍に切断分界(9)が施されている、請求項1または2に記載のダイシング方法。
- 前記切断分界(9)は、前記ポリイミド層(8)の間隙により形成される、請求項3に記載のダイシング方法。
- 前記ポリイミド層(8)は感光性であり、前記切断分界(9)は、フォトリソグラフィを使用して形成される、請求項3または4に記載のダイシング方法。
- 前記集積回路領域(2、20)に、前記ポリイミド層(8)によって覆われていないコンタクトパッド(5)を設けるステップと、
前記テープ層(14)を施す前に、前記コンタクトパッド(5)の1つに各々電気的に接続されるバンプコンタクト(13)を施すステップと、をさらに含む、請求項1から5のいずれか1項に記載のダイシング方法。 - 一部が前記コンタクトパッド(5)に接触する導電層(10)を前記ポリイミド層(8)に施すステップと、
前記導電層(10)を部分的に覆うカバー層(11)を前記導電層(10)に施すステップと、
前記テープ層(14)を施す前に、アンダーバンプメタライゼーション(12)および前記バンプコンタクト(13)を前記導電層(10)の前記カバー層(11)で覆われていない部位に施すステップと、
前記テープ層(14)を前記カバー層(11)に施すステップと、をさらに含む、請求項6に記載のダイシング方法。 - 液体ポリイミド層を上にスピニングすることにより、前記カバー層(11)が施される、請求項7に記載のダイシング方法。
- 前記トレンチ(7)を開けた後、前記テープ層(14)を除去する前に、前記ポリイミド層(8)を切断により分断できるように可撓性を有するダイシング箔(16)を前記半導体基板(1)に施すステップをさらに含む、請求項1から8のいずれか1項に記載のダイシング方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP14170380.1 | 2014-05-28 | ||
EP14170380.1A EP2950338B1 (en) | 2014-05-28 | 2014-05-28 | Dicing method for wafer-level packaging |
PCT/EP2015/061302 WO2015181050A1 (en) | 2014-05-28 | 2015-05-21 | Dicing method for wafer-level packaging and semiconductor chip with dicing structure adapted for wafer-level packaging |
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JP2017519360A JP2017519360A (ja) | 2017-07-13 |
JP6317475B2 true JP6317475B2 (ja) | 2018-04-25 |
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US (1) | US9917012B2 (ja) |
EP (1) | EP2950338B1 (ja) |
JP (1) | JP6317475B2 (ja) |
CN (1) | CN106415817B (ja) |
WO (1) | WO2015181050A1 (ja) |
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WO2016077617A1 (en) | 2014-11-12 | 2016-05-19 | Femtometrix, Inc. | Systems for parsing material properties from within shg signals |
DE102016109165B4 (de) * | 2016-05-18 | 2023-10-12 | Infineon Technologies Ag | Ein halbleiterbauelement und verfahren zum bilden einer mehrzahl von halbleiterbauelementen |
DE102017103095A1 (de) | 2017-02-15 | 2018-08-16 | Infineon Technologies Ag | Handhaben eines dünnen Wafers während der Chipherstellung |
WO2019117987A1 (en) | 2017-12-15 | 2019-06-20 | Didrew Technology (Bvi) Limited | System and method of embedding driver ic (emdic) in lcd display substrate |
WO2019135783A1 (en) | 2018-01-04 | 2019-07-11 | Didrew Technology (Bvi) Limited | Frameless lcd display with embedded ic system and method of manufacturing thereof |
CN111712907A (zh) | 2018-02-09 | 2020-09-25 | 迪德鲁科技(Bvi)有限公司 | 制造具有无载体模腔的扇出型封装的方法 |
WO2019160566A1 (en) | 2018-02-15 | 2019-08-22 | Didrew Technology (Bvi) Limited | Method of simultaneously fabricating multiple wafers on large carrier with warpage control stiffener |
WO2019160570A1 (en) | 2018-02-15 | 2019-08-22 | Didrew Technolgy (Bvi) Limited | System and method of fabricating tim-less hermetic flat top his/emi shield package |
US11908831B2 (en) * | 2020-10-21 | 2024-02-20 | Stmicroelectronics Pte Ltd | Method for manufacturing a wafer level chip scale package (WLCSP) |
CN113255273B (zh) * | 2021-06-07 | 2021-10-01 | 上海国微思尔芯技术股份有限公司 | 分割及验证方法、装置、电子设备、存储介质 |
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US9917012B2 (en) | 2018-03-13 |
JP2017519360A (ja) | 2017-07-13 |
CN106415817B (zh) | 2019-06-28 |
CN106415817A (zh) | 2017-02-15 |
EP2950338B1 (en) | 2019-04-24 |
WO2015181050A1 (en) | 2015-12-03 |
US20170200647A1 (en) | 2017-07-13 |
EP2950338A1 (en) | 2015-12-02 |
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