TWI540655B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

Info

Publication number
TWI540655B
TWI540655B TW103138374A TW103138374A TWI540655B TW I540655 B TWI540655 B TW I540655B TW 103138374 A TW103138374 A TW 103138374A TW 103138374 A TW103138374 A TW 103138374A TW I540655 B TWI540655 B TW I540655B
Authority
TW
Taiwan
Prior art keywords
layer
opening
conductive
semiconductor structure
germanium substrate
Prior art date
Application number
TW103138374A
Other languages
English (en)
Other versions
TW201519340A (zh
Inventor
簡瑋銘
李柏漢
劉滄宇
何彥仕
Original Assignee
精材科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 精材科技股份有限公司 filed Critical 精材科技股份有限公司
Publication of TW201519340A publication Critical patent/TW201519340A/zh
Application granted granted Critical
Publication of TWI540655B publication Critical patent/TWI540655B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device
    • H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H01L2224/0348—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體結構及其製造方法
本發明是有關一種半導體結構及一種半導體結構的製造方法。
習知的半導體結構可包含晶片(chip)、焊墊、介電層(例如二氧化矽)、佈線層(Redistribution Layer；RDL)、導電層、阻隔層與錫球。一般而言，在製作半導體結構時，會先於尚未切割成晶片的矽基板(wafer)上覆蓋介電層，以保護矽基板上的電子元件(例如感光元件)。接著，可利用光微影與蝕刻製程將介電層中之焊墊上方的矽基板與介電層去除，使矽基板與介電層形成通道，而焊墊藉由此通道露出。
之後，可將絕緣層覆蓋於矽基板背對介電層的表面上與矽基板環繞通道的表面上。待絕緣層形成後，可於絕緣層上與焊墊上依序形成佈線層與導電層。待導電層形成後，阻隔層可覆蓋於導電層上，並於阻隔層形成開口供錫球設置。
然而，由於導電層完全覆蓋於佈線層上，會造成導電層材料(例如鎳與金)的浪費。此外，當錫球電性接觸導電層後，需經側向力(剪力)測試錫球的固定性。由於導電層完全覆蓋於佈線層上，當錫球受側向力時，佈線層與導電層的角落區域容易受損，造成整個半導體結構的良率難以提升。
本發明之一技術態樣為一種半導體結構的製造方法。
根據本發明一實施方式，一種半導體結構的製造方法包含下列步驟：(a)提供具有矽基板與保護層的晶圓結構，其中保護層上的焊墊由矽基板的鏤空區露出。(b)形成絕緣層於矽基板環繞鏤空區的側壁上與矽基板背對保護層的表面上。(c)形成佈線層於絕緣層上與焊墊上。(d)形成阻隔層於佈線層上。(e)圖案化阻隔層而形成第一開口，使位於矽基板之表面上的佈線層由第一開口露出。(f)形成第一導電層於露出第一開口的佈線層上。(g)設置導電結構於第一開口中，使導電結構電性接觸第一導電層。
在本發明一實施方式中，上述步驟(e)更包含：圖案化阻隔層而形成第二開口，使位於焊墊上與側壁上之佈線層由第二開口露出。
在本發明一實施方式中，上述步驟(f)更包含：形成第二導電層於露出第二開口的佈線層上。
在本發明一實施方式中，上述步驟(f)係以化鍍的方式形成第一導電層。
在本發明一實施方式中，上述步驟(b)係以化學氣相沉積的方式形成絕緣層。
在本發明一實施方式中，上述晶圓結構具有透光元件與位於透光元件與保護層之間的支撐層，半導體結構的製造方法更包含：切割阻隔層、矽基板、保護層、支撐層與透光元件。
在本發明一實施方式中，上述半導體結構的製造方法更包含：形成尖角結構於矽基板中，其中尖角結構之高度小於或等於矽基板之表面的高度。
本發明之一技術態樣為一種半導體結構。
根據本發明一實施方式，一種半導體結構包含矽基板、保護層、焊墊、絕緣層、佈線層、阻隔層、第一導電層與導電結構。矽基板具有感光元件與鏤空區。保護層位於矽基板上，且覆蓋感光元件。焊墊位於保護層上，且對準於鏤空區。絕緣層位於矽基板環繞鏤空區的側壁上與矽基板背對保護層的表面上。佈線層位於絕緣層上與焊墊上。阻隔層位於佈線層上，且具有第一開口。第一導電層位於第一開口中的佈線層上。導電結構位於第一開口中，且電性接觸第一導電層。
在本發明一實施方式中，上述阻隔層具有第二開口，且位於焊墊上與側壁上之佈線層由第二開口露出。
在本發明一實施方式中，上述半導體結構更包含第 二導電層。第二導電層位於露出第二開口的佈線層上。
在本發明一實施方式中，上述第二導電層的垂直高度小於矽基板背對保護層之表面的垂直高度。
在本發明一實施方式中，上述鏤空區的口徑朝焊墊的方向逐漸減小，使矽基板之側壁為斜面。
在本發明一實施方式中，上述絕緣層為氧化物或氮化物。
在本發明一實施方式中，上述半導體結構更包含透光元件與支撐層。支撐層位於透光元件與保護層之間。
在本發明一實施方式中，上述矽基板更包含尖角結構。尖角結構緊鄰鏤空區，且尖角結構之高度小於或等於矽基板之表面的高度。尖角結構的頂端為尖形、圓形或平坦形。
在本發明一實施方式中，上述導電結構包含錫球或導電凸塊。
在本發明上述實施方式中，由於第一導電層僅形成於露出第一開口的佈線層上，非完全覆蓋於佈線層上，因此可節省第一導電層的材料成本。此外，當導電結構位於第一開口中的第一導電層上時，會電性接觸第一導電層。當導電結構經側向力(剪力)測試導電結構的固定性時，由於第一導電層僅形成於露出第一開口的佈線層上，因此佈線層與第一導電層的角落或邊緣不易受損，使得整個半導體結構的良率得以提升。
100a‧‧‧半導體結構
100b‧‧‧半導體結構
102‧‧‧透光元件
104‧‧‧支撐層
106‧‧‧彩色濾光片
110‧‧‧矽基板
111‧‧‧表面
112‧‧‧感光元件
113‧‧‧表面
114‧‧‧鏤空區
116‧‧‧側壁
118‧‧‧尖角結構
120‧‧‧保護層
130‧‧‧焊墊
140‧‧‧絕緣層
150‧‧‧佈線層
160‧‧‧阻隔層
162‧‧‧第一開口
164‧‧‧第二開口
170‧‧‧第一導電層
180‧‧‧導電結構
190‧‧‧第二導電層
D‧‧‧方向
F‧‧‧側向力
H1‧‧‧高度
H2‧‧‧高度
L‧‧‧線段
R‧‧‧口徑
S1‧‧‧步驟
S2‧‧‧步驟
S3‧‧‧步驟
S4‧‧‧步驟
S5‧‧‧步驟
S6‧‧‧步驟
S7‧‧‧步驟
第1圖繪示根據本發明一實施方式之半導體結構的剖面圖。
第2圖繪示根據本發明一實施方式之半導體結構的製造方法的流程圖。
第3圖繪示第2圖之矽基板形成絕緣層與佈線層後的剖面圖。
第4圖繪示第3圖之佈線層形成阻隔層後的剖面圖。
第5圖繪示第4圖之露出第一開口的佈線層形成第一導電層後的剖面圖。
第6圖繪示第5圖之第一導電層設置導電結構後的剖面圖。
第7圖繪示根據本發明一實施方式之半導體結構的剖面圖。
第8圖繪示根據本發明一實施方式之半導體結構的製造方法的流程圖。
第9圖繪示第8圖之佈線層形成阻隔層後的剖面圖。
第10圖繪示第9圖之露出第一開口與第二開口的佈線層分別形成第一導電層與第二導電層後的剖面圖。
第11圖繪示第10圖之第一導電層設置導電結構後的剖面圖。
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1圖繪示根據本發明一實施方式之半導體結構100a的剖面圖。如圖所示，半導體結構100a包含矽基板110、保護層120、焊墊130、絕緣層140、佈線層150、阻隔層160、第一導電層170與導電結構180。矽基板110具有感光元件112與鏤空區114。保護層120位於矽基板110的表面111上，且保護層120覆蓋感光元件112，使感光元件112可由保護層120保護。此外，焊墊130位於保護層120上，且對準於矽基板110的鏤空區114。絕緣層140位於矽基板110環繞鏤空區114的側壁116上與矽基板110背對保護層120的表面113上。佈線層150位於絕緣層140上與焊墊130上。阻隔層160位於佈線層150上，且具有第一開口162，阻隔層160可阻隔水氣與灰塵進入半導體結構100a。第一導電層170位於第一開口162中的佈線層150上。導電結構180位於第一開口162中，且電性接觸第一導電層170。
由於第一導電層170僅形成於露出第一開口162的佈線層150上，非完全覆蓋於佈線層150上，因此可節省第一導電層170的材料成本。此外，當導電結構180位於 第一開口162中的第一導電層170上時，會電性接觸第一導電層170。當導電結構180經側向力F(剪力)測試導電結構180的固定性時，由於第一導電層170僅形成於露出第一開口162的佈線層150上，因此佈線層150與第一導電層170的角落或邊緣不易受損，使得整個半導體結構100a的良率得以提升。
此外，半導體結構100a還可包含透光元件102、支撐層104與彩色濾光片106。其中，支撐層104位於透光元件102與保護層120之間，使透光元件102與保護層120間相隔一間距。彩色濾光片106設置於保護層120背對矽基板110的表面上。彩色濾光片106對準於矽基板110的感光元件112，使光線進入透光元件102後，可穿過彩色濾光片106而由感光元件112感測。
在本實施方式中，矽基板110可以為影像感測元件、微機電(MEMS)系統元件、運算處理元件等，其材質包含矽。矽基板110可為晶圓(wafer)經切割(dicing)製程後所形成多個晶片中的一片。保護層120與阻隔層160可以為矽的氧化物，例如二氧化矽。絕緣層140可以為氧化物或氮化物。焊墊130的材質可以包含銅，佈線層150的材質可以包含鋁，而第一導電層170的材質可以包含鎳與金。導電結構180可以為錫球或導電凸塊。此外，透光元件102可以為玻璃板，支撐層104的材質可以包含環氧樹脂，但上述材料並不用以限制本發明。
此外，矽基板110還可包含尖角結構118。尖角結 構118緊鄰鏤空區114，且尖角結構118之高度H1小於或等於矽基板110之表面113(也就是矽基板110之背面)的高度H2。尖角結構118的頂端可以為尖形、圓形或平坦形。
應瞭解到，在以上敘述中，已敘述過的元件連接關係將不在重複贅述，合先敘明。在以下敘述中，將說明半導體結構100a的製造方法。
第2圖繪示根據本發明一實施方式之半導體結構的製造方法的流程圖。首先在步驟S1中，提供具有矽基板與保護層的晶圓結構，其中保護層上的焊墊由矽基板的鏤空區露出。接著在步驟S2中，形成絕緣層於矽基板環繞鏤空區的側壁上與矽基板背對保護層的表面上。之後在步驟S3中，形成佈線層於絕緣層上與焊墊上。接著在步驟S4中，形成阻隔層於佈線層上。之後在步驟S5中，圖案化阻隔層而形成第一開口，使位於矽基板之表面上的佈線層由第一開口露出。接著在步驟S6中，形成第一導電層於露出第一開口的佈線層上。最後在步驟S7中，設置導電結構於第一開口中，使導電結構電性接觸第一導電層。
在以下敘述中，將敘述上述半導體結構之製造方法的各步驟，並以矽基板110表示尚未經切割製程的晶圓。
第3圖繪示第2圖之矽基板110形成絕緣層140與佈線層150後的剖面圖。首先，提供具有矽基板110與保護層120的晶圓結構，其中保護層120上的焊墊130由矽基板110的鏤空區114露出。矽基板110的鏤空區114可由蝕刻製程形成。在本實施方式中，當形成鏤空區114時， 尖角結構118可形成於矽基板110中，其中尖角結構118之高度H1小於或等於矽基板110之表面113的高度H2。接著，絕緣層140可形成於矽基板110環繞鏤空區114的側壁116上與矽基板110背對保護層120的表面113上，例如以化學氣相沉積(Chemical Vapor Deposition；CVD)的方式形成絕緣層140，但並不以此方法為限。待絕緣層140形成後，佈線層150可形成於絕緣層140上與焊墊130上。
在本實施方式中，鏤空區114的口徑R朝焊墊130的方向D逐漸減小，使矽基板110之側壁116可以為斜面。如此一來，側壁116與焊墊130間的夾角為鈍角，可避免佈線層150在側壁116與焊墊130的鄰接處發生斷裂。
第4圖繪示第3圖之佈線層150形成阻隔層160後的剖面圖。同時參閱第3圖與第4圖，待佈線層150形成於絕緣層140上與焊墊130上後，阻隔層160可形成於佈線層150上，且覆蓋鏤空區114。接著，阻隔層160可圖案化而形成第一開口162，使位於矽基板110之表面113上的佈線層150由阻隔層160的第一開口162露出。其中，圖案化製程可包含曝光、顯影與蝕刻等光微影技術。
第5圖繪示第4圖之露出第一開口162的佈線層150形成第一導電層170後的剖面圖。同時參閱第4圖與第5圖，待部分的佈線層150由阻隔層160的第一開口162露出後，第一導電層170可形成於露出第一開口162的佈線層150上。其中，由於佈線層150的材質為金屬(例如鋁)，因此第一導電層170能以化鍍(chemical plating)的方式形 成於露出第一開口162的佈線層150上。第一導電層170的材質可為鎳與金，在製作第一導電層170時，可先將第4圖的結構浸泡於鎳槽中再浸泡於金槽中，使露出第一開口162的佈線層150上可形成具鎳與金的第一導電層170。
第6圖繪示第5圖之第一導電層170設置導電結構180後的剖面圖。同時參閱第5圖與第6圖，待第一導電層170形成於露出第一開口162的佈線層150上後，導電結構180可設置於阻隔層160的第一開口162中，使導電結構180可電性接觸第一導電層170。接著，可將阻隔層160、矽基板110、保護層120、支撐層104與透光元件102沿線段L切割，便可得到第1圖之半導體結構100a。
第7圖繪示根據本發明一實施方式之半導體結構100b的剖面圖。如圖所示，半導體結構100b包含矽基板110、保護層120、焊墊130、絕緣層140、佈線層150、阻隔層160、第一導電層170與導電結構180。與第1圖實施方式不同的地方在於：阻隔層160具有第二開口164，且位於焊墊130上與矽基板110之側壁116上的佈線層150由阻隔層160的第二開口164露出。此外，半導體結構100b還包含第二導電層190。第二導電層190位於露出第二開口164的佈線層150上。
在本實施方式中，第二導電層190的垂直高度小於矽基板110背對保護層120之表面113的垂直高度。也就是說，第二導電層190是位於矽基板110之表面113的下方。
應瞭解到，在以上敘述中，已敘述過的元件連接關係將不在重複贅述，合先敘明。在以下敘述中，將說明半導體結構100b的製造方法。
第8圖繪示根據本發明一實施方式之半導體結構的製造方法的流程圖。首先在步驟S1中，提供具有矽基板與保護層的晶圓結構，其中保護層上的焊墊由矽基板的鏤空區露出。接著在步驟S2中，形成絕緣層於矽基板環繞鏤空區的側壁上與矽基板背對保護層的表面上。之後在步驟S3中，形成佈線層於絕緣層上與焊墊上。接著在步驟S4中，形成阻隔層於佈線層上。之後在步驟S5中，圖案化阻隔層而形成第一開口與第二開口，使位於矽基板之表面上的佈線層與位於焊墊上與側壁上之佈線層分別由第一開口與第二開口露出。接著在步驟S6中，分別形成第一導電層與第二導電層於露出第一開口的佈線層上與露出第二開口的佈線層上。最後在步驟S7中，設置導電結構於第一開口中，使導電結構電性接觸第一導電層。
在以下敘述中，將敘述上述半導體結構之製造方法的各步驟，並以矽基板110表示尚未經切割製程的晶圓。
首先提供第3圖的結構，保護層120上的焊墊130由矽基板110的鏤空區114露出。絕緣層140形成於矽基板110環繞鏤空區114的側壁116上與矽基板110背對保護層120的表面113上。佈線層150形成於絕緣層140上與焊墊130上。
第9圖繪示第8圖之佈線層150形成阻隔層160後 的剖面圖。待佈線層150形成於絕緣層140上與焊墊130上後，阻隔層160可形成於佈線層150上，且覆蓋鏤空區114。接著，阻隔層160可圖案化而形成第一開口162與第二開口164，使位於矽基板110之表面113上的佈線層150由阻隔層160的第一開口162露出，而位於焊墊130上與側壁116上的佈線層150由阻隔層160的第二開口164露出。
第10圖繪示第9圖之露出第一開口162與第二開口164的佈線層150分別形成第一導電層170與第二導電層190後的剖面圖。同時參閱第9圖與第10圖，待部分的佈線層150由阻隔層160的第一開口162與第二開口164露出後，第一導電層170可形成於露出第一開口162的佈線層150上，第二導電層190可形成於露出第二開口164的佈線層150上。由於佈線層150的材質為金屬(例如鋁)，因此第一導電層170與第二導電層190能以化鍍(chemical plating)的方式分別同步形成於露出第一開口162的佈線層150上與第二開口164的佈線層150上。在製作第一導電層170與第二導電層190時，可先將第9圖的結構浸泡於鎳槽中再浸泡於金槽中，使露出第一開口162的佈線層150上可形成具鎳與金的第一導電層170，露出第二開口164的佈線層150上可形成具鎳與金的第二導電層190。
第11圖繪示第10圖之第一導電層170設置導電結構180後的剖面圖。同時參閱第10圖與第11圖，待第一導電層170與第二導電層190分別形成於露出第一開口162 的佈線層150與露出第二開口164的佈線層150上後，導電結構180可設置於阻隔層160的第一開口162中，使導電結構180電性接觸第一導電層170。接著，可將阻隔層160、矽基板110、保護層120、支撐層104與透光元件102沿線段L切割，便可得到第7圖之半導體結構100b。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
S1‧‧‧步驟
S2‧‧‧步驟
S3‧‧‧步驟
S4‧‧‧步驟
S5‧‧‧步驟
S6‧‧‧步驟
S7‧‧‧步驟

Claims (15)

  1. 一種半導體結構的製造方法，包含下列步驟：(a)提供具有一矽基板與一保護層的一晶圓結構，其中該保護層上的一焊墊由該矽基板的一鏤空區露出；(b)形成一尖角結構於該矽基板中；(c)形成一絕緣層於該矽基板環繞該鏤空區的一側壁上與該矽基板背對該保護層的一表面上，其中該尖角結構之高度小於或等於該矽基板之該表面的高度；(d)形成一佈線層於該絕緣層上與該焊墊上；(e)形成一阻隔層於該佈線層上；(f)圖案化該阻隔層而形成一第一開口，使位於該矽基板之該表面上的該佈線層由該第一開口露出；(g)形成一第一導電層於露出該第一開口的該佈線層上；以及(h)設置一導電結構於該第一開口中，使該導電結構電性接觸該第一導電層。
  2. 如請求項1所述之半導體結構的製造方法，其中該步驟(f)更包含：圖案化該阻隔層而形成一第二開口，使位於該焊墊上與該側壁上之該佈線層由該第二開口露出。
  3. 如請求項2所述之半導體結構的製造方法，其中該步驟(g)更包含： 形成一第二導電層於露出該第二開口的該佈線層上。
  4. 如請求項1所述之半導體結構的製造方法，其中該步驟(g)係以化鍍的方式形成該第一導電層。
  5. 如請求項1所述之半導體結構的製造方法，其中該步驟(c)係以化學氣相沉積的方式形成該絕緣層。
  6. 如請求項1所述之半導體結構的製造方法，其中該晶圓結構具有一透光元件與位於該透光元件與該保護層之間的一支撐層，該半導體結構的製造方法更包含：切割該阻隔層、該矽基板、該保護層、該支撐層與該透光元件。
  7. 一種半導體結構，包含：一矽基板，具有一感光元件、一鏤空區與一尖角結構，且該尖角結構緊鄰該鏤空區；一保護層，位於該矽基板上，且覆蓋該感光元件；一焊墊，位於該保護層上，且對準於該鏤空區；一絕緣層，位於該矽基板環繞該鏤空區的一側壁上與該矽基板背對該保護層的一表面上，其中該尖角結構之高度小於或等於該矽基板之該表面的高度；一佈線層，位於該絕緣層上與該焊墊上；一阻隔層，位於該佈線層上，且具有一第一開口； 一第一導電層，位於該第一開口中的該佈線層上；以及一導電結構，位於該第一開口中，且電性接觸該第一導電層。
  8. 如請求項7所述之半導體結構，其中該阻隔層具有一第二開口，且位於該焊墊上與該側壁上之該佈線層由該第二開口露出。
  9. 如請求項8所述之半導體結構，更包含：一第二導電層，位於露出該第二開口的該佈線層上。
  10. 如請求項9所述之半導體結構，其中該第二導電層的垂直高度小於該矽基板之該表面的垂直高度。
  11. 如請求項7所述之半導體結構，其中該鏤空區的口徑朝該焊墊的方向逐漸減小，使該矽基板之該側壁為斜面。
  12. 如請求項7所述之半導體結構，其中該絕緣層為氧化物或氮化物。
  13. 如請求項7所述之半導體結構，更包含：一透光元件；以及 一支撐層，位於該透光元件與該保護層之間。
  14. 如請求項7所述之半導體結構，其中該尖角結構的頂端為尖形、圓形或平坦形。
  15. 如請求項7所述之半導體結構，其中該導電結構為錫球或導電凸塊。
TW103138374A 2013-11-07 2014-11-05 半導體結構及其製造方法 TWI540655B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201361901276P 2013-11-07 2013-11-07

Publications (2)

Publication Number Publication Date
TW201519340A TW201519340A (zh) 2015-05-16
TWI540655B true TWI540655B (zh) 2016-07-01

Family

ID=53006420

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103138374A TWI540655B (zh) 2013-11-07 2014-11-05 半導體結構及其製造方法

Country Status (3)

Country Link
US (1) US9214579B2 (zh)
CN (1) CN104637827B (zh)
TW (1) TWI540655B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI600125B (zh) * 2015-05-01 2017-09-21 精材科技股份有限公司 晶片封裝體及其製造方法
JP6612979B2 (ja) * 2015-10-28 2019-11-27 チャイナ ウェイファー レベル シーエスピー カンパニー リミテッド イメージセンシングチップのパッケージ構造とパッケージング方法
CN110148634A (zh) * 2018-02-02 2019-08-20 华星光通科技股份有限公司 防止湿气进入的光感测器电极堆迭结构
JP6986492B2 (ja) * 2018-06-01 2021-12-22 日東電工株式会社 配線回路基板
CN111146083B (zh) 2018-11-01 2022-08-19 精材科技股份有限公司 晶片封装体的制造方法及晶片封装体
CN116964734A (zh) * 2022-02-24 2023-10-27 京东方科技集团股份有限公司 阵列基板及显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6656828B1 (en) * 1999-01-22 2003-12-02 Hitachi, Ltd. Method of forming bump electrodes
US8405115B2 (en) * 2009-01-28 2013-03-26 Maxim Integrated Products, Inc. Light sensor using wafer-level packaging
CN101800207B (zh) * 2010-03-12 2011-10-26 苏州晶方半导体科技股份有限公司 半导体器件的封装结构及其制造方法
TWI502708B (zh) * 2010-03-23 2015-10-01 Xintec Inc 晶片封裝體
US20120146214A1 (en) * 2010-12-09 2012-06-14 Mehdi Frederik Soltan Semiconductor device with vias and flip-chip
US8779540B2 (en) * 2011-01-26 2014-07-15 Maxim Integrated Products, Inc. Light sensor having transparent substrate with lens formed therein
US8901701B2 (en) * 2011-02-10 2014-12-02 Chia-Sheng Lin Chip package and fabrication method thereof
US8890191B2 (en) * 2011-06-30 2014-11-18 Chuan-Jin Shiu Chip package and method for forming the same
US9153707B2 (en) * 2012-06-11 2015-10-06 Xintec Inc. Chip package and method for forming the same

Also Published As

Publication number Publication date
TW201519340A (zh) 2015-05-16
CN104637827A (zh) 2015-05-20
US9214579B2 (en) 2015-12-15
CN104637827B (zh) 2017-08-01
US20150123231A1 (en) 2015-05-07

Similar Documents

Publication Publication Date Title
TWI540655B (zh) 半導體結構及其製造方法
US10157811B2 (en) Chip package and method for forming the same
US10109663B2 (en) Chip package and method for forming the same
US9780251B2 (en) Semiconductor structure and manufacturing method thereof
JP5178569B2 (ja) 固体撮像装置
TWI600125B (zh) 晶片封裝體及其製造方法
TWI624039B (zh) 晶片封裝體及其製造方法
TWI640046B (zh) 晶片封裝體及其製作方法
US9450015B2 (en) Manufacturing method of semiconductor structure
TWI593121B (zh) 感測器裝置及其形成方法
TWI591764B (zh) 晶片封裝體及其製造方法
TW201532223A (zh) 晶片封裝體及其製造方法
TWI582918B (zh) 晶片封裝體及其製造方法
TWI585870B (zh) 晶片封裝體及其製造方法
US9865526B2 (en) Chip package and method for forming the same
TWI418002B (zh) 晶片封裝體及其製造方法
TWI603407B (zh) 晶片封裝體及其製造方法
TWI630712B (zh) 晶片封裝體及其製造方法
TWI564961B (zh) 半導體結構及其製造方法
US9236429B2 (en) Semiconductor structure and manufacturing method thereof
TWI549243B (zh) 半導體結構及其製造方法
TWI620286B (zh) 晶片封裝體及其製造方法