CN105590911A - 晶片封装体及其制造方法 - Google Patents
晶片封装体及其制造方法 Download PDFInfo
- Publication number
- CN105590911A CN105590911A CN201510736145.2A CN201510736145A CN105590911A CN 105590911 A CN105590911 A CN 105590911A CN 201510736145 A CN201510736145 A CN 201510736145A CN 105590911 A CN105590911 A CN 105590911A
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- Prior art keywords
- layer
- wafer
- perforation
- wafer encapsulation
- weld pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims description 83
- 238000005538 encapsulation Methods 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract 3
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- HOWHQWFXSLOJEF-MGZLOUMQSA-N systemin Chemical compound NCCCC[C@H](N)C(=O)N[C@@H](CCSC)C(=O)N[C@@H](CCC(N)=O)C(=O)N[C@@H]([C@@H](C)O)C(=O)N[C@@H](CC(O)=O)C(=O)OC(=O)[C@@H]1CCCN1C(=O)[C@H]1N(C(=O)[C@H](CC(O)=O)NC(=O)[C@H](CCCN=C(N)N)NC(=O)[C@H](CCCCN)NC(=O)[C@H](CO)NC(=O)[C@H]2N(CCC2)C(=O)[C@H]2N(CCC2)C(=O)[C@H](CCCCN)NC(=O)[C@H](CO)NC(=O)[C@H](CCC(N)=O)NC(=O)[C@@H](NC(=O)[C@H](C)N)C(C)C)CCC1 HOWHQWFXSLOJEF-MGZLOUMQSA-N 0.000 description 1
- 108010050014 systemin Proteins 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
- G06F21/31—User authentication
- G06F21/32—User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
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- H01L21/02008—Multistep processes
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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Abstract
一种晶片封装体及其制造方法,该晶片封装体包含晶片、激光阻档件、绝缘层、重布线层、阻隔层与导电结构。晶片具有焊垫、及相对的第一表面与第二表面。焊垫位于第一表面上。第二表面具有第一穿孔,使焊垫从第一穿孔裸露。激光阻档件位于第一穿孔中的焊垫上。绝缘层位于第二表面上与第一穿孔中。绝缘层具有相对第二表面的第三表面。绝缘层具有第二穿孔,使激光阻档件从第二穿孔裸露。重布线层位于第三表面上、第二穿孔的壁面上与第二穿孔中的激光阻档件上。阻隔层位于第三表面上与重布线层上。导电结构位于重布线层上,使导电结构电性连接焊垫。本发明不仅能节省制程的时间与机台的成本,还可提升晶片封装体侦测时的准确度。
Description
技术领域
本发明是有关一种晶片封装体及其制造方法。
背景技术
指纹感测装置(fingerprintsensor)或射频感测装置(RFsensor)需利用平坦的感测面来侦测信号。若感测面不平整,会影响感测装置侦测时的准确度。举例来说,当指头按压于指纹感测装置的感测面时,若感测面不平整,将难以侦测到完整的指纹。
此外,上述的感测装置在制作时,会先于晶圆中形成硅穿孔(ThroughSiliconVia;TSV),使焊垫从硅穿孔裸露。接着,会以化学气相沉积法(ChemicalVaporDeposition;CVD)在焊垫上与硅穿孔的壁面上形成绝缘层。之后,还需通过图案化制程于焊垫上的绝缘层形成开口。一般而言图案化制程包含曝光、显影与蚀刻制程。在后续制程中,重布线层便可形成在绝缘层上并电性连接绝缘层开口中的焊垫。
然而,化学气相沉积与图案化制程均需耗费大量的制程时间与机台的成本。
发明内容
本发明的一技术态样为一种晶片封装体。
根据本发明一实施方式,一种晶片封装体包含晶片、激光阻档件、绝缘层、重布线层、阻隔层与导电结构。晶片具有焊垫、及相对的第一表面与第二表面。焊垫位于第一表面上。第二表面具有第一穿孔,使焊垫从第一穿孔裸露。激光阻档件位于第一穿孔中的焊垫上。绝缘层位于第二表面上与第一穿孔中。绝缘层具有相对第二表面的第三表面。绝缘层具有第二穿孔,使激光阻档件从第二穿孔裸露。重布线层位于第三表面上、第二穿孔的壁面上与第二穿孔中的激光阻档件上。阻隔层位于第三表面上与重布线层上。阻隔层具有开口,使重布线层从开口裸露。导电结构位于开口中的重布线层上,使导电结构电性连接焊垫。
本发明的一技术态样为一种晶片封装体的制造方法。
根据本发明一实施方式,一种晶片封装体的制造方法包含下列步骤:(a)提供暂时接合的晶圆与支撑件,其中晶圆具有焊垫、及相对的第一表面与第二表面,焊垫位于第一表面,支撑件覆盖第一表面与焊垫;(b)在晶圆的第二表面中形成第一穿孔,使焊垫从第一穿孔裸露;(c)电镀激光阻档件于第一穿孔中的焊垫上;(d)形成绝缘层于晶圆的第二表面上与第一穿孔中,其中绝缘层具有相对第二表面的第三表面;(e)使用激光贯穿绝缘层以形成第二穿孔,其中激光由激光阻档件阻挡,且激光阻档件从第二穿孔裸露;(f)电镀重布线层于绝缘层的第三表面上、第二穿孔的壁面上与第二穿孔中的激光阻档件上。
在本发明上述实施方式中,由于激光阻档件位于第一穿孔中的焊垫上,因此当激光贯穿绝缘层时,激光可由激光阻档件阻挡,并于绝缘层形成裸露激光阻档件的第二穿孔。待第二穿孔形成后,便可电镀重布线层于绝缘层的第三表面上、第二穿孔的壁面上与第二穿孔中的激光阻档件上,使得重布线层可通过激光阻档件电性连接焊垫。本发明的晶片封装体及其制造方法可省略已知化学气相沉积绝缘层与图案化绝缘层的制程,能节省制程的时间与机台的成本。此外,晶片的第一表面未经额外的加工,因此平坦性佳,可提升晶片封装体侦测时的准确度。
附图说明
图1绘示根据本发明一实施方式的晶片封装体的俯视图。
图2绘示图1的晶片封装体沿线段2-2的剖面图。
图3绘示图2的晶片封装体的局部放大图。
图4绘示根据本发明一实施方式的晶片封装体的制造方法的流程图。
图5绘示根据本发明一实施方式的晶圆与支撑件的剖面图。
图6绘示图5的晶圆形成第一穿孔后的剖面图。
图7绘示图6的焊垫上形成激光阻档件后的剖面图。
图8绘示图7的晶圆的第二表面上与第一穿孔中形成绝缘层后的剖面图。
图9绘示图8的绝缘层形成第二穿孔后的剖面图。
图10绘示图9的绝缘层的第三表面、第二穿孔的壁面与激光阻档件上形成重布线层后的剖面图。
图11绘示图10的绝缘层与重布线层上形成阻隔层后的剖面图。
图12绘示图11的重布线层上形成导电结构后的剖面图。
其中,附图中符号的简单说明如下:
100:晶片封装体
110:晶片
110a:晶圆
112:焊垫
113:第一表面
114:第二表面
115:第一穿孔
120:激光阻档件
121:侧绝缘层
122:第四表面
130:绝缘层
132:第三表面
133:第二穿孔
134:壁面
140:重布线层
150:阻隔层
152:开口
160:导电结构
170:空穴
180:阻障层
210:支撑件
2-2:线段
D1~D2:孔径
D3~D5:厚度
L1:线段
L2:线段
S1~S6:步骤。
具体实施方式
以下将以图式揭露本发明的多个实施方式,为明确说明起见,许多实务上的细节将在以下叙述中一并说明。然而,应了解到,这些实务上的细节不应用以限制本发明。也就是说,在本发明部分实施方式中,这些实务上的细节是非必要的。此外,为简化图式起见,一些已知惯用的结构与元件在图式中将以简单示意的方式绘示。
图1绘示根据本发明一实施方式的晶片封装体100的俯视图。图2绘示图1的晶片封装体100沿线段2-2的剖面图。同时参阅图1与图2,晶片封装体100包含感测晶片110、激光阻档件120、绝缘层130、重布线层140(RedistributionLayer;RDL)、阻隔层150与导电结构160。晶片110具有焊垫112、及相对的第一表面113与第二表面114。第一表面113为感测面。焊垫112位于第一表面113上。第二表面114具有第一穿孔115,使焊垫112从第一穿孔115裸露。激光阻档件120位于第一穿孔115中的焊垫112上。绝缘层130位于晶片110的第二表面114上与第一穿孔115中。绝缘层130具有相对晶片110第二表面114的第三表面132。绝缘层130具有第二穿孔133,使激光阻档件120从第二穿孔133裸露。重布线层140位于绝缘层130的第三表面132上、第二穿孔133的壁面上与第二穿孔133中的激光阻档件120上。阻隔层150位于绝缘层130的第三表面132上与重布线层140上。阻隔层150具有开口152,使重布线层140从开口152裸露。导电结构160位于开口152中的重布线层140上,使导电结构160可通过重布线层140与激光阻档件120电性连接焊垫112。此外,晶片封装体100还可包含侧绝缘层121。侧绝缘层121位于第一穿孔115的壁面上,且侧绝缘层121位于激光阻档件120与晶片110之间,可防止激光阻档件120与晶片110直接接触而造成短路。
在本实施方式中,晶片封装体100可以为指纹感测装置(fingerprintsensor)或射频感测装置(RFsensor),但并不用以限制本发明。晶片110的材质可以包含硅。激光阻档件120的材质可以包含金或铜,可采用电镀的方式形成。重布线层140的材质可以包含铜,亦可采用电镀的方式形成。绝缘层130的材质可以包含环氧树脂(epoxy)。
图3绘示图2的晶片封装体100的局部放大图。激光阻档件120具有朝向重布线层140的第四表面122。第二穿孔133可利用激光贯穿绝缘层130而形成。通过激光的使用,第二穿孔133的孔径D2可小于第一穿孔115的孔径D1,对于微小化设计有所助益。由于第二穿孔133由激光形成,因此第二穿孔133的壁面134与激光阻档件120的第四表面122均为粗糙面。第二穿孔133的壁面134为绝缘层130朝向第二穿孔133的表面。
由于激光阻档件120位于焊垫112上,因此当激光贯穿绝缘层130时,激光可由激光阻档件120阻挡,并于绝缘层130形成裸露激光阻档件120的第二穿孔133。待第二穿孔133形成后,便可以化镀加电镀重布线层140于绝缘层130的第三表面132上、第二穿孔133的壁面134上与第二穿孔133中的激光阻档件120上,使得重布线层140可电性连接焊垫112。
此外,由于重布线层140是以电镀的方式形成,因此重布线层140在绝缘层130的第三表面132上的厚度D3大于重布线层140在第二穿孔133的壁面134上的厚度D4,且重布线层140在第二穿孔133的壁面134上的厚度D4大于重布线层140在激光阻档件120上的厚度D5。
在本实施方式中,晶片封装体100还具有空穴170,且空穴170位于阻隔层150与第二穿孔133中的重布线层140之间。晶片封装体100还可具有阻障层180。阻障层180位于焊垫112与激光阻档件120之间。阻障层180用以提升激光阻档件120在焊垫112的附着力。当激光阻档件120的材质包含金时,阻障层180的材质可包含镍;当激光阻档件120的材质包含铜时,阻障层180的材质可包含钛。
在以下叙述中,将说明晶片封装体100的制造方法。
图4绘示根据本发明一实施方式的晶片封装体的制造方法的流程图。晶片封装体的制造方法包含下列步骤。在步骤S1中,提供暂时接合的晶圆与支撑件,其中晶圆具有焊垫、及相对的第一表面与第二表面,焊垫位于第一表面,支撑件覆盖第一表面与焊垫。接着在步骤S2中,在晶圆的第二表面中形成第一穿孔,使焊垫从第一穿孔裸露。之后在步骤S3中,电镀激光阻档件于第一穿孔中的焊垫上。接着在步骤S4中,形成绝缘层于晶圆的第二表面上与第一穿孔中,其中绝缘层具有相对第二表面的第三表面。之后在步骤S5中,使用激光贯穿绝缘层以形成第二穿孔,其中激光由激光阻档件阻挡,且激光阻档件从第二穿孔裸露。最后在步骤S6中,电镀重布线层于绝缘层的第三表面上、第二穿孔的壁面上与第二穿孔中的激光阻档件上。在以下叙述中,将说明上述步骤。
图5绘示根据本发明一实施方式的晶圆110a与支撑件210的剖面图。晶圆110a意指切割后可形成复数个图2的晶片110的半导体基板。首先,可提供暂时接合的晶圆110a与支撑件210,其中晶圆110a具有焊垫112、及相对的第一表面113与第二表面114,焊垫112位于第一表面113,支撑件210覆盖第一表面113与焊垫112。支撑件210可提供晶圆110a支撑力,防止晶圆110a在后续制程中因受力而破裂。待接合支撑件210于晶圆110a后,可研磨晶圆110a的第二表面114,以减薄晶圆110a的厚度。
图6绘示图5的晶圆110a形成第一穿孔115后的剖面图。同时参阅图5与图6,接着,可在晶圆110a的第二表面114中形成第一穿孔115,使焊垫112从第一穿孔115裸露。在此步骤中,可采用蚀刻制程在晶圆110a中形成第一穿孔115,例如干蚀刻制程。
图7绘示图6的焊垫112上形成激光阻档件120后的剖面图。同时参阅图6与图7,待第一穿孔115形成后,可形成侧绝缘层121于第一穿孔115的壁面上。接着,电镀激光阻档件120于第一穿孔115中的焊垫112上,使得激光阻档件120与晶圆110a之间由侧绝缘层121隔开。此外,为了提升激光阻档件120在焊垫112的附着力,还可先电镀阻障层180(见图3)于焊垫112上后,接着才电镀激光阻档件120。
图8绘示图7的晶圆110a的第二表面114上与第一穿孔115中形成绝缘层130后的剖面图。待激光阻档件120形成后,便可形成绝缘层130于晶圆110a的第二表面114上与第一穿孔115中,其中绝缘层130具有相对第二表面114的第三表面132。在此步骤中,绝缘层130可采用印刷的方式形成于晶圆110a的第二表面114上与第一穿孔115中。接着,设计者可以涂布、研磨、压印、制模方式处理绝缘层130的第三表面132,以减薄绝缘层130的厚度。
图9绘示图8的绝缘层130形成第二穿孔133后的剖面图。同时参阅图8与图9,待图8的结构形成后,可使用激光贯穿绝缘层130以形成第二穿孔133。激光可由焊垫112上的激光阻档件120阻挡,使激光阻档件120从第二穿孔133裸露。此外,激光是对准第一穿孔115与激光阻档件120发射,因此第二穿孔133可由第一穿孔115环绕。
图10绘示图9的绝缘层130的第三表面132、第二穿孔133的壁面与激光阻档件120上形成重布线层140后的剖面图。同时参阅图9与图10,待第二穿孔133形成于绝缘层130中后,可电镀重布线层140于绝缘层130的第三表面132上、第二穿孔133的壁面上与第二穿孔133中的激光阻档件120上。
图11绘示图10的绝缘层130与重布线层140上形成阻隔层150后的剖面图。同时参阅图10与图11,待图10的结构形成后,可形成阻隔层150于绝缘层130的第三表面132上与重布线层140上。接着,可图案化阻隔层150以形成开口152,使部分的重布线层140可从阻隔层150的开口152裸露。
图12绘示图11的重布线层140上形成导电结构160后的剖面图。同时参阅图11与图12,待阻隔层150的开口152形成后,可形成导电结构160于开口152中的重布线层140上,使得导电结构160可通过重布线层140与激光阻档件120电性连接焊垫112。在此步骤后,便可移除晶圆110a的第一表面113上的支撑件210。
最后,可沿线段L1、L2切割晶圆110a、绝缘层130与阻隔层150,以形成图2的晶片封装体100。
本发明的晶片封装体及其制造方法可省略已知化学气相沉积绝缘层与图案化绝缘层的制程,能节省制程的时间与机台的成本。此外,晶片的第一表面未经额外的加工,因此平坦性佳,可提升晶片封装体侦测时的准确度。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
Claims (22)
1.一种晶片封装体,其特征在于,包含:
一晶片,具有一焊垫、及相对的一第一表面与一第二表面,其中该焊垫位于该第一表面上,该第二表面具有一第一穿孔,使该焊垫从该第一穿孔裸露;
一激光阻档件,位于该第一穿孔中的该焊垫上;
一绝缘层,位于该第二表面上与该第一穿孔中,该绝缘层具有相对该第二表面的一第三表面,该绝缘层具有一第二穿孔,使该激光阻档件从该第二穿孔裸露;
一重布线层,位于该第三表面上、该第二穿孔的一壁面上与该第二穿孔中的该激光阻档件上;
一阻隔层,位于该第三表面上与该重布线层上,该阻隔层具有一开口,使该重布线层从该开口裸露;以及
一导电结构,位于该开口中的该重布线层上,使该导电结构电性连接该焊垫。
2.根据权利要求1所述的晶片封装体,其特征在于,该第二穿孔的孔径小于该第一穿孔的孔径。
3.根据权利要求1所述的晶片封装体,其特征在于,还具有一空穴,且该空穴位于该阻隔层与该第二穿孔中的该重布线层之间。
4.根据权利要求1所述的晶片封装体,其特征在于,该第二穿孔的该壁面为一粗糙面。
5.根据权利要求1所述的晶片封装体,其特征在于,该激光阻档件具有朝向该重布线层的一第四表面,且该第四表面为一粗糙面。
6.根据权利要求1所述的晶片封装体,其特征在于,该重布线层在该绝缘层的该第三表面上的厚度大于该重布线层在该第二穿孔的该壁面上的厚度。
7.根据权利要求1所述的晶片封装体,其特征在于,该重布线层在该第二穿孔的该壁面上的厚度大于该重布线层在该激光阻档件上的厚度。
8.根据权利要求1所述的晶片封装体,其特征在于,该绝缘层的材质包含环氧树脂。
9.根据权利要求1所述的晶片封装体,其特征在于,还包含:
一阻障层,位于该焊垫与该激光阻档件之间。
10.根据权利要求9所述的晶片封装体,其特征在于,该阻障层的材质包含镍,该激光阻档件的材质包含金。
11.根据权利要求9所述的晶片封装体,其特征在于,该阻障层的材质包含钛,该激光阻档件的材质包含铜。
12.根据权利要求1所述的晶片封装体,其特征在于,还包含:
一侧绝缘层,位于该第一穿孔的壁面上,且该侧绝缘层位于该激光阻档件与该晶片之间。
13.一种晶片封装体的制造方法,其特征在于,包含:
(a)提供暂时接合的一晶圆与一支撑件,其中该晶圆具有一焊垫、及相对的一第一表面与一第二表面,该焊垫位于该第一表面,该支撑件覆盖该第一表面与该焊垫;
(b)在该晶圆的该第二表面中形成一第一穿孔,使该焊垫从该第一穿孔裸露;
(c)电镀一激光阻档件于该第一穿孔中的该焊垫上;
(d)形成一绝缘层于该晶圆的该第二表面上与该第一穿孔中,其中该绝缘层具有相对该第二表面的一第三表面;
(e)使用一激光贯穿该绝缘层以形成一第二穿孔,其中该激光由该激光阻档件阻挡,且该激光阻档件从该第二穿孔裸露;以及
(f)电镀一重布线层于该绝缘层的该第三表面上、该第二穿孔的一壁面上与该第二穿孔中的该激光阻档件上。
14.根据权利要求13所述的晶片封装体的制造方法,其特征在于,还包含:
形成一阻隔层于该绝缘层的该第三表面上与该重布线层上;以及
图案化该阻隔层以形成一开口,使该重布线层从该开口裸露。
15.根据权利要求14所述的晶片封装体的制造方法,其特征在于,还包含:
形成一导电结构于该开口中的该重布线层上。
16.根据权利要求14所述的晶片封装体的制造方法,其特征在于,还包含:
切割该晶圆、该绝缘层与该阻隔层,以形成该晶片封装体。
17.根据权利要求13所述的晶片封装体的制造方法,其特征在于,还包含:
研磨该晶圆的该第二表面。
18.根据权利要求13所述的晶片封装体的制造方法,其特征在于,该步骤(d)包含:
印刷该绝缘层于该晶圆的该第二表面上与该第一穿孔中。
19.根据权利要求13所述的晶片封装体的制造方法,其特征在于,还包含:
压印、涂布、制模、研磨该绝缘层的该第三表面。
20.根据权利要求13所述的晶片封装体的制造方法,其特征在于,还包含:
移除该晶圆的该第一表面上的该支撑件。
21.根据权利要求13所述的晶片封装体的制造方法,其特征在于,还包含:
电镀一阻障层于该焊垫上。
22.根据权利要求13所述的晶片封装体的制造方法,其特征在于,还包含:
形成一侧绝缘层于该第一穿孔的壁面上。
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WO2018145413A1 (zh) * | 2017-02-13 | 2018-08-16 | 深圳市汇顶科技股份有限公司 | 硅通孔芯片的二次封装方法及其二次封装体 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000323516A (ja) * | 1999-05-14 | 2000-11-24 | Fujitsu Ltd | 配線基板の製造方法及び配線基板及び半導体装置 |
US20030042618A1 (en) * | 2001-08-29 | 2003-03-06 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
CN1838406A (zh) * | 2005-03-24 | 2006-09-27 | 矽统科技股份有限公司 | 封装结构与其封装方法 |
CN103094479A (zh) * | 2013-02-21 | 2013-05-08 | 吉林大学 | 一种在有机电子器件薄膜封装过程中保护电极的方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7091124B2 (en) * | 2003-11-13 | 2006-08-15 | Micron Technology, Inc. | Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices |
US8513119B2 (en) * | 2008-12-10 | 2013-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bump structure having tapered sidewalls for stacked dies |
US8791549B2 (en) * | 2009-09-22 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside interconnect structure connected to TSVs |
TWI416685B (zh) * | 2010-03-04 | 2013-11-21 | Unimicron Technology Corp | 封裝基板及其製法 |
CN102592982B (zh) * | 2011-01-17 | 2017-05-03 | 精材科技股份有限公司 | 晶片封装体的形成方法 |
TWI581325B (zh) * | 2014-11-12 | 2017-05-01 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
-
2015
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000323516A (ja) * | 1999-05-14 | 2000-11-24 | Fujitsu Ltd | 配線基板の製造方法及び配線基板及び半導体装置 |
US20030042618A1 (en) * | 2001-08-29 | 2003-03-06 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
CN1838406A (zh) * | 2005-03-24 | 2006-09-27 | 矽统科技股份有限公司 | 封装结构与其封装方法 |
CN103094479A (zh) * | 2013-02-21 | 2013-05-08 | 吉林大学 | 一种在有机电子器件薄膜封装过程中保护电极的方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108074823A (zh) * | 2016-11-14 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法和电子装置 |
WO2018145413A1 (zh) * | 2017-02-13 | 2018-08-16 | 深圳市汇顶科技股份有限公司 | 硅通孔芯片的二次封装方法及其二次封装体 |
US11183414B2 (en) | 2017-02-13 | 2021-11-23 | Shenzhen GOODIX Technology Co., Ltd. | Secondary packaging method and secondary package of through silicon via chip |
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