TW201703214A - 晶片封裝體及其製造方法 - Google Patents
晶片封裝體及其製造方法 Download PDFInfo
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- TW201703214A TW201703214A TW105102230A TW105102230A TW201703214A TW 201703214 A TW201703214 A TW 201703214A TW 105102230 A TW105102230 A TW 105102230A TW 105102230 A TW105102230 A TW 105102230A TW 201703214 A TW201703214 A TW 201703214A
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 113
- 239000011241 protective layer Substances 0.000 claims description 42
- 230000004888 barrier function Effects 0.000 claims description 19
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 claims description 2
- 239000007787 solid Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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Abstract
一種晶片封裝體包含晶片、介電接合層、載體與重佈線層。晶片具有基底、焊墊與保護層。保護層位於基底上。焊墊位於保護層中。介電接合層位於保護層上,且介電接合層位於載體與保護層之間。載體、介電接合層與保護層具有連通的穿孔,使焊墊從穿孔裸露。重佈線層包含連接部與被動元件部。連接部位於焊墊、穿孔的壁面與載體背對介電接合層的表面上。被動元件部位於載體的表面上,且被動元件部的一端連接在載體之表面上的連接部。
Description
本發明是有關一種晶片封裝體及一種晶片封裝體的製造方法。
習知的射頻感測器(RF sensor)包含晶片封裝體與被動元件,其中被動元件例如電感元件(inductor)。晶片封裝體作為主動元件。晶片封裝體與電感元件均設置於電路板上,且電感元件位於晶片封裝體外。
也就是說,當晶片封裝體製作完成後,還需在電路板設置獨立的電感元件才可讓射頻感測器正常工作。如此一來,射頻感測器會花費大量的組裝時間,且電感元件的成本難以降低。此外,電路板還需預留安裝電感元件的空間與線路,造成設計上的不便。
本發明之一技術態樣為一種晶片封裝體。
根據本發明一實施方式,一種晶片封裝體包含晶片、介電接合層、載體與重佈線層。晶片具有基底、焊墊與保
護層。保護層位於基底上。焊墊位於保護層中。介電接合層位於保護層上,且介電接合層位於載體與保護層之間。載體、介電接合層與保護層具有連通的穿孔,使焊墊從穿孔裸露。重佈線層包含連接部與被動元件部。連接部位於焊墊、穿孔的壁面與載體背對介電接合層的表面上。被動元件部位於載體的表面上,且被動元件部的一端連接在載體之表面上的連接部。
本發明之一技術態樣為一種晶片封裝體的製造方法。
根據本發明一實施方式,一種晶片封裝體的製造方法包含下列步驟。使用介電接合層將載體貼附於晶圓上,其中晶圓具有基底、焊墊與保護層,焊墊位於保護層中,介電接合層位於保護層與載體之間。蝕刻載體背對介電接合層的表面,使載體、介電接合層與保護層具有連通的穿孔,且焊墊從穿孔裸露。形成重佈線層於焊墊、該穿孔的壁面與載體的表面上。圖案化重佈線層,使重佈線層同步形成連接部與被動元件部,連接部位於焊墊、穿孔的壁面與載體的表面上,被動元件部位於載體的表面上,且被動元件部的一端連接在載體之表面上的連接部。
在本發明上述實施方式中,由於晶片封裝體的重佈線層具有被動元件部,因此晶片封裝體除了具有主動元件的功能外,還具有被動元件的功能。舉例來說,被動元件部可作為晶片封裝體的電感元件。載體具有支撐重佈線層的功能。當圖案化重佈線層時,被動元件部與連接部會同步形成,使被動元件部形成於載體的表面上,因此可節省製作被動元件部的時
間。本發明的晶片封裝體可作為射頻感測器,不需習知獨立的電感元件便具有電感元件的功能。如此一來,晶片封裝體不僅可節省大量的組裝時間,且能降低習知電感元件的成本。此外,設置晶片封裝體的電路板不需預留安裝習知電感元件的空間與線路,可提升設計上的便利性。
100~100b‧‧‧晶片封裝體
110‧‧‧晶片
110a‧‧‧晶圓
112‧‧‧基底
113‧‧‧表面
114‧‧‧焊墊
115‧‧‧穿孔
116‧‧‧保護層
120‧‧‧介電接合層
130‧‧‧載體
132‧‧‧表面
140‧‧‧重佈線層
142‧‧‧連接部
144‧‧‧被動元件部
150‧‧‧阻隔層
152‧‧‧開口
160‧‧‧導電結構
170‧‧‧空穴
180‧‧‧磁性元件
D1~D4‧‧‧厚度
L-L‧‧‧線段
L1‧‧‧導線
S1~S4‧‧‧步驟
第1圖繪示根據本發明一實施方式之晶片封裝體的剖面圖。
第2圖繪示第1圖之晶片封裝體之重佈線層的線路布局示意圖。
第3圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。
第4圖繪示根據本發明一實施方式之晶圓被載體貼附後的剖面圖。
第5圖繪示第4圖之載體研磨後的剖面圖。
第6圖繪示第5圖之載體、介電接合層與保護層形成穿孔後的剖面圖。
第7圖繪示第6圖之焊墊、穿孔的壁面與載體形成重佈線層後的剖面圖。
第8圖繪示第7圖之重佈線層形成導電結構後的剖面圖。
第9圖繪示第8圖之基底研磨後的剖面圖。
第10A圖繪示根據本發明一實施方式之晶片封裝體的剖面圖。
第10B圖繪示第10A圖之晶片封裝體之重佈線層的線路布局示意圖。
第11A圖繪示根據本發明一實施方式之晶片封裝體的剖面圖。
第11B圖繪示第11A圖之晶片封裝體之重佈線層的線路布局示意圖。
第11C圖繪示第11B圖的另一實施方式。
以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1圖繪示根據本發明一實施方式之晶片封裝體100的剖面圖。第2圖繪示第1圖之晶片封裝體100之重佈線層140的線路布局示意圖。同時參閱第1圖與第2圖,晶片封裝體100包含晶片110、介電接合層120、載體130與重佈線層140。晶片110具有基底112、焊墊114與保護層116。保護層116位於基底112上。焊墊114位於保護層116中。介電接合層120位於保護層116上,且介電接合層120位於載體130與保護層116之
間。載體130、介電接合層120與保護層116具有連通的穿孔115,使焊墊114從穿孔115裸露。重佈線層140包含連接部142與被動元件部144。連接部142位於焊墊114、穿孔115的壁面與載體130背對介電接合層120的表面132上。被動元件部144位於載體130的表面132上,且被動元件部144的一端連接在載體130之表面132上的連接部142。
在本實施方式中,晶片封裝體100可以為射頻感測器(RF sensor),但並不用以限制本發明。基底112的材質可以包含矽。保護層116可包含內層介電層(ILD)、內金屬介電層(IMD)與鈍化層(passivation layer)。介電接合層120的材質包含聚合物(polymer)或氧化物。載體130的材質可以包含氮化鋁或玻璃,具高阻抗與高介電常數,可減少晶片封裝體100的功率損失,節省電力。重佈線層140的材質可以包含鋁或銅,可先採用物理氣相沉積(PVD)或電鍍的方式覆蓋焊墊114、穿孔115的壁面與載體130後,再利用圖案化製程使重佈線層140同步形成連接部142與被動元件部144。圖案化製程可包含曝光、顯影與蝕刻等光微影技術。
由於晶片封裝體100的重佈線層140具有被動元件部144,因此晶片封裝體100除了具有主動元件的功能外,還具有被動元件的功能。舉例來說,被動元件部144可作為晶片封裝體100的電感元件(inductor)。本發明的晶片封裝體100不需習知獨立的電感元件便具有電感元件的功能。如此一來,晶片封裝體100不僅可節省大量的組裝時間,且能降低習知電感元件的成本。
載體130具有支撐重佈線層140的功能。當圖案化重佈線層140時,被動元件部144與連接部142會同步形成,使被動元件部144形成於載體130的表面132上,因此可節省製作被動元件部144的時間。此外,設置晶片封裝體100的電路板不需預留安裝習知電感元件的空間與線路,可提升設計上的便利性。
在本實施方式中,被動元件部144的形狀為U形,但並不此為限。設計者可依實際需求設計重佈線層140的線路布局,使被動元件部144具有其他形狀。
晶片封裝體100還包含阻隔層150與導電結構160。阻隔層150位於重佈線層140上與載體130的表面132上。阻隔層150具有開口152,使連接部142裸露。導電結構160位於阻隔層150之開口152中的連接部142上,使導電結構160可透過重佈線層140的連接部142電性連接焊墊114。導電結構160可以球閘陣列(BGA)的錫球或導電凸塊。此外,晶片封裝體100還可選擇性具有空穴170。空穴170位於阻隔層150與穿孔115中的連接部142之間。
在以下敘述中,將說明晶片封裝體100的製造方法。
第3圖繪示根據本發明一實施方式之晶片封裝體的製造方法的流程圖。晶片封裝體的製造方法包含下列步驟。在步驟S1中,使用介電接合層將載體貼附於晶圓上,其中晶圓具有基底、焊墊與保護層,焊墊位於保護層中,介電接合層位於保護層與載體之間。接著在步驟S2中,蝕刻載體背對介電接
合層的表面,使載體、介電接合層與保護層具有連通的穿孔,且焊墊從穿孔裸露。之後在步驟S3中,形成重佈線層於焊墊、該穿孔的壁面與載體的表面上。接著在步驟S4中,圖案化重佈線層,使重佈線層同步形成連接部與被動元件部,連接部位於焊墊、穿孔的壁面與載體的表面上,被動元件部位於載體的表面上,且被動元件部的一端連接在載體之表面上的連接部。在以下敘述中,將說明上述步驟。
第4圖繪示根據本發明一實施方式之晶圓110a被載體130貼附後的剖面圖。第5圖繪示第4圖之載體130研磨後的剖面圖。在以下敘述中,晶圓110a意指第1圖之晶片110尚未經切割製程的半導體結構。晶圓110a具有基底112、焊墊114與保護層116。同時參閱第4圖與第5圖,首先,可使用介電接合層120將載體130貼附於晶圓110a上,使介電接合層120位於保護層116與載體130之間。載體130的材質可包含氮化鋁或玻璃,可提供晶圓110a支撐強度。接著,可研磨載體130背對介電接合層120的表面132,以減薄載體130的厚度,使載體130的厚度D1減薄至厚度D2。
第6圖繪示第5圖之載體130、介電接合層120與保護層116形成穿孔115後的剖面圖。同時參閱第5圖與第6圖,待載體130減薄後,可蝕刻載體130的表面132,使載體130、介電接合層120與保護層116具有連通的穿孔115。穿孔115對齊焊墊114,因此焊墊114可從穿孔115裸露。
第7圖繪示第6圖之焊墊114、穿孔115的壁面與載體130形成重佈線層140後的剖面圖。同時參閱第6圖與第7
圖,待焊墊114從穿孔115裸露後,可於焊墊114、穿孔115的壁面與載體130的表面132上形成重佈線層140。接著,圖案化重佈線層140,使重佈線層140同步形成連接部142與被動元件部144。其中,連接部142位於焊墊114、穿孔115的壁面與載體130的表面132上。被動元件部144位於載體130的表面132上,且被動元件部144的一端連接載體130之表面132上的連接部142。
第8圖繪示第7圖之重佈線層140形成導電結構160後的剖面圖。同時參閱第7圖與第8圖,待重佈線層140經圖案化形成連接部142與被動元件部144後,可於重佈線層140上與載體130的表面132上形成阻隔層150。接著,圖案化阻隔層150以形成開口152,使重佈線層140的連接部142從開口152裸露。之後,便可於阻隔層150之開口152中的連接部142上形成導電結構160,使導電結構160經由連接部142電性連接焊墊114。
第9圖繪示第8圖之基底112研磨後的剖面圖。同時參閱第8圖與第9圖,待導電結構160形成後,可研磨基底112背對保護層116的表面113,以減薄基底112的厚度,使基底112的厚度D3減薄至厚度D4。接著,可沿線段L-L切割晶圓110a、介電接合層120、載體130與阻隔層150。如此一來,便可得到第1圖之晶片封裝體100。
在以下敘述中,已敘述過的元件連接關係與材料將不再重複贅述,僅敘述其他型式的晶片封裝體。
第10A圖繪示根據本發明一實施方式之晶片封裝體100a的剖面圖。第10B圖繪示第10A圖之晶片封裝體100a之重佈線層140的線路布局示意圖。同時參閱第10A圖與第10B圖,晶片封裝體100a包含晶片110、介電接合層120、載體130與重佈線層140。重佈線層140包含連接部142與被動元件部144。與第1圖、第2圖實施方式不同的地方在於:被動元件部144的形狀為平面螺旋狀。晶片110具有位於保護層116中的導線L1,且導線L1連接焊墊114與相鄰的另一焊墊114。
第11A圖繪示根據本發明一實施方式之晶片封裝體100b的剖面圖。第11B圖繪示第11A圖之晶片封裝體100b之重佈線層140的線路布局示意圖。同時參閱第11A圖與第11B圖,晶片封裝體100b包含晶片110、介電接合層120、載體130與重佈線層140。重佈線層140包含連接部142與被動元件部144。與第1圖、第2圖實施方式不同的地方在於:被動元件部144的形狀為立體螺旋狀。也就是說,被動元件部144的位置並非在同一水平面上。
第11C圖繪示第11B圖的另一實施方式。同時參閱第11A圖與第11C圖,晶片封裝體100b包含晶片110、介電接合層120、載體130與重佈線層140。重佈線層140包含連接部142與被動元件部144。與第11B圖實施方式不同的地方在於:晶片110還包含磁性元件180,且磁性元件180由重佈線層140的被動元件部144環繞。在本實施方式中,磁性元件180可提高晶片封裝體100b的感值(inductance value)。
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧晶片封裝體
110‧‧‧晶片
112‧‧‧基底
114‧‧‧焊墊
115‧‧‧穿孔
116‧‧‧保護層
120‧‧‧介電接合層
130‧‧‧載體
132‧‧‧表面
140‧‧‧重佈線層
142‧‧‧連接部
144‧‧‧被動元件部
150‧‧‧阻隔層
152‧‧‧開口
160‧‧‧導電結構
170‧‧‧空穴
Claims (16)
- 一種晶片封裝體,包含:一晶片,具有一基底、一焊墊與一保護層,該保護層位於該基底上,該焊墊位於該保護層中;一介電接合層,位於該保護層上;一載體,該介電接合層位於該載體與該保護層之間,該載體、該介電接合層與該保護層具有連通的一穿孔,使該焊墊從該穿孔裸露;以及一重佈線層,包含:一連接部,位於該焊墊、該穿孔的壁面與該載體背對該介電接合層的一表面上;以及一被動元件部,位於該載體的該表面上,且該被動元件部的一端連接在該載體之該表面上的該連接部。
- 如請求項1所述之晶片封裝體,其中該被動元件部的形狀包含U形、平面螺旋狀與立體螺旋狀。
- 如請求項1所述之晶片封裝體,更包含:一阻隔層,位於該重佈線層上與該載體的該表面上。
- 如請求項3所述之晶片封裝體,其中該阻隔層具有一開口,使該連接部裸露,該晶片封裝體更包含:一導電結構,位於該阻隔層之該開口中的該連接部上,使該導電結構電性連接該焊墊。
- 如請求項4所述之晶片封裝體,其中該導電結構為錫球或導電凸塊。
- 如請求項3所述之晶片封裝體,具有一空穴,且該空穴位於該阻隔層與該穿孔中的該連接部之間。
- 如請求項1所述之晶片封裝體,其中該晶片更包含:一磁性元件,由該被動元件部環繞。
- 如請求項1所述之晶片封裝體,其中該載體的材質包含氮化鋁或玻璃。
- 如請求項1所述之晶片封裝體,其中該介電接合層的材質包含聚合物或氧化物。
- 如請求項1所述之晶片封裝體,其中該晶片具有位於該保護層中的一導線,且該導線連接該焊墊與相鄰的另一焊墊。
- 一種晶片封裝體的製造方法,包含下列步驟:使用一介電接合層將一載體貼附於一晶圓上,其中該晶圓具有一基底、一焊墊與一保護層,該焊墊位於該保護層中,該介電接合層位於該保護層與該載體之間; 蝕刻該載體背對該介電接合層的一表面,使該載體、該介電接合層與該保護層具有連通的一穿孔,且該焊墊從該穿孔裸露;形成一重佈線層於該焊墊、該穿孔的壁面與該載體的該表面上;以及圖案化該重佈線層,使該重佈線層同步形成一連接部與一被動元件部,該連接部位於該焊墊、該穿孔的壁面與該載體的該表面上,該被動元件部位於該載體的該表面上,且該被動元件部的一端連接在該載體之該表面上的該連接部。
- 如請求項11所述之晶片封裝體的製造方法,更包含:研磨該載體的該表面,以減薄該載體的厚度。
- 如請求項11所述之晶片封裝體的製造方法,更包含:形成一阻隔層於該重佈線層上與該載體的該表面上;以及圖案化該阻隔層以形成一開口,使該連接部從該開口裸露。
- 如請求項13所述之晶片封裝體的製造方法,更包含:形成一導電結構於該阻隔層之該開口中的該連接部上,使該導電結構電性連接該焊墊。
- 如請求項14所述之晶片封裝體的製造方法,更包含:切割該晶圓、該介電接合層、該載體與該阻隔層。
- 如請求項11所述之晶片封裝體的製造方法,更包含:研磨該基底背對該保護層的一表面,以減薄該基底的厚度。
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CN106876290A (zh) | 2017-03-10 | 2017-06-20 | 三星半导体(中国)研究开发有限公司 | 晶圆级扇出型封装件及其制造方法 |
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US5234860A (en) * | 1992-03-19 | 1993-08-10 | Eastman Kodak Company | Thinning of imaging device processed wafers |
US8217272B2 (en) * | 2009-12-18 | 2012-07-10 | Intel Corporation | Apparatus and method for embedding components in small-form-factor, system-on-packages |
US8692382B2 (en) * | 2010-03-11 | 2014-04-08 | Yu-Lin Yen | Chip package |
US8698316B2 (en) * | 2010-03-11 | 2014-04-15 | Yu-Lin Yen | Chip package |
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US9006896B2 (en) * | 2012-05-07 | 2015-04-14 | Xintec Inc. | Chip package and method for forming the same |
US9553208B2 (en) * | 2013-09-16 | 2017-01-24 | Infineon Technologies Ag | Current sensor device |
US20150237732A1 (en) * | 2014-02-18 | 2015-08-20 | Qualcomm Incorporated | Low-profile package with passive device |
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