TWI286825B - Stacked semiconductor package - Google Patents

Stacked semiconductor package Download PDF

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Publication number
TWI286825B
TWI286825B TW093105058A TW93105058A TWI286825B TW I286825 B TWI286825 B TW I286825B TW 093105058 A TW093105058 A TW 093105058A TW 93105058 A TW93105058 A TW 93105058A TW I286825 B TWI286825 B TW I286825B
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TW
Taiwan
Prior art keywords
substrate
wafer
package
pin
semiconductor
Prior art date
Application number
TW093105058A
Other languages
English (en)
Other versions
TW200427012A (en
Inventor
Wataru Kikuchi
Toshio Sugano
Satoshi Isa
Original Assignee
Elpida Memory Inc
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Publication date
Application filed by Elpida Memory Inc filed Critical Elpida Memory Inc
Publication of TW200427012A publication Critical patent/TW200427012A/zh
Application granted granted Critical
Publication of TWI286825B publication Critical patent/TWI286825B/zh

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
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五'發明說明（1) 【發明所屬之技術領域】 t發明係有關於一種堆疊式半導體封裝，特別是有關 於堆豐式DRAM封裝以形成高速資料傳輸。 【先前技術】 請參照第1圖’常見的堆疊式半導體封裝包括數個可 $之半導體封裝’其中個別之可堆疊的半導體封裝包 一形成於上表面中央位置之具有一凹處101之基板 ，一由基板102之上表面延伸至下表面之導線圖案 103，一配置於基板102之凹處1〇1中之半導體晶片1〇^， 數個連接半導體晶片104以及導線圖案103之金屬線105， =數個位於基板102上表面且連接導線圖案1〇3之末端銲墊 106，以及一複數個位於基板102下表面用以連接並固定導 線圖案1 0 3之銲錫球1 〇 7。 末端銲墊106於圖案上與銲錫球丨〇7排列一致，亦即若 將此類複數個可堆疊之半導體封裝拆開再堆疊時，位於上 層封裝之銲錫球107將一 一對應至鄰接之下層封裝、 =墊106。所以，藉由堆疊複數個可堆疊之半導體封裝並 完成迴銲（reflowing)步驟後，即可得到一堆疊複數^半 導體晶片且相互連接之堆疊式封裝。 吻參照第2圖，另一常見的堆疊式半導體封裝包括 導體晶片111以及個別包覆半導體晶片i u之彈性t基板 112 ° 請參照第3圖，每一個堆疊式半導體封裝之半導體晶 2130-6196-PF(N2) ;Uofung.ptd 五、發明說明（2) 片in，如第2圖所示，具有一提供複數個接點121之下表 此外，每一個彈性基板112之上表面具有對應於接點 121之第一傳導銲墊陣列122排列之圖案（可逆圖案）^彈性 基板112之下表層具有第二傳導銲塾陣列，且與第一傳導 銲墊陣+列1 2 2以垂直方向重疊對齊（即排列之圖案與接點 1 21相符），第二以及第四傳導銲墊陣列形成於第二傳導銲 ，陣列之對側。每個第三以及第四傳導銲墊陣列以對應之 ^個第二傳導銲墊陣列之可逆圖案方式排列並透過導線圖 案連接。 當半導體晶片111架設於彈性基板11 2之上表層時，半 體阳片111之接點121連接於第一傳導銲墊陣列Kg之第 傳‘銲墊，並且透過彈性基板丨丨2，其亦位於彈性基板 之下^表層之第二傳導銲墊陣列之第二傳導銲墊。據此 一淪，每個半導體晶片111之接點121係連接於相對應之第 二以及第四傳導銲墊陣列之銲墊之一。當該彈性基板〗2對 ”以包覆該第二半導體晶片11丨時，該第三以及第四傳導 銲墊陣列便位於半導體晶片之上表層之上，亦即該第三以 及第四傳導銲墊陣列相對。一第五傳導銲墊陣列定 二以及第四傳導銲墊陣列依相同於第一傳導銲墊陣列:圖 ，排列。如此，半導體晶片丨丨i與相對應之彈性基板1 2便 成為一可堆疊之半導體封裝。 藉由堆疊複數個上述結構之可堆疊之半導體封裝並加 …、，位於上層封裝之第二傳導銲墊陣列以及鄰近下層封裝 之第五傳導銲墊陣列便可以銲接方式連接。如此一 ^，二 五、發明說明（3) 具有半導f# 另士 圖所示（例如、衣炎V隹疊封裝便相互堆疊並連接，例如第2 參如吴國專利第6, 4 73, 308號）。 及生^母一個傳統堆疊式半導體封裝係由具有一美始 上之可…半導趙封裝^ =作ίί:式封裝中，因其餘之可堆叠之半導體ΐϋ I、連接鄰近可堆疊之半導體封 用， ^ 外部連接總妙裝之引腳（銲錫球或傳導銲墊）乃用以做為 運接^。然而，一堆疊封裝之可堆疊丰暮 為 導體封裝：垂是取決於每-個可堆疊之半 距離而下層封f /、疋上層封裝具有一較長金屬線 半導體封iff 金屬線距離，亦即傳統堆疊式 導體封有至外部連接端之距離因每一個可堆疊之半 V體封裝位置不同而有所差異之缺點。 【發明内容】 有，於此，本發明之目的在於提供一種堆疊 f裝、，包括單一基底以及架設於該基底上之兩半導體ί 同。’以使金屬線自外部連接端至兩半導體晶片之線長相 明之另一目的在於提供一種堆疊式半導體封裝， 以形成雨速資料傳輸。 為達成上述目的，本發明提供一種堆疊式半導體封 "包括· 一基底，具有第一以及第二相互對應之表面， 1286825
(4) 以，第二半導體晶片，每一該晶片 =定之圖案中提供複數個晶片引腳 半導體晶片被各自架設於第一以及 該架設表面隔著該基板相互對應。 述之堆疊式半導體封裝中，該基板 封裝引腳之該晶片引腳，並形成於 第一或第二表面，以將第一、第二 五、發明說明 以及第一 面以於一 以及第二 面，以使 於上 於複數個 架設區之 設妤。 於上 同之一預 於上 接至與其 定引腳與 於上 屬線，其 線部分， 引腳，以 由該共用 大體上相 腳。 具有一架設表 設置，該第一 第二基板表 具有各自對應 不同於一晶片 半導體晶片架 述之堆疊 定圖案配 述之堆疊 對應之第 對應於第 述之堆疊 中該連線 其中該連 作為對應該第一 式半導體 置。 式半導體 一、第二 一、第二 式半導體 金屬線一 同於該共 封裝中’該封裝引腳以完全相 封裝中 半導體 半導體 封裝中 一端連接至該固 線連接其他共用 第二半 端至對應之該晶 用金屬線 ，該封裝 晶片之晶 晶片之引 ’該基板 定引腳以 金屬線之 導體晶片 片引腳之 引腳包括一連 片引腳，且固 腳連接。 具有一共用金 及一分支金屬 端點至兩晶片 之晶片引腳。 金屬線長度， 一端至另一對應之該晶片引 於上述之堆疊式半導體封裝中，該分支金屬線部份包 括一介層孔’該介層孔形成於該兩晶片引腳以及連接至共 用金屬線之其他端點之間之位置，而第一、第二分支金屬 線之長度彼此相同。
2130-6196-PF(N2) ;Uofung.ptd 第10頁 !286825 〜---- 五、發明說明---*--- 、上迷之堆疊式半導體封裝中，對應於該固定引腳之 tJ p 1 接、^ 5 W腳透過基板相互面對，該分支金屬線具有一直 接至兩晶片引腳之介層孔。 底，$上述之堆疊式半導體封裝中，該基底係一多層基 線以i i ϊ r基層板及/或一能源供應板，而該共用金屬 —禮认μ刀支金屬線各自與基層板及/或能源供應板形成 傳輪線。 晶圓ϊ半導體晶片為一元素晶片（裸晶），例如dram，藉由 及製作（預製程）以形成一封裝結構，包括一基板以 晶片架設於基板上並電性連接至該基板。 下文；2 $發明之上述目的、特徵和優點能更明顯易懂， 特舉車父佳實施例，並配合所附圖式，作詳細說明如 【實施方式】 堆品=f，第u、4b圖，其係顯示根據本發明實施例之一 導體封裝10 ’其包括第—半導體晶片11、第二半 性美：” ’以及一用以架設第一、第二半導體晶片之彈 土 fl3。該彈性基板13上下表面為相互對應之第一以及 弟一表面。 ^、該/ 一半導體晶片11架設於晶片架設區（如第11圖之 1)之彈性基板13之上表面，以形成對分為兩區域之上表 面的其中之一。該第二半導體晶片12架設於彈性基板13之 下表面，隔著彈性基板13對應該第一半導體晶片12。該第
1286825 五、發明說明（6) 第一半導體基晶片1 1、j 2架設於彈性基板 用銲錫球。 土孜1 d上，例如使 該彈性基板1 3對摺以包覆該第二半導體晶 :成驟Λ得剩餘之彈性㈣^ 52)^為整個堆疊半導體封裝1〇之底部表面。於剩餘 Ϊ =成複數㈣裝引腳（鲜锡球）14以作為堆疊式半導體 封裝10之外部連接端。 千導體 第 著’請參照第5至11圖，將詳細說明每一第 一半導體基晶片11、1 2以及彈性基板1 3。 第一、第二半導體基晶片U、12之結構彼此相似。 第一半導體基晶片11、1 2皆係一記憶晶片，例如·· DRAM此外，苐一、第二半導體基晶片11、12皆可為由晶 圓製程製作（預製程）製作之元素晶片（或裸晶），或一包= 基板以及架設於基板上之該元素晶片，由封裝製程（後 製程）形成之封裝結構。 ^ 一具有封装結構之半導體晶片，例如揭露於曰本專利 第H1 1 -1 35562號以及第mu 86449號，於第5、6圖中說 明。請參照第5、6圖，該半導體晶片係藉由架設一元素晶 片20 2、302於基板2〇1、301上形成，利用金屬線（銲 塾）203、303以金屬線銲接方式（或内引腳接合、覆晶連 接’及其他類似方式）電性連接元素晶片202、302與基 板’接著將該晶片2 0 2、3 0 2以及該基板封於樹脂模型中以 保護基板上之導體圖案。 此外，該半導體晶片可為利用一封裝製程（後製程）與
I 2130-6196-PF(N2);Uofung.ptd 第12頁 1286825 五、發明說明（7) 一 % (預製程）整合之另一封裝結構，且該封裝製程於 曰^員層級之下完成。該半導體晶片指的是晶圓級之晶片 裝（ChlI) Package or chip scale package ; 〆一晶圓製程封裝。例如，此半導體晶片種類係揭露 昭=本專利第2002一26 1 1 92號以及第2003-298 0 05號。請參 :—7圖’如上述文件揭露之於晶圓製程之半導體晶片結 匕括·一保護層402、一重裝電線層403 (rewiring ay er)、一銅柱4〇4以及其他類似物於半導體基板上，並 以樹脂模型405加以密封。 請參照第8圖，每一半導體晶片u、12具有一附有複 矣個引腳（半導體錫球，亦稱為晶片引腳）2 i之表面（架設 又面），其中該引腳以一預定之圖案配置以適於電性以及 機械連接至彈性基板丨3。 每一封裝引腳係根據不同之作用（訊號）配置。例如， DR- Π之SDRAM的晶片引腳21以陣列圖案配置並設計出不 同之功能，如第9圖所示。於第9圖中，晶片引腳2丨之配置 係自上層開始。例如，於第9圖中，於第A列第i行之弓 (A1引腳）係作為vdd。 在此’說明堆疊式半導體1〇之封裝引腳14的配置。該 封裝引腳14以相同於半導體晶片u (或12)之引腳21的預^ 圖案配置。例如，形成SDRAMs之堆疊式半導體封裝之封 引腳以第10圖所示之圖案配置相互堆疊，其中該以粗體^ 表示之引腳與第9圖的不同。 請參照第9、1〇圖，該資料引腳（DQ)以及指令/位址弓丨
2130-6196-PF(N2);Uofung.ptd 第13頁
1286825 五、發明說明（8) 腳（C/Α)個別設置於上半部以及下半部。於第1〇圖中，3對 6個引腳以粗體字表示包括晶片選擇引腳（cs〇以及csi)， 計時引聊（CKEO以及CKE1),以及晶粒上端引腳（〇Dn以及 0DT1)。該些引腳係用以各自獨立操作第一、第二半導體 晶片11、12。每一引腳只連接至半導體晶片之一。例如， 若第一晶片11之CS、CKE以及ODT個別連接至封裝晶片引 CSO、CKEO以及ODTO，第二晶片12之以、CKE以及〇dt則1^固 別連接至封裝晶片引腳CSO、CKEO以及ODT0。 該些用以個別獨立操作第一、第二半導體晶片u、12 之封裝引腳被稱為選擇性引腳，而剩餘之封裝引腳被稱 一般性引腳。 … :第)0圖所，’該堆疊式半導體封裝之封裝引 包括弟二（或附加）半導體晶片之選擇性引腳， 圖所示之每一半導體晶片所配置之晶片引腳。 ，外，該平坦基板13係一多層金屬基板，例如一四屏 土反括四層‘體層，包括做為兩側表層之較高或 (前側或後侧）訊號層以及以VDD、GND板形成之中間兩声。 在此，本發明之彈性基板13為四層基板。 " 如第11圖所示，於彈性基板13上表面之 =;個=接銲墊(第一連接銲墊陣列)=以 同；第+導體晶片11(或12)之引腳21的預定圖牵 置。在剩餘之彈性基板13之上表面區域52中，—^ 列包括複數個對應該封裝引腳(封 = 部連接塾以作為堆疊式半導體封裝】。之外部連車接：= 第14頁 2130-6196-PF(N2) ;Uofung.ptd 1286825
一第一半導體晶片1 1之預定引腳配置之玻璃圖案。於彈性 基板13之下表面以及一位於架設晶片區51之後側之上的區 域5 3，设置有複數個晶片連接銲墊於玻璃圖案中以對應第 二半導體晶片12之引腳21。於彈性基板13之下表面以^對 應於外部連接銲墊陣列之區域54中，形成複數個連接至外 W知墊之介層孔（如第13圖之506)。彈性基板13更具有複 數個金屬線（訊號線之金屬圖案）以及其他介層孔（第丨4圖 之6 03、604、608、610、612 ;第15 圖之702 ;第 16 圖之 803 )以個別連接相對應之該第一、第二半導體連接銲銲墊 至外部連接墊（封裝引腳）。該金屬線形成於前、後之訊號 層0 石月參照第12A、12B圖，第一、第二半導體晶片η、i2 個別架設於彈性基板1 3之頂部以及底部。如第丨2A圖所 示’將第一、第二半導體晶片11、12之位置互換，該第一 半導體晶片11之A1引腳設置於左侧（左方或後方）時，該第 二半導體晶片1 2之A1引腳設置於右側（右方或前方）時。 第一半導體晶片11之每一引腳以及對應之第二半導體 曰曰片引腳（具有相同功能）的兩關係彼此相反，且透過彈性 基板13之金屬線連接至對應之封裝引腳14。個別作用於第 一、第二半導體晶片11、12之一對引腳中只有一引腳連接 至相對應之封褒引腳14之一。 於第一、第二半導體晶片11、1 2個別架設於彈性基板 1 3上之後，該彈性基板i 3對摺以包覆該第二半導體晶片 12 ’如此便形成如第々A、4B圖所示之堆疊式半導體封裝
2130-6196-PF(N2);Uofung.ptd 第15頁 1286825 五、發明說明（10) =㈧ί時之該封裝引腳14以相同於第—半導體晶片11之引 方向以及圖案設置。因此該堆疊式半導體封裝1〇， 曰架設第一半導體晶片丨〗於適用之基板上以作為元素 :莫(：可容納選擇性引腳之基板較佳）。這表示架設第-記憶封ί 7之基板之架設區可架設依據有兩倍儲存容量之 ，著說明有關第一、第二半導體晶片連接墊之 及外部連接墊。 第一、第二半導體晶片n、12之引腳21包括連接至封 ^弓丨腳14之選擇性引腳以及連接至固定引腳之晶片引腳。 =^至固定引腳之晶片引腳，係透過觸面板以及⑽面 ^接至固定引腳，且該連接係透過前側及/或後侧之訊 ，層。晶片引腳透過訊號層連接至固定引腳，該訊號層之 引腳係以每對引腳互相面對並透過基板上形成之介層孔之 方式直接連接。為使上述之兩晶片間連接，該銲 方式連接。 請參照第1 3圖，於第一連接銲墊陣列中，每一連接至 ，擇性引腳之晶片引腳銲墊5〇1，透過金屬線5〇2(訊號線） 連接至對應於選擇性引腳之外部連接銲墊5〇3，其中該金 屬線包括彈性基板1 3之前側訊號層。另外，第二連接銲墊 陣列中，每一連接至選擇性引腳之晶片引腳銲墊5〇4，透 過金屬線50 5 (訊號線）連接至彈性基板13下表面區域“之 介層孔506，其中該金屬線包括彈性基板13之後侧訊號 層。該介層孔50 6連接至外部連接銲墊5〇7，而該外部連接 2130-6196-PF(N2) ;Uofung.ptd 第16頁 1286825 五、發明說明（Π) "----- 鲜塾507則連接至對應之選擇性引腳。在此，每一金屬線 包括於後侧之訊號層其透過連接該區域54之介層孔以連接 至對應的外部連接銲墊。 請參照第14圖，於第一連接銲墊陣列該晶片引腳之銲 (VDD，VDDQ) 6 02 (僅顯示其一）透過該VDD基板6〇1之固定 引腳連接，而該VDD基板601透過介層孔603連接，而該介 層孔603向基底13之底部表面。該VDD基板6〇1透過介層孔 604連接至對應之外部連接墊Mg。相同的，於第一連接銲 墊陣列中，該晶片引腳之銲墊6〇7(僅顯示一個為代表）透 過該GND基板606之固定引腳連接，而該GND基板6〇6透過介 層孔608^連接，而該介層孔6〇8向基底13之底部表面。另 外’於第二連接銲墊陣列該晶片引腳之銲墊6 〇 g (僅顯示其 「）透過該VDD基板601之固定引腳連接，而該VDD基板6(H 透過介層孔61 0連接，而該介層孔6丨〇向基底丨3之底部表 面。相同的’於第二連接銲墊陣列中，該晶片引腳之銲墊 6〇ljVSS，VSSQ)(僅顯示一個為代表）透過該GNI)基板6〇6之 固定引腳連接，而該GND基板60 6透過介層孔612連接，而 該介層孔612向基底13之底部表面。 〇 在此’該與電源供應有關之銲墊（VDD, VDDQ)連接至 單一 VDD基板。VDD以及VDDQ可藉由分開同一層中之VDD基 板來個別打線。VDD、VDDQ亦可打線於前側訊號層及/或後 侧訊號層之空的間隙中。此外，形成_VDD、VDDQ銲墊之 附加基板。該連接至GND平面之銲墊（VSS，VSSQ)可以相同 方式進行打線。
五、發明說明（12) 請參照第1 5圖，於第一連接墊陣列中，每一透過前側 訊號層及/或後側訊號層連接至固定引腳晶片之引腳之鲜 塾701 (除該銲藝直接透過介層孔連接至底部表面之銲墊者 之外）係透過金屬線（分支金屬線）7〇3連接至介層孔7〇2而 形成於對應於第一、第二訊號銲墊之中間點附近，其中該 金屬線703包括前側訊號層。該第二連接墊陣列之對應鲜/ 墊704透過金屬線（分支金屬線）7〇5連接至相同之介層~孔 70 2其中該金屬線7 〇 5包括後侧訊號層。而透過訊號層金 屬線連接至每一固定引腳之一對銲墊7〇1、7〇4係透過介層 孔702彼此連接，而形成於中間點附近。該連接至該對銲 墊701、704之介層孔702會進一步透過前側及/或後側之訊 號層的金屬線70 6或70 7連接至外部連接墊，以使其對應於 固定引腳。該分支金屬線703、705以及介層孔7〇2彼此連、 接並整個視為分支金屬線部份。根據上述結構，該分支金 屬線連接至彼此對應之連接墊（晶片引腳）的長度係大體彼 此相同的（在此範圍下不會產生實施上的問題）。 請參照第1 6圖，於第一連接銲墊陣列中，其他留下之 透過别侧及/或後側之訊號層連接至固定引腳之連接銲墊 801各透過介層孔803連接至該第二連接銲墊陣列後側之連 接墊802。此乃因半導體晶片11、1 2之部份引腳功能可以 凋換而不致產生任何問題。例如，每一半導體晶片11、1 2 f引腳以第9圖所示之功能設置，其中第一、第二半導體 ，片11、12之一的DQ〇、DQi、DQ2以及DQ3引腳對應於另一 曰曰片的DQ1、DQ0、DQ3以及DQ2。在此，每一半導體晶片之 1286825 五、發明說明（13) DQ〇、DQ1、DQ2以及DQ3引腳可互換其功能，以便使該些相 互對應之引腳連接至相同之固定引腳且不產生問題。第一 ^接塾陣列之每一連接墊8〇1可直接透過介層孔8〇3連接至 第一連接墊陣列之連接墊8〇2，其中該第二連接墊陣列設 置於後侧底層。該一對透過介層孔8〇3彼此連接之連接墊 801、802之一則透過前侧及/或後侧之訊號層的金屬線8〇4 或8 0 5連接至對應之固定引腳。於此例中，當金屬線⑽4或 805共同連接至分支金屬線部分時，該介層孔8形成一 支金屬線部分。 、該可直接透過介層孔相連接之對應連接墊可因在設計 Γ i ί產上之方便以不同方法相互連接。特別《，兩彼此 ==鮮墊可透過介層孔連接，上述之方式形成於 *、、墊之中間點附近。另外，前侧及/或後侧訊號層之 :ΐ非iff接，❿係透過介層孔利用金屬線形成於不同 ^置。右銲墊透過介層孔直接連接時，此介層孔直 =墊上。亦可視為該介層孔形成於料料而直接連接 接？ ’將說明第一、第二連接銲墊陣列 接墊，連接，特別是有關晶片連接至固定引腳之連：：連 凊參照第1 7A圖，其係顯示彈性基板1 3之部分前伽 ，層（對^於第9圖之半導體晶片的金屬線Α — W。對應於5 第17:之1^基中板13之部分後侧訊號層則顯示於Ι7βί。於 弟1 7Α、1 7Β圖中所顯示之彈性基板丨3係一上視 ' 請參照第17Α圖，該第一半導體晶片之…引腳的連接 第19頁 2130-6196-PF(N2) ;Uofung.ptd 1286825 發明說明（14) 墊’透過前側金屬線71(分支金屬線）連接至介層孔72 外，如第17B圖所示，該第二半導體晶片之人8引曰腳的連接 墊，透過後侧金屬線73(分支金屬線）連接至介層孔72。 此，該介層孔72形成於兩半導體晶片之“引腳二連接墊 中間點附近，以便使金屬線71、73之長度彼此相同。形 長度彼此相同之金屬線71、73以作為傳輸線（為使|電阻 相當）。該介層孔72更透過後侧訊號層之金屬線（共用金 線）74連接至形成於該區域54之底部表面的介層孔75並 接至該A8封裝引腳的鲜墊。 、 與A8引腳的連接墊相同，該第一、第二半導體晶片之 B3引腳的連接墊透過一介層孔76相互連接，其中該介層孔 76形成於兩半導體晶片之連接墊的中間點附近。與人8引腳 的介層孔72不同的是，該介層孔76透過前侧訊號^之訊號 線77連接至該B3封裝引腳的銲墊。 與A8引腳的連接墊相同，該對應於第一以及二半導體 晶片之B7引腳之連接墊連接至B7封裝弓丨腳後侧之介層孔 78 ° 睛參照第17A圖，該第一半導體晶片之引腳C2、D3的 連接銲墊，透過訊號層前側之金屬線個別連接至外部封裝 引腳C8 Μ的連接墊。在此未圖解說明該引腳的連 $墊係透過介層孔個別直接連接該第二半導體晶片後 C8、B7引腳。 同樣的，如第17B圖所示，該第二半導體晶片之引腳 、D3的連接銲塾，透過訊號層後側之金屬線個別連接至 第20頁 2130-6196-PF(N2) ;Uofung.ptd 1286825 、發明說明（15) 連接封裝引腳C2、D3的介# ?丨。户+土㈤& 、Μ @ # | & π ^ ^層孔在此未圖解說明該引腳 侧之C8、Β7引Ϊ 層孔個別連接該第一半導體晶片後 連接至VDD基板之薛塾㈠列如A1引腳之連接 由介層孔連接至VDD基板，肤古々介虛m ^ 置接 之鲜塾。 孜此方式亦應用於連接至GND基板 / 2 Γ至2^擇性引腳之晶片％ ’之連接塾係透過前側及 /或後側之訊號層的金屬線，以相同於第一、第二半導體 晶片之引腳C2、D3的連接銲墊方式連接。 兔@ ΐ著’ &明於彈性基板上形成金屬線。該彈性基板1 3 為八有—基底金屬、線及/或一能量供應金屬線之複數層基 反。大部分（甚或全部）訊號金屬線圖案與基板及/或能量 供應板一起構成傳輸線（或金屬線）。請參照第18 —21圖， 其係顯示藉由每-金屬、線圖案形成之不同的傳輸線結構。 如第18A、18B圖所示，該傳輸線可為微帶線，包括： 一訊號金屬線圖案81，以及一鄰接於該訊號金屬線圖案81 之基板及/或能量供應板（平面金屬線）82。接著，請參照 第19A、19B圖所示，該傳輸線可為一帶線，包括：一訊號 金屬線圖案81，以及一對鄰接於該訊號金屬線圖案81之對 應侧基板及/或能量供應板（平面金屬線）82a及/或82b。如 第20A、20B圖所示，該傳輸線可為平行線包括：一訊號金 屬線圖案81，以及一基板及/或能量供應金屬線（平面金屬 線）83，該基板及/或能量供應金屬線（平面金屬線）83沿著 與訊號金屬線圖案之一側（或對應侧）平行延伸。上述之傳 2130-6196-PF(N2) ;Uofung.ptd 第21頁 1286825 五、發明說明（16) 輸線結構適當選擇並結合以形成訊號金屬圖案。 該基板及/或能量供應板（平面金屬線）82、82a以及 8 2b形成寬度不小於訊號金屬圖案之微帶線或帶線。 請參照第21A圖，該基板及/或能量供應板（平面金屬 線）91、9 2形成之傳輸線包括複數個基板部分及/或電源供 應金屬板部分（平板）。 〃 請參照第21B圖，該基板及/或能量供應板（平面金屬 線）82、82a以及82b形成之傳輸線可由介層孔95及/或另一 金屬線9 6部分分隔。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定^發明，任何熟習此項技藝者，在不脫離本發明之精 2和範圍内，§可作更動與潤飾，因此本發明之保護範圍 虽視後附之申請專利範圍所界定者為準。 ^ =二士述之說明中該封裝引腳與第一半導體晶片引 mi 準。請參照第22圖，該封裝引腳可能會位 八用金屬線之長度。請參照第23Α以及23Β圖，該封 ㊁引腳之排列亦可與第一半導體晶片引腳之排列相當不 第22頁 2130-6196-PF(N2) ;Uofung.ptd 1286825 圖式簡單說明 第1圖係縿示出傳統堆疊半慕 ^ ® ^ ^ , 且干♦體封裝剖面圖； 第2圖係、會不出另一傳統堆疊 第3圖係I會示出用於第2圖 /體封裝』面圖； 晶片以及一彈性基板分解圖 “體封裝之半導體 第4 A、4B圖係各自繪示出根摅 — 導體封裝之透視圖以及上視圖。 卷月貫施例之堆疊半 裝結構之半導體晶片剖 統封裝結構之半導體晶片 傳統封裝結構之半導體晶 第8圖係繪示出第4A、4B圖中田认认田， 半導體晶片透視圖； 时用於堆豐半導體封裝之 第9圖係繪示出第8圖中之半導 置圖_係繪一配 ㈣…用於…導艘封裝 第5圖係繪示出具有一傳統封 面圖； 第6圖係繚示出具有另一傳 剖面圖； 第7圖係緣示出具有再另一 片剖面圖； 之 第12A、12B圖係各自緣示屮楚 嵌於溫地Λ 4c; a々、凑、目囬 4A、4B圖半導體晶片鑲 甘入於彈性基板别之透視圖以及垂直剖面圖· 腳 第1 3圖係繪示出有關第！ ！圖之其 連接剖面圖； 園之w生基板上的選擇引 第1 4圖係繪示出有關第11圖之 口 <弹性基板中之VDD平面
1286825 圖式簡單說明 連接剖面圖； 第1 5圖係繪示出有關第i】 接剖面圖； "弟11圖之每性基板上固定引腳連 第16圖係㈣出料間藉由第 層孔直接相互連接剖面圖； 心评l'生基扳中I )丨 第17A、17B圖係繪示出彈性基板之 -晶片連接銲整陣列與外部連接短執-廷接刀各总: 第二晶片連接銲墊陣列以及連接至列間之連接，以 層孔間之連接。 及連接至外部連接銲墊陣列之介 弟1 8 Δ、1 8 Β圖係各自綠示出傲册 視圖以及縱向圖； 出u為嘁▼線之傳輸線的透 弟1 9 A、1 9 B係各自綠示出另一册 透視圖以及縱向圖； ：、、、ρ τ線之傳輸線的 第20A、20B圖係各自繪示出再一 的透視圖以及縱向圖； 為试f線之傳輸線 及/或能量供應板部 第21 A圖係繪示出包括複數個基板 分之能量供應板透視圖； 第21 B圖係繪示出另一包括複數個 板部分之能量供應板透視圖； 板及/或犯1供應 第2 2圖係緣示出根據本發明 剖面圖； “之改良式堆疊半導體封裝 半導 第23A、23B圖係各自繪示出根據本 體封裝之剖面圖以及透視圖。 月之改良式堆疊
2130-6196-PF(N2) ;Uofung.ptd 第24頁 1286825 圖式簡單說明 【符號說明】 1 0〜堆疊式半導體封裝； 1 1〜第一半導體晶片 12〜第二半導體晶片； 1 3〜彈性基板； 14〜封裝引腳； 21〜晶片引腳； 51〜晶片架設區， 52〜上表面區域； 53〜下表面區域； 54〜下表面區域； 7 1〜前側金屬線； 7 2〜介層孔； 7 3〜後側金屬線； 7 4〜共用金屬線， 7 5〜介層孔； 7 6〜介層孔； 7 7〜訊號線； 7 8〜介層孔； 8 1〜訊號金屬線圖案； 9 5〜介層孔； 9 6〜金屬線； 1 0 1〜凹處； 102〜基板； 10 3〜導線圖案； 104〜半導體晶片； 1 0 5〜金屬線； 106〜末端銲墊； 1 0 7〜焊錫球； 111〜半導體晶片； 1 1 2〜彈性基板； 1 2 2〜第一傳導銲墊陣列； 1 2 1〜接點； 2 0 1〜基板； 2 0 2〜元素晶片； 203〜銲墊； 3 0 1〜基板； 3 0 2〜元素晶； 3 0 3〜銲墊； 4 0 2〜保護層； 4 0 3〜重裝電線層； 404〜銅柱； 4 0 5〜樹脂模型； 5 0 2〜金屬線； 5 0 3〜外部連接銲墊； 5 0 5〜金屬線； 5 0 6〜介層孔；
2130-6196-PF(N2);Uofung.ptd 第25頁 1286825 圖式簡單說明 5 0 7〜外部連接銲墊； 6 0 2〜焊塾； 6 0 4〜介層孔； 6 0 6〜GND基板； 6 0 8〜介層孔； 6 1 0〜介層孔； 6 1 2〜介層孔； 7 0 2〜介層孔； 704〜銲墊； 801〜連接墊； 8 0 3〜介層孔； 82〜基板及/或能量供應板 91〜基板及/或能量供應板 9 2〜基板及/或能量供應板 7 0 6〜前侧訊號層之金屬線 7 0 7〜後側訊號層之金屬線； 82a〜基板及/或能量供應板 82b〜基板及/或能量供應板 83〜基板及/或能量供應金屬 501〜選擇性引腳之晶片引腳 504〜選擇性引腳之晶片引腳 6(Π〜VDD基板； 6 0 3〜介層孔； 6 0 5〜外部連接墊 6 0 7〜銲墊； 6 0 9〜銲墊； 61 1〜銲墊； 701〜銲墊； 70 3〜分支金屬線 70 5〜分支金屬線 80 2〜連接墊； 8 0 4〜金屬線； 8 0 5〜金屬線； 線； 銲墊 鲜塾
2130-6196-PF(N2);Uofung.ptd 第26頁

Claims (1)

1286825 銮號 9310g058 修正车 六、申請專利範圍 1· 一種堆疊式半導體封裝，包括一基底，具有第一以 及第二相互對應之表面’以及苐一以及第二半導體晶片， 每一該晶片具有一架没表面以於一預定之圖案中提供複數 個晶片引腳設置，該第一以及第二半導體晶片被各自架設 於第一以及第二之基板表面，以使該架設表面隔著***其 間之該基板相互對應，並且該第一和第二半導體晶片具有 相同之引腳配置；其中： 該基板具有各自對應於該晶片引腳之複數個封裝引 腳，並形成於該第一或第二表面上不同於一架設第_、第 二半導體晶片之晶片架設區的區域； 該封裝引腳包括連接至第一、第二半導體晶片之一者的對 應晶片引腳之述擇性引腳，以及連接至第一、第二半導體 晶片之對應晶片引腳之一般性引腳； 该基板具有一共用金屬線，其一端點連接至該一般性引 腳’以及一分支金屬線部分，其連接該共用金屬線之另一 端點至作為該第一、第二半導體晶片之對應晶片引腳的兩 晶片引腳； 由該共用金屬線之該端點至該對應晶片引腳中之一者 的金屬線長度，大體上相同於該共用金屬線之該端點至另 一該對應晶片引腳的金屬線長度。 2·如申請專利範圍第1項所述之堆疊式半導體封裝， 其中： 該分支金屬線部份包括一介層孔，該介層孔形成於該 兩晶片引腳以及連接至共用金屬線之另一端點之間之位
2130-6196-PF3(N2).ptc 第27頁 案號931〇^ 1286825
六、申請專利範圍 置，而第一、I 一 \ 〜为支金屬線之長度彼此相同。 3·如申靖專利範圍第丨項所 其中對應於該一般持2丨『 > 斗 声且叭千V體封哀， 對，該分支金屬線部片查引腳透過基板相互面 介層孔。 祁刀具有一直接連接至兩一般性引腳之 4·如申請專利範圍第丨項所述之堆疊式半導體封裝， 其中該基底係一多層基底，其具有一基層板及/或一能源 供應板，而該共用金屬線以及該分支金屬線部份各自與基 層板及/或能源供應板形成一傳輸線。 5 ·如申請專利範圍第4項所述之堆疊式半導體封裝， 其中該傳輸線包括任一微帶線（microstrip line)、帶線 (strip line)以及一平行埠。 6 ·如申請專利範圍第5項所述之堆疊式半導體封裝， 其中該基層板及/或電源供應板包括由複數個基層板及/或 電源供應板形成之部分或由一介層孔或另一金屬線部分隔 離之部分。
2130-6196-PF3(N2) 第28頁
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