CN1531087A - 层叠型半导体封装件 - Google Patents

层叠型半导体封装件 Download PDF

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Publication number
CN1531087A
CN1531087A CNA2004100076721A CN200410007672A CN1531087A CN 1531087 A CN1531087 A CN 1531087A CN A2004100076721 A CNA2004100076721 A CN A2004100076721A CN 200410007672 A CN200410007672 A CN 200410007672A CN 1531087 A CN1531087 A CN 1531087A
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China
Prior art keywords
chip
pins
pin
wiring
semiconductor
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CNA2004100076721A
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English (en)
Inventor
菊地涉
夫
管野利夫
伊佐聪
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Micron Memory Japan Ltd
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Elpida Memory Inc
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Publication of CN1531087A publication Critical patent/CN1531087A/zh
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Abstract

本发明公开了一种层叠型半导体封装件。其中，分别具有安装面的两个半导体芯片(11)、(12)相互对向地安装到基板(13)的表面和底面上，从而使半导体芯片(11)、(12)的安装面夹着基板(13)，所述安装面上按预定的排列设有多个芯片引脚。在基板的非芯片安装面上，形成与芯片引脚相同排列的封装件引脚。用相同长度的分支布线把两个半导体芯片的相互对应的芯片引脚连接到在它们的中间位置形成的通路上。用共用布线把各通路与连接于通路的芯片引脚所对应的封装件引脚(14)连接起来。这样，在一个基板上就可以安装两个半导体芯片，就能够使从外部连接端子到各半导体芯片的布线长度实质上互相相等。

Description

层叠型半导体封装件
技术领域
本发明涉及层叠型半导体封装件，特别涉及能够进行高速数据传输的层叠型DRAM封装件。
背景技术
如图21所示，现有的层叠型半导体封装件具有：在其上面中央部形成模穴101的基板102；从基板102的上面至下面形成的布线图103；配设在基板102的模穴101中的半导体芯片104；把半导体芯片104连接到布线图103上的焊丝105；在基板102的上面侧与布线图103连接的多个端子焊盘(pad)106；以及在基板102的下面侧与布线图103连接固定的多个焊料球107。
此处，使多个端子焊盘106和多个焊料球107以相同的排列而形成。即，将所预备的多个层叠型封装件相互重叠时，使位于上面的封装件的焊料球107和位于下面的封装件的端子焊盘106一一对应。这样，如果将多个层叠型封装件重叠并且经过回流工序，就能够得到多个半导体芯片相互层叠且连接的层叠封装件(例如，参照特开平11-220088号公报)。
还有，如图22所示，另一种现有层叠型半导体封装件具有：半导体芯片111和包着芯片111的挠性基板112。
如图23所示，在图22所示的层叠型半导体封装件所用的半导体芯片111的下面，排列形成多个触点121。还有，在挠性基板112的上面，形成第一导电焊盘群122，该第一导电焊盘群122的排列对应于在半导体芯片111的下面所形成的多个触点121的排列(反转排列)。再有，在挠性基板112的下面，以与第一导电焊盘群122重合的方式(即，以与触点121相同的排列)形成第二导电焊盘群，同时，在其两侧形成第三及第四导电焊盘群。把第三及第四导电焊盘群分别配置成第二导电焊盘群的一半进行反转后的排列，通过布线图与对应的第二导电焊盘群的一半连接。
把半导体芯片111安装到挠性基板112上，就使半导体芯片111的触点121连接到对应的第一导电焊盘122上，同时，通过挠性基板112，使半导体芯片111的触点121也连接到位于挠性基板112底面的第二导电焊盘群上。结果，使半导体芯片111的各触点121连接到第三及第四导电焊盘群中的各焊盘上。如果把挠性基板112卷曲，使其包住半导体芯片111，第三及第四导电焊盘群就处在了半导体芯片的上面侧。由第三及第四导电焊盘群形成的第五导电焊盘群的排列与第一导电焊盘群的排列相同。
如果把上述构成的多个半导体封装件相互重合，并对其进行加热，位于上边的封装件的第二导电焊盘群和位于下边的封装件的第五导电焊盘群就由软焊料相连接，从而得到图22所示的多个半导体芯片相互层叠并连接的层叠封装件(例如，参照美国专利第6473308号公报)。
现有的层叠型半导体封装件是在一个基板上安装一个芯片而构成的，使其多个重合就构成了层叠封装件。在这种层叠封装件中，把位于最下边的层叠型半导体封装件的引脚(焊料球或导电焊盘)用作外部连接端子(层叠封装件引脚)，其它的层叠型半导体封装件的引脚则用来与下面的层叠型半导体封装件连接。此外，构成层叠封装件的各层叠型半导体封装件的引脚与外部连接端子之间的布线距离取决于各层叠型半导体封装件的上下位置，位置越靠上越长。也就是说，现有的层叠型半导体封装件存在以下问题点：层叠后，到外部连接端子的距离随其层叠位置而变。
发明内容
本发明的目的是提供一种使两个半导体芯片安装于一个基板上且能够使从外部连接端子到各半导体芯片的布线长度实质上相等的层叠型半导体封装件。
还有，本发明的目的是提供一种能够进行高速数据传输的层叠型半导体封装件。
根据本发明就可以得到具有以下特征的层叠型半导体封装件：分别具有安装面的两个半导体芯片相互对向地安装到基板的表面和底面上，从而使半导体芯片的安装面夹着基板，所述安装面上按预定的排列设有多个芯片引脚。
在该层叠型半导体封装件中，上述基板在其表面上或底面上的区域，在与用于安装上述两个半导体芯片的区域不同的区域，具有与上述多个芯片引脚分别对应的多个封装件引脚。
上述多个封装件引脚可以按照与上述预定的排列相同的排列而设置。
上述多个封装件引脚包括：选择引脚，只与所述第一及第二半导体芯片之一上的对应芯片引脚连接；以及普通引脚，与所述第一及第二半导体芯片的每一半导体芯片上的对应芯片引脚连接。
上述基板具有：共用布线，其一端连接于上述普通引脚；以及分支布线部，用于把共用布线的另一端连接到上述两个半导体芯片各自对应的芯片引脚上，并且使从上述共用布线的另一端至上述对应的芯片引脚的布线距离实质上相等。
为使从上述共用布线的另一端至上述对应的芯片引脚的布线距离实质上互相相等，上述分支布线部具有：通路(via)，形成在上述对应的芯片引脚的中间位置近旁，且连接于上述共用布线的另一端；以及第一及第二分支布线，它们把通路与上述对应的芯片引脚连接起来，它们的长度实质上相等。
上述普通引脚所对应的两个芯片引脚，在隔着上述基板相互面对面的情况下，上述分支布线部具有将上述两个芯片引脚进行直接连接的通路。
上述基板是具有接地面和/或电源面的多层基板，其中，上述布线图构成传输线路。
此处，作为上述半导体芯片，可以是DRAM等在晶片工序(前工序)制造的单体芯片(裸管芯)，也可以是把上述单体芯片安装在基板上、使上述芯片和上述基板进行电连接后的封装件构造。
根据本发明，使具有相同引脚配置的两个半导体芯片夹着基板、以相对的方向安装于该基板的表、底面上，从而使得从各封装件引脚到各半导体芯片的对应芯片引脚的布线长度实质上相等，能够进行数据的高速传输。
附图说明
图1是表示本发明的一种实施方式的层叠型半导体封装件的简略构成的(a)斜视图及(b)正视图。
图2是表示一例现有封装件构造的半导体芯片的简略剖面构成图。
图3是表示另一例现有封装件构造的半导体芯片的简略剖面构成图。
图4是表示又一例现有封装件构造的半导体芯片的简略剖面构成图。
图5是表示图1的层叠型半导体封装件所使用的半导体芯片的简略构成的斜视图。
图6是用于对图5的半导体芯片的引脚的功用进行说明的配置图。
图7是用于对图1的层叠型半导体封装件的封装件引脚的功用进行说明的配置图。
图8是表示图1的层叠型半导体封装件所使用的挠性基板的简略构成的斜视图。
图9是表示半导体芯片安装于挠性基板之前的简略图，(a)为斜视图，(b)为纵向剖面图。
图10是用于对与图8的挠性基板中的选择引脚有关的连接进行说明的部分剖面图。
图11是用于对与图8的挠性基板中的VDD面有关的连接进行说明的部分剖面图。
图12是用于对与图8的挠性基板中的通常的普通引脚有关的连接进行说明的部分剖面图。
图13是用于对与图8的挠性基板中的用通路直接连接的焊盘的连接进行说明的部分剖面图。
图14是表示图8的挠性基板的布线一部分的图，(a)是表示第一芯片连接焊盘群与外部连接焊盘群的连接关系的图，(b)是表示第二芯片连接焊盘群与外部连接焊盘群所连接的通路的连接关系的图。
图15是用于对作为微带(micro-strip)线路而构成的传输线路进行说明的图，(a)为斜视图，(b)为纵向剖面图。
图16是用于对作为带状线路而构成的传输线路进行说明的图，(a)为斜视图，(b)为纵向剖面图。
图17是用于对作为平行线路而构成的传输线路进行说明的图，(a)为斜视图，(b)为纵向剖面图。
图18是用于对构成传输线路的接地或电源板的其它方式进行说明的图，(a)表示接地或电源板由多个部分构成的例子，(b)表示接地或电源板被通路或其它布线部分地分断的例子。
图19是表示本发明的层叠型半导体封装件的变形例的简略剖面图。
图20是表示本发明的层叠型半导体封装件的另一变形例的(a)简略剖面图、(b)斜视图。
图21是表示一例现有层叠型半导体封装件的简略构成的剖面图。
图22是表示另一例现有层叠型半导体封装件的简略构成的斜视图。
图23是对图18的层叠型半导体封装件所用的半导体芯片和挠性基板的构成进行说明的分解斜视图。
具体实施方式
下面，参照附图对本发明的实施方式进行详细说明。
在图1(a)及(b)中，示出了本发明的一种实施方式的层叠型半导体封装件的简略构成图。所示的层叠型半导体封装件10具有：第一半导体芯片11；第二半导体芯片12；以及用于安装这些半导体芯片11、12的挠性基板13。
把挠性基板13的上面分为两部分，第一半导体芯片11安装在其中的一部分区域(芯片安装区域)上。还有，第二半导体芯片12安装在挠性基板13的下面，与第一半导体芯片11相对，中间夹着挠性基板13。可以用例如软焊料球将第一及第二半导体芯片11、12安装到挠性基板13上。
还有，把挠性基板13折两个折，包住第二半导体芯片12。折叠之后的结果，挠性基板13的上面就成为层叠型半导体封装件10的下面，在该成为下面的区域上形成了成为该层叠型半导体封装件10的外部连接端子的封装件引脚(软焊料球)14。
下面，参照图2至图8，对半导体芯片11、12及挠性基板13的各构成进行详细说明。
第一半导体芯片11和第二半导体芯片12具有相同的构成，例如DRAM等存储器芯片。这些半导体芯片11、12可以是在晶片工序(前工序)制造的单体芯片(裸管芯)，也可以是经过封装工序(后工序)后把单体芯片安装在基板上的封装结构的芯片。
作为封装结构的半导体芯片，例如，特开平11-135562号公报及特开平11-186449号公报中都有记载。如图2或图3所示，这些公报中所记载的半导体芯片的构成如下：单体芯片202或302安装在基板201或301上，用焊丝205或305(或内部引线连接，或者倒装焊接)将单体芯片202或302的布线(焊盘)203或303与基板201或301上的布线204或304进行连接，为保护在基板201或301上形成的导体图形206或306，用树脂207或307进行密封。
作为其它的封装结构的半导体芯片，可以使封装工序(后工序)与晶片工序(前工序)变成连续的一体化工序，以在晶片状态下完成封装工序的方式制造，称为晶片级CSP或是称为晶片工序封装件的芯片。这种构造的半导体芯片，例如，在特开2002-261192号公报及特开2003-298005号公报中都有记载。前者所记载的半导体芯片的构成，如图4所示，在晶片工序完成后的半导体基板401上形成保护膜402、再布线层403、以及铜柱404之后，用树脂405进行密封。
在各半导体芯片11、12的一面(安装面)上，如图5所示，与挠性基板13进行电的、机械的连接的多个引脚(也称半导体球，芯片引脚)21按预定的排列而形成。
多个芯片引脚21的各个芯片引脚21分别对应各种特定的功用(信号)。例如，在DDR-II用的SDRAM的情况下，把芯片引脚21排列成矩阵状，各芯片引脚21所担当的功用如图6所示。另外，图6是从上面侧观看芯片引脚的配置的图。例如，在图6中，A行1列的引脚(A1引脚)用于ADD。
此处，对层叠型半导体封装件10的封装件引脚14的配置进行说明。封装件引脚14的配置与层叠的半导体芯片11(或12)的引脚配置大致相同。例如，把上述SDRAM进行层叠后的层叠型半导体封装件的封装件引脚的配置如图7所示。在图7中，用粗体字来表示与图6不同的引脚。
在图6及图7中，如果粗略进行分类，大致上半部分为数据(DQ)系引脚，下半部分为命令地址(C/A)系引脚。还有，在图7中用粗体字表示的3组6个引脚，即，芯片选择引脚(CS 0及CS 1)、时钟引脚(CKE 0及CKE 1)、以及芯片终端(オンダイタ一ミネ一シヨン)引脚(ODT 0及ODT 1)，用于使第一半导体芯片11和第二半导体芯片12相互独立地工作，每个引脚仅连接于其中的一个半导体芯片。例如，如果把第一半导体芯片11的CS、CKE、以及ODT分别连接于封装件引脚的CS 0、CKE 0以及ODT 0，第二半导体芯片12的CS、CKE、以及ODT就分别连接于CS1、CKE1以及ODT1。
这样，使第一半导体芯片11和第二半导体芯片12相互独立地工作的封装件引脚称为选择引脚，其它的封装件引脚称为普通引脚。
图7的层叠型半导体封装件的引脚排列是在图6的半导体芯片单体用的芯片引脚配置上追加了第二半导体芯片用的选择引脚之后的排列。
另一方面，挠性基板13是多层布线基板，例如，四层基板，具有作为表层的上下2层(或表层及底层)的信号层和作为内层的VDD面及GND面的2层。在以下的说明中，挠性基板13为四层基板。
如图8所示，在挠性基板13的上面的芯片安装区域51上，与第一半导体芯片11的各引脚21对应，形成相同排列的多个芯片连接焊盘(第一连接焊盘群)。还有，在挠性基板13的上面的其他区域52上，形成外部连接用焊盘群，该外部连接用焊盘群与成为该层叠型半导体封装件10的外部连接端子的多个封装件引脚(封装件引脚群)14对应，并且相对于第一半导体芯片11的引脚排列呈镜像排列。再有，在挠性基板13的下面，即位于芯片安装区域51的底面的区域53上，与第二半导体芯片12的各引脚对应，形成排列(镜像排列)的多个芯片连接焊盘(第二连接焊盘群)(未示出)。再有，在挠性基板13的下面，即与外部连接用焊盘群对应的区域54上，形成与外部连接用焊盘相连接的通路(例如，图10中的506)。挠性基板13还具有用于把第一连接焊盘群及第二连接焊盘群的连接焊盘的各个焊盘与对应的外部连接用焊盘(封装件引脚)进行连接的布线及通路(例如，图11中的603、604、608、610、612，图12中的702，图13中的803)。另外，在表层侧及底层侧信号层内形成布线。
如图9(a)及(b)所示，第一半导体芯片及第二半导体芯片11、12分别安装于挠性基板13的芯片安装区域的上、下面。此时，从图9(a)可以看出，第一半导体芯片11及第二半导体芯片12成为相互反转的状态。例如，在这种状态下，第一半导体芯片11的A1引脚位于左侧(左内)，而第二半导体芯片12的A1引脚位于右侧(右内)。
挠性基板13的布线把存在上述的反转关系的第一半导体芯片11的各引脚和与其对应的(相同功用的)第二半导体芯片12的引脚一同与对应的封装件引脚14进行连接。但是，对于所述的、用于使各半导体芯片11、12进行独立工作的芯片引脚，任何一个半导体芯片只与对应的封装件引脚14进行连接。
把第一及第二半导体芯片11、12安装于挠性基板13之后，把挠性基板13折起来(折两次)，使其包住第二半导体芯片12，就得到如图1所示的层叠型半导体封装件。此时，封装件引脚14与第一半导体芯片11的引脚在相同方向为相同排列。于是，该层叠型半导体封装件10就能够在这种状态下安装到用于安装第一半导体芯片11单体的基板(此处指与选择引脚对应的基板)上。这意味着，在具有用于安装第一半导体芯片11的必要的实装面积的基板上，能够安装2倍存储容量的存储器封装件。
下面，说明使第一及第二半导体芯片连接的连接焊盘与外部连接焊盘之间的连接关系。
在第一及第二半导体芯片的引脚21中，有与封装件引脚14中的选择引脚连接的芯片引脚和与封装件引脚中的普通引脚连接的芯片引脚。还有，在与普通引脚连接的芯片引脚中，有通过VDD面或GND面连接于普通引脚的芯片引脚和通过表层侧和/或底层侧的信号层连接于普通引脚的芯片引脚。再有，在通过信号层连接于普通引脚的芯片引脚中，有通过在基板上形成的通路使相对的一对引脚直接连接的芯片引脚。为实现这些芯片间的连接，各焊盘间以下述方式进行连接。
如图10所示，在第一连接焊盘群中，与选择引脚连接的芯片引脚用的焊盘501通过作为挠性基板13的表层侧信号层的一部分的布线(信号线)502连接到对应的选择用的外部连接焊盘503上。另一方面，在第二连接焊盘群中，与选择引脚连接的芯片引脚用焊盘504通过作为挠性基板13的底层侧信号层的一部分的布线(信号线)505连接到在挠性基板13的下面的区域54内形成的通路上，即对应的选择引脚用的外部连接焊盘505所连接的通路506上。此处的构造为，底层侧布线通过区域54的通路连接到对应的外部连接焊盘上。
还有，如图11所示，在第一连接焊盘群中，通过VDD面601与普通引脚连接的芯片引脚用的焊盘(VDD、VDDQ)602利用从该处向着基板底面侧所形成的通路603连接到VDD面601上。再有，VDD面601利用通路604连接到对应的外部连接焊盘605上。同样，在第一连接焊盘群中，通过GND面606而与普通引脚连接的芯片引脚用的焊盘607利用从该处向着基板下面侧所形成的通路608连接到GND面606上。另一方面，在第二连接焊盘群中，通过VDD面603而与普通引脚连接的芯片引脚用的焊盘609利用从该处向着基板上面侧所形成的通路610连接到VDD面601上。同样，在第二连接焊盘群中，通过GND面606而与普通引脚连接的芯片引脚用的焊盘(VSS、VSSQ)611利用从该处向着基板上面侧所形成的通路612连接到GND面606上。
此处，与电源有关的焊盘(VDD、VDDQ)连接到一个VDD面上，不过，也可以在同一层内把VDD和VDDQ进行分割，做成别的布线，还可以在表层侧和/或底层侧的空闲的地方进行布线，还可以再设计追加面。对连接于GND面的焊盘(VSS、VSSQ)也可以做成同样的布线。
如图12所示，在第一连接焊盘群中，通过表层侧和/或底层侧的信号层而与普通引脚连接的芯片引脚用的焊盘701，除了用后述的通路与底层侧的焊盘直接连接的焊盘外，通过作为表层侧信号层的一部分的布线(分支布线)703连接到第一及第二连接焊盘中的对应的焊盘的中间点近旁形成的通路702上。第二连接焊盘群的对应的焊盘704通过作为底层侧信号层的布线(分支布线)705连接到同一个通路702上。也就是说，利用信号层的布线而连接于各普通引脚的一对芯片引脚用的焊盘对701、704，通过在它们的中间点的近旁形成的通路702而相互连接。把一对连接焊盘701、704连接起来的通路702通过表层侧或底层侧信号层的布线(共用布线)706或707连接到对应的普通引脚用的外部连接焊盘上。分支布线703和705以及使它们进行连接的通路702统称为分支布线部。通过这种构成，就能够使相互对应的一对连接焊盘(芯片引脚)所连接的分支布线的长度实质上(实用上不产生问题的程度)相等。
如图13所示，在第一连接焊盘群中，通过表层侧和/或底层侧的信号层而与普通引脚连接的连接焊盘中其余的焊盘801则通过通路803直接连接到位于底面侧的第二连接焊盘群的连接焊盘802上。这是考虑到，在各半导体芯片11、12的引脚中，即使变换其功用，也不存在妨碍。例如，使各半导体芯片11、12的引脚担当图6所示的功用时，夹着挠性基板13、且相对配置的第一及第二半导体芯片中的一个半导体芯片的DQ 0、DQ 1、DQ 2以及DQ 3引脚就会与另一个半导体芯片的DQ 1、DQ 0、DQ 3以及DQ 2引脚对接。此处，各半导体芯片的DQ 0、DQ 1、DQ 2以及DQ 3引脚，由于能够变换其功用，从而即使把相互对接的引脚连接于相同的普通引脚也不会有任何问题。因此，通过通路803，把与这些引脚连接的第一连接焊盘群的连接焊盘801直接连接到位于其底面的第二连接焊盘群的连接焊盘802上。接着，通过表层侧或底层侧的信号层的布线804或805，把利用通路803相互连接的一对连接焊盘801、802中的一个焊盘连接到对应的普通引脚上。在这种情况下，通路803构成分支布线，布线804或805则成为与其连接的共用布线。
另外，对于可以用通路直接连接的焊盘，根据设计上或者制造上的情况，与上述的焊盘相同，也可以在相互对应的两个连接焊盘的中间点近旁形成通路而相互连接。或者，可以不把位于表、底的引脚彼此直接连接，而是在别的位置形成通路，利用布线使它们进行连接。用通路直接连接焊盘时，在焊盘上形成通路，进行直接连接，不过，不言而喻，也可以在焊盘近旁形成通路，进行直接连接。
下面，对于第一及第二连接焊盘群与外部连接焊盘之间的连接，特别是与连接于普通引脚的芯片引脚用的连接焊盘有关的连接，列举具体例子进行说明。
图14(a)是表示挠性基板13的表层侧信号层的一部分(对应于半导体芯片的A～D行)的图。还有，图14(b)是对应于图14(a)的挠性基板13的底层侧信号层的一部分。另外，图14(a)及14(b)都是从表面(上面)侧对挠性基板13进行观看的图。
如图14(a)所示，第一半导体芯片的A8引脚用的连接焊盘通过表层侧的布线(分支布线)71连接到通路72上。另一方面，如图14(b)所示，第二半导体芯片的A8引脚用的连接焊盘通过底层侧的布线(分支布线)73连接到通路72上。此处，为了使布线71与布线73的长度相等，通路72在第一半导体芯片的A8引脚用的连接焊盘与第二半导体芯片的A8引脚用的连接焊盘的中间点的近旁形成。形成布线71与布线73，以致于使它们的长度实质上相等，且成为传输路径(阻抗匹配)。通路72再通过底层侧信号层的布线(共用布线)74连接到通路75上，通路75位于与A8封装件引脚用的连接焊盘连接形成的下面的区域54。
第一及第二半导体芯片的B3引脚用的连接焊盘，与A8引脚用的连接焊盘相同，通过在它们的中间点近旁形成的通路76而相互连接。该通路76与A8引脚用的通路72不同，通过表层侧信号层的信号线77连接到B3封装件引脚用的焊盘上。
第一及第二半导体芯片的B7引脚所对应的连接焊盘，也与A8引脚用的连接焊盘的情况相同，连接到B7封装件引脚用的焊盘的底面的通路78上。
如图14(a)所示，第一半导体芯片的C2引脚及D3引脚用的连接焊盘，通过表层侧的布线，分别连接到C8封装件引脚及D7封装件引脚用的外部连接焊盘上。还有，尽管没有示出，不过，这些C2引脚及D3引脚用的连接焊盘通过通路分别直接连接到底面侧的第二半导体芯片的C8引脚及D7引脚用的连接焊盘上。
另一方面，如图14(b)所示，第二半导体芯片的C2引脚及D3引脚用的连接焊盘通过底层侧的布线连接到C2封装件引脚及D3封装件引脚所分别连接的通路上。还有，尽管没有示出，不过，这些C2引脚及D3引脚用的连接焊盘，通过通路，分别连接到表面侧的第一半导体芯片的C8引脚及D7引脚用的连接焊盘上。
另外，如同A1引脚用的连接焊盘那样，连接于VDD板的焊盘通过通路直接连接于VDD板。对于连接于GND板的焊盘也一样。
还有，与选择引脚连接的芯片引脚用的连接焊盘，与第一及第二C2引脚或者D3引脚用的连接焊盘相同，通过表面侧或底面侧的信号层的布线来实现。
下面，对在挠性基板上形成的布线进行说明。挠性基板13是具有接地和/或电源布线的多层基板，信号布线图中的大部分(最好是所有线)与接地和/或电源布线一起构成传输线路。参照图15至18，对信号布线图的传输线路的构成进行说明。
如图15(a)及(b)所示，传输线路由信号布线图81和与该信号布线图81邻接的层的接地面和/或电源面(平板布线)82，作为微带线路来构成。还有，如图16(a)及(b)所示，传输线路由信号布线图81和与其两侧邻接的接地面和/或电源面(平板布线)82a、82b作为带状(strip)线路来构成。或者，如图17(a)及(b)所示，传输线路由信号布线图81和在其同一层上、在单侧(或两侧)邻接、平行的接地和/或电源布线83，作为平行线路来构成。对上述的传输线路构成进行适当的选择、组合来构成信号布线图。
另外，构成微带线路或带状线路的接地面和/或电源面(平板布线)82、82a、82b的宽度不小于信号布线图81的宽度。
还有，如图18(a)所示，构成传输线路的接地面和/或电源面(平板布线)82、82a、82b，可以由多个接地布线部和/或电源布线部分91、92构成。
再有，如图18(b)所示，构成传输线路的接地面和/或电源面(平板布线)82、82a、82b，可以由通路95或其它布线96部分地进行分断。
以上以实施例的方式对本发明进行了说明，不过，本发明并不限于上述实施例的方式。
例如，在上述说明中，封装件引脚的位置做成与第一半导体芯片的芯片引脚的位置在上下方向一致，不过，如图19所示，为了缩短共用布线的长度，也可以使封装件引脚的位置进行偏移。还有，如图20(a)及(b)所示，也可以使封装件引脚的配置与第一半导体芯片的芯片引脚的配置完全不同。

Claims (11)

1.一种层叠型半导体封装件，包括：
基板，具有相对的第一及第二表面；以及
第一及第二半导体芯片，其中的每一半导体芯片具有安装面，所述安装面上具有按预定的图形排列的多个芯片引脚，
所述第一及第二半导体芯片分别安装于所述基板的第一及第二表面，使所述安装面相对而置，在所述安装面的中间夹着所述的基板。
2.根据权利要求1所述的层叠型半导体封装件，其中：
所述基板在所述第一及第二表面上的、与安装所述两个半导体芯片的安装区域不同的区域，具有与所述芯片引脚分别对应的多个封装件引脚。
3.根据权利要求2所述的层叠型半导体封装件，其中：
所述多个封装件引脚按照与所述预定的图形相同的图形排列。
4.根据权利要求1所述的层叠型半导体封装件，其中：
所述封装件引脚包括：选择引脚，只与所述第一及第二半导体芯片之一上的对应芯片引脚连接；以及普通引脚，与所述第一及第二半导体芯片的每一半导体芯片上的对应芯片引脚连接。
5.根据权利要求4所述的层叠型半导体封装件，其中：
所述基板具有：共用布线，其一端连接于所述普通引脚；以及分支布线部，将所述共用布线的另一端连接到两个芯片引脚上，这两个芯片引脚是所述第一及第二半导体芯片的对应芯片引脚；
从所述共用布线的一端至所述对应芯片引脚的布线长度实质等于从所述共用布线的所述一端至另一个所述对应芯片引脚的布线长度。
6.根据权利要求5所述的层叠型半导体封装件，其中：
所述分支布线部包括：通路，形成在所述两个芯片引脚的中间位置近旁，且连接于所述共用布线的另一端；以及第一及第二分支布线，它们的长度实质上相等，并且它们将所述通路与所述两个芯片引脚相连接。
7.根据权利要求5所述的层叠型半导体封装件，其中：
与所述普通引脚对应的两个芯片引脚隔着所述基板而相互面对面，所述分支布线部具有与所述两个芯片引脚直接连接的通路。
8.根据权利要求1所述的层叠型半导体封装件，其中：
所述基板是具有接地面和/或电源面的多层基板，所述共用布线及分支布线部与所述接地面和/或所述电源面一起构成传输线路。
9.根据权利要求8所述的层叠型半导体封装件，其中：
所述传输线路包括微带线路、带状线路以及平行线路之中的任意一种。
10.根据权利要求9所述的层叠型半导体封装件，其中：
所述接地面和/或所述电源面包括由多个接地面部件和/或电源面部件形成的部分以及部分地被通路或其它布线分断的部分。
11.根据权利要求1所述的层叠型半导体封装件，其中：
所述半导体芯片为：单体芯片，即裸管芯；或者，具有封装结构的芯片，即：把所述单体芯片安装在基板上，通过焊丝、内部引线连接、倒装焊接或类似方法，使所述单体芯片的引线或焊盘与所述基板上的引线进行电连接，为了保护所述基板、晶片级CSP或晶片工序封装件上的导体图形，把所述芯片及基板密封在树脂模中，成为封装件。
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