TW498429B - Power MOSFET and method for forming same using a self-aligned body implant - Google Patents
Power MOSFET and method for forming same using a self-aligned body implant Download PDFInfo
- Publication number
- TW498429B TW498429B TW090117818A TW90117818A TW498429B TW 498429 B TW498429 B TW 498429B TW 090117818 A TW090117818 A TW 090117818A TW 90117818 A TW90117818 A TW 90117818A TW 498429 B TW498429 B TW 498429B
- Authority
- TW
- Taiwan
- Prior art keywords
- source
- patent application
- scope
- item
- trench
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000007943 implant Substances 0.000 title claims description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 125000006850 spacer group Chemical group 0.000 claims abstract description 30
- 210000000746 body region Anatomy 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 2
- 239000010410 layer Substances 0.000 description 77
- 230000003071 parasitic effect Effects 0.000 description 9
- 238000012546 transfer Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000008267 milk Substances 0.000 description 2
- 210000004080 milk Anatomy 0.000 description 2
- 235000013336 milk Nutrition 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 244000046052 Phaseolus vulgaris Species 0.000 description 1
- 235000010627 Phaseolus vulgaris Nutrition 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 244000269722 Thea sinensis Species 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/905—Plural dram cells share common contact or common trench
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Description
90117818 "^7^5^說明(1) 介年:月a 曰 修正 相關申請案 本案係基於2000年7月20日所提出之第60/219, 858號共 同臨時申請案,該臨時申請案之完整揭露係併合此以作為 參考。 本發明之範圍 本發明係關於半導體裝置方面’及特別是關於一種加有 溝/閘之功率金氧半導體場效電晶體。 本發明之背景 電子工業已表示除適當結實外對具有低接通電阻 (RDSon),大阻隔電壓(VDSBR)及低閘電荷元小型分離功率 金氧半導體場效電晶體(M0SFET)之非常需要,結實性限定 該裝置之安全操作區(S 0 A )及鬆開之電感性轉接(u I S ),具 有此等特性之最佳組合,可獲致特別低之接通狀態功率損 失及接轉損失,導致例如D C - D C變換器之系統中高功率轉 換效率。 經發展出超稠密加有溝/閘之功率Μ 0 S F E T以滿足上述之 需要。藉緊縮單元節距,即減少功率Μ 0 S F Ε Τ之尺寸,以使 更多之功率M0SFET能在矽之每平方面積中形成而可獲得較 低之接通電阻(〇 η - r e s i s t a n c e),但經常係以減低裝置之 結實性達成。為解決此一負影響,具有減縮單元節距之裝 置必須設計為在災難性誤失發生之前可吸收更多之能量 (包括DC及動態功率散逸)。 加有溝/閘之功率Μ 0 S F Ε T之基本概念係參照圖1 - 3予以舉 例說明。圖1表示習用之加溝閘功率金氧半導體場效電晶
O:\72\72671-910621.ptc 第5頁 498429
體ι〇。閘12係位於p賴内所形成之溝14中,至㈣成源 本體接觸區18,一相當之敍刻掩蔽必須對準於溝14, 源電極22與閘氧化物層24間之電介質層2〇覆蓋N+源區26 ,-部分平表δ ’覆蓋N+源區26之電介質層2〇之大小係由 :大之閘-源極定率決定之。因&,習用結構之最小單元
=距係受源/本體接觸掩蔽之不對準容許度加上表面電介 質層2 〇所取間隔之限制。 此項限制可用圖2及3中所示設溝技術予以排除,在結果 所得之裝置結構28中,閘12係退藏於溝14甲,留下大得足
夠供兒介質層20用之凹入區。可決定該電介質層2〇之最後 厚度之該凹入區深度係由最大之閘一源極定率確定之。在 已氣知電介質層2 0之後,返回作該層蝕刻,使用平坦石夕表 面3 2作為終止點。 與圖1中所示之習用設有溝—閘之功率从〇51?]£7 ^ 〇比較, 此裝置28提供非常高之通道密度。此裝置28在圖2中標以 3a及3b之不同位置之截面圖係分別例示於圖3a及化中。為 形成具有非常小之單元節距之裝置28而無源/本體接觸蝕 刻掩蔽步驟之嚴格要求,可將P+源/本體接觸區18中斷並 定期沿其N +條紋放置,在該處N +源區2 6被完全排除。 不幸者’ P +源/本體接觸區1 8之定期配置增加該裝置? $ 之接通電阻,以及寄生BJT之基極電阻與共同基極電流增 益。該寄生BJT乃以N+源區26,P阱16及N外延層9形成結曰 果,該寄生BJT將以極低之電流接通,導致不良之s〇A及較 低之UIS能力。
頁 498429 五、發明說明(3) 本發明之概要 :::::::’是以本發明之目在提供-種具有降低 ^ ^ ,閘功率金氧半導體場效電晶體及其形成 方法。 本發明之另一目的為# A5P ^ 、不減乂衣置結實性之加溝/閘 力率i乳+ ¥月且野效電晶體(M〇SFET)。 根據本發明之此等與其他優點, 功率MOSFET之方法提佴,吁古、土 4八r 的知由衣以 之一、、蓋# &禰熱$、#,、汶方法匕3形成在一半導體層中 之溝形成襯墊5亥溝之一閘介質層 分中之一閙導雷屏;s r S /箅t下δ部 :層及%成-電介質層以充填該溝之上面部 夂另=將側面鄰接該電介質層之半導體層之 =間隔?,使其側面鄰接該電介質層=;卜卜之= 刀亚且用作自仃對準掩蔽以限定源/本體接觸區。 結果所得之設有溝閘之功率M0SFET乃 °成° =之接通電阻,並使裝置之結實性不=也 7^太\低乃因母一M〇SFET包括一源/本體接觸區之故,今 源/本體接觸區提供M0SFET之源及本體區域間之^ 4 路’結果裝置之結實性被增加。 有效短 :外:接通電阻之被減低係因該電介質層完全形成於該 溝内之結果而減縮功率M0SFET之單元節距之故。'了 4黾介貝層並不在源區之表面上, + 接觸區縮成最小。 了使源£與源電極間之
第7頁 498429 五、發明說明(4、) 降低功率MOSFET之接通電阻盥罝々…扣 ΐ ^ ^n n ψ ^ ^ ^ ^# # #j 限疋源/本體接觸區域。 ^ Τ 伸之帝八拼昆π U芍各間隔物係自行對準向外延 ^ 丨貝層,可避免源/本體接觸掩蔽不對準公差。 本發明之另一具體實例為進一 //// 對進也# 乂便用各間隔物作為自行 1準掩敝,以在限定源/本體接 遮蓋之一卹八々增舰⑦ 示古禾叉間物 較低之二匕t::: 半導體層之一部分除去,需用 軏T之此里内植滲雜劑,以形成源/本體接觸區。 此外:源/本體接觸區由於其一部分已除去之結 及:ΐ深處形成,此可減少寄生bjt之基本電阻 MOSFETr^ ’而增進裝置結實性,亦即增加功率 MOSFET之女全操作範圍(s〇A)及鬆開之電感性接轉(Η” ^ 層且各部分之移除係執行至等於或小於約1微 不之冰度该閘導電層則係凹入於溝中在從其—開口起之約 〇· 2至〇. 8微米範圍内,可將功率M〇SFET形 ’ 洁今十人 通運或p通 、之功¥金氧半導體場效電晶體。 本發明之另一特色係指向一種由其中有_溝之半導體 層’襯墊該溝之一閘介質層及在該溝下面部分之一問^電 層所組成之M0SFET,該M0SFET宜另包括在該溝上面;分二 層及從半導體層向外延伸之一電介質層,各源區宜鄰^向 外延伸之電介質層及源/本體接觸區宜在側面盥爲 留間隔。 一阑V 4層 功率M0SFET之另一實例係關於各源區,其中源區之一部
第8頁 五、發明說明(5) —-' ^包括在源/本體接觸區上方之一凹處。在又另一實例 。源區包括暴露本體區域之一開口,故源極乃與源/ 本體接觸區相接觸。 又、 1式之簡單說明 ' 圖1為根據先前技藝之一習用設有溝—問之功率Μ 0 S F Ε Τ。 圖2為根據先前技藝使用設溝技術形成之設有溝閘之功 二 率MOSFET之頂部平面圖。 - 圖3a及31)為圖2中所示分別沿線3a及3b所取之設有溝/閘-之功率MOSFET之截面圖。 圖4為舉例說明根據本發明製作一設有溝/閘之功率 | MOSFET方法之流程圖。 圖5 -1 3為舉例說明根據本發明方法之各處理步驟之設有 溝/閘之功率MOSFET之一部分截面圖。 圖14-1 5為鄰接之設有溝/閘功率M〇SFET之一部分截面 圖,舉例說明根據本發明基於源/本體接觸區之深度之崩 潰電流路徑。 體實例之詰細說明 現在下文中茶考附圖對本發明作更完整之敘述,其中顯 禾本發明之各較佳具體實例,然而本發明可用許多不同方 式予以體現及不應解釋為限於本文所述之各具體實例,此 等實例之所以提供乃使本文所揭露在澈底及完整,及完全 轉達本發明之fe圍,於熟諳本技藝人士,同樣之編號係指 :- 本文中相等之各元件為較清晰起見,各層及區域之尺寸在 - 各圖中可能予以誇張。 -
第9頁 498429 五 '發明說明(6) 么么參閱圖4 ’說明根據本發明製作一設有溝/閘之功率 MOSFET之方法,從開始(方塊40)處起,在方塊42處形成一 溝道於一半導體層中及在方塊44處形成一閘介質層以襯塾 該溝,然後在方塊46處,一閘導電層被形成於該溝之下面 部分,在方塊48處,形成一電介質層以充填該溝之上面部 分。 5亥方法另包括在方塊5 0處’除去该半導體層側面鄰接電 介質層之部分’故其上部從該半導體層向外延伸,在方塊 5 2處,形成各間隔物,其側面鄰接該電介質層之向外伸展 之上面部分’以及在方塊54處,將各間隔物用作自行對準 掩蔽,以界定源/本體接觸區域。 根據本發明之方法便利地提供一高密度功,具 有使用各間隔物以自行對準方式所形成之源/本體接觸區 域,因為各間隔物係自行對準向外伸展之電介質層,該功 率MOSFET之最小單元節距不受源/本體楱觸掩蔽不對準容 限之限制。 此外,接通電阻被降低乃係每一M〇SFET具有源/本體接 觸區之結果。此亦有助於降低寄生BJT之基極電阻及丘 之基極電流增i,寄生奶將以較高電流接通 : 之SOA及較高之UIS能力。 ^ 肉此夕卜里接通電阻被降低乃因電介質層 内之=使功率廳FET之單元節距為之縮小之故換: 之,該電介質層不在各源區之^ _ 換。
MOSPpI考圖5 —丨3敘述根據本發明製作一設有溝/閘之功率 \方法之各步驟’縱使一η通道功率m〇sfet 70係例示 考圖中,各處理步驟亦可用以形成—p通道 丁 ’如熟諳本技藝在可迅易瞭解者。
ώ型外延層g係形成於半導體基體8上,該半導體基體8 / ’了'η型及以石夕製為宜’該外延層9忍受功率㈣^以了〇之 吸j至源極崩潰電壓,如熟諳本技藝在可欣然瞭解者。
概墊氧化物層7 2係在外延層9上生長,繼以p型摻雜劑 ^植以形成功率M〇SFET 70之p阱或本體區16。該p型摻雜 d例如哪乃使用在約1 E1 3 / c m2至5 E1 4 / c m2範圍内之劑量, 例如在約4 0至2 0 0 k e V範圍内之能量階層予以内植。 一掩罩74係形成於該襯墊氧化物層72之表面上以限定溝 道1 4 °舉例而言,該掩罩了 4可為一低溫度氧化物層,將本 體區1 6及外延層9蝕刻以形成溝丨4,如圖5中所示,然後除 去掩罩7 4。 使一閘介質層2 4生長於該溝1 4之側壁與底部壁上以及在 本體區1 6之表面上,此閘介質層2 4具有在約1 〇至1 〇 〇毫微 米範圍内之厚度,導電材料25例如聚硅(Polys i 1 icon)乃 被澱積於溝14中及在閘介質層24之表面上,如圖6中所 示0 現參閱圖7 ’聚硅25被從p阱1 6之表面移除及返回在溝1 4 内蝕刻以限定在功率M0SFET 70之溝1 4下面部分中之退藏 閘1 2 ’凹入該溝1 4内閘1 2之深度係在從該溝之開口起算約 0 · 2至0. 8微米之範圍内。
第11頁 498429 五、發明說明(8) 電介質層7 6係澱積於閘介質層2 4之表面上及閘1 2之表面 上,電質層7 6係用以隔離閘1 2。將表面介質層7 6除去,及 使本體區16之上部表面與在溝14内之電介質層20之上表面 成為平面,如圖8中所示者。 在本體區16之上部表面及溝〗4内之電介質層20之上表面 變成平面後’將11型摻雜劑移植於鄰接電介質層之本體區 1 6,以限定功率mosFET 70之源區2 6 , η型摻雜劑例如砷或 磷乃使用例如在約2E15/cm2至2E16/Cm2範圍内之劑量及例 如在約40至20 0 keV範圍内之能量階層予以植入,直後進 行在約9 0 0至11〇〇 t之溫度範圍内之退火。 ’、 將側面鄰接電介質層之表面部分移除 4分之厚度係在約〇. 1至丨微米之苑 矛、〜衣面 詳細說明者,向外伸展之電介声:,如將在下文" 各間隔物得以形成。 貝層20便利地使自行對準《 •因為#刻該表面層時’源區26之摻 只施另一源區之内植以增強源區之摻j /辰度可卜低,3 及者,可使用相同之劑量及能 嘬度,如前文所黯 :法之另-方 <,内植n型摻雜項增強。作為所站 去側面鄰接電介質層之表面邱分以 疋源區26可在已除 層20之後付諸實施,用此方法,僅=^向外伸展之電介貿 26。 〜次移值以限定源區 ;然後’在電介質層20及源區26上 该氮化物澱積以形成各間隔物80,如图物澱積,蝕刻 498429 五、發明說明(9) 娜 使用各間隔物80作為自行對準之掩蔽,將p型摻雜劑植 入本體區域1 6以界定源/本體接觸區8 2,如圖1 1甲所示。p 型摻雜劑例如硼乃以高能階植入,以期滲透源區2 6,蝴之 内植可使用例如在約2E15/cm2至2E16/cm2範圍内之劑量及 在例如約120至4 0 0 keV之能階,其後完成在約攝氏9〇〇至 1100度之溫度範圍内之退火。 除去各間隔物8 0,並在源區2 6上形成一源極8 4。此方法 另包括在源極84與源/本體接觸區82間形成至少一導電通 路86,一吸極係在基體8之底邊上。 源/本體接觸區82係在本體區16與源區26間繼續接觸。 換舌之,每一功率MOSFET包括一源/本體接觸區82,此有 助於降低功率MOSFET 70之接通電阻,又此亦有助於減少 寄生B J T之基極電阻與共同之基極電流增益,該寄生β j 丁將 以較高之電流接通,導致改良之S〇a及較高之uis能力。 此外’接通電阻之降低乃因電介質層20係完全形成於溝 14内之結果使功率M〇SFET 70之單元節距減縮之故。換言 之’電介質層2 0不在源區2 6之表面上,可使源區與源極間 之接觸區縮至最小。結果,本體區1 6,閘丨2,源區2 6及源 /本體接觸區8 2限定約例如〇 · 5微米之單元節距。 代替使用高能階内植摻雜劑以限定源/本體區82,設若 如間隔物80被用作自行對準掩蔽以移除未受各間隔物遮蔽 之一部分源區2 6,則可使用低之能量,如圖1 2中所最佳例 不者。已移除間隔物8 0未遮蓋之源區2 6之一部分。此功率 M〇SFET乃以參考編號70’表示之。
第13頁 498429 五、發明說明(ίο) 除去源區2 6之一部分具有使源/本體接觸區8 2得以使用 低能量限定之優點,p型摻雜劑例如硼亦可使用在例如約 2E1 5/cm2至2E1 6/cm2範圍内之劑量予以植入,但能量現係 在例如約40至120 keV之範圍内,如上所述者,其後實施 在攝氏約900至1100度溫度範圍内之退火此功率μ 在 圖12中係以參考編號70,表示之。, 作為另一實例,將未被各間隔物80遮蓋之源區26之一部 分完全除去,在源/本體接觸區82已用低能量限定後,源 極84即直接與各接觸區在一起,此功率在圖13中 係以參考編號7〇”表示之。 除去未被間隔物8 0所遮蔽源區2 6之全部及甚至在下面之 本體區16之一部分,所獲之利益為可將源/本體接觸區82 更深入形成於本體區16内。此可減少寄生Bjt之共同基極 兒流增盃,有助於增進裝置之結實性,亦即增加安全操作 範圍(SOA)及增加功率M0SFET之鬆開電感性接轉(UIS)。 源/本體接觸區82之深度亦影響崩潰電流之路徑,如圖 U及1 5中所最佳例示者。舉例而言,當使用各間隔物8〇以 $刻經由源區2 6而進入本體區1 6相當於0 · 5微米之深度 時’模擬之崩潰電流90在到達源/本體接觸區82之前,流 至溝1 4之底部,如圖1 4中所示,此相當於3 9 · 6 7 V之閉実 電壓(VDSBR)。 1 ★然而’增加蝕刻之深度至例如0 · 8微米,模擬之崩潰電 w 9 0有一較短之路徑可資遵循,因其並不流至溝1 4底部之 故’如圖15中所示者,此相當於3 6 · 75 v之閉塞電壓
第14頁 498429 五、發明說明(11) (VDSBR)。所以圖1 5中之設有溝/閘功率MOSFET裝置乃較圖 1 4中所示之裝置為更結實。 本發明之另一特色係指上文中揭示方法結果所形成之功 率MOSFET 70,該功率MOSFET 70包含其中有一溝14之半導 體層8 ’ 9,襯墊該溝之一電介質層2 4,及在該溝下面部分 之一閘導電層1 2。 一電介質層2 0係在溝1 4之上面部分並從半導體層8,9向 外伸展。源區2 6係鄰接向外延伸之電介質層2 〇,及源/本 月豆接觸區8 2在侧面與閘導電層1 2隔開。 功率MOSFET 70’之另一實例係關於源區26,其中各源區 2 6之:部分包括在源/本體接觸區上面之一凹處,如圖1 2 不,在功率M0SFET之又另一實例中,各源區26包括 ^路本體區1 6之一開口,故源極84乃與一源/本體接觸區 82接觸,如圖13中所示。 及 解 正 ,發明之許多修正與其他之實例可為獲益於前列說明中 2圖所表達教導之熟諳本技藝人士所顯見。因此,可瞭 ^月並非限於所發表之特殊實例,以及旨在將各種修 與貫例包括在所附申請專利範圍之範圍内。
第15頁 498429
第16頁
Claims (1)
- 498429—MM π 90117818 年6月二/ 曰 修正 \、申請專利範圍 1 . 一種製作功率金氧半導體場效電晶體(MOSFET)之方 法,包含: 形成在一半導體層中之一溝; 形成襯墊該溝之一閘介質層; 形成在該溝之下面部分之一閘導電層; 形成充填該溝之上面部分之一電介質層; 除去側面鄰接該電介質層之半導體層之各部分,故其 上面部分從該半導體層向外伸展; 形成側面鄰接該電介質層向外延伸之上面部分之各間 隔物;以及 使用各該間隔物作為限定源/本體接觸區之自行對準 掩蔽 2. 作為 觸區 3. 作為 導體 4. 行至 度。 5. 隔物 區 。 根據申請專利範圍第1項之方法,其中使用各間隔物 自行對準之掩蔽,包含内植摻雜劑以限定源/本體接 〇 根據申請專利範圍第1項之方法,其中使用各間隔物 自行對準之掩蔽,包含蝕刻未被各間隔物所遮蓋之半 層。 根據申請專利範圍第3項之方法,其中所述之餘刻執 從該半導體層之表面起達等於或小於約1微米之深 根據申請專利範圍第1項之方法,另包含於形成各間 之前在鄰接向外伸展電介質層之半導體層中形成各源O:\72\72671-910621.ptc 第17頁 498429 __案號90117818 年 < 月上/日 修正_ 六、申請專利範圍 6. 根據申請專利範圍第5項之方法,另包含在各源區上 及該電介質層上形成一源極。 7. 根據申請專利範圍第6項之方法,另包含在源極與源 /本體接觸區之間形成至少一導電性通路。 8. 根據申請專利範圍第5項之方法,另包含在各源極區 上,在該電介質層上以及在源/本體接觸區上形成一源 極〇 9. 根據申請專利範圍第1項之方法,另包含將各間隔物 除去。 10. 根據申請專利範圍第1項之方法,其中除去半導體 層部分係執行至從其表面起達等於或小於約1微米之深 度。 11. 根據申請專利範圍第1項之方法,其中該閘導電層 係退藏於該溝中,在從其一開口起約0 . 2至0 . 8微米之範圍 内〇 12. 根據申請專利範圍第1項之方法,另包含在鄰接該 溝之半導體層中形成一本體。 13. 一種用以製作一MOSFET之方法,包含: 形成在一半導體層中之一溝; 形成襯墊該溝之一閘介質層; 形成在該溝之下面部分之一閘導電層; 形成充填該溝之上面部分之一電介質層; 除去該半導體層之側面鄰接電介質層部分,故其上面 部分從半導體層向外伸展;O:\72\7267I-9lQ62i.ptc 第18頁 498429 _案號90117818_f/年 < 月jl/曰 修正_ 六、申請專利範圍 形成側面鄰接電介質層之向外延伸部分之各間隔物; 使用各間隔物作為自行對準掩蔽,以蝕刻未為間隔物 遮蓋之半導體層;及 使用各間隔物作為自行對準掩蔽,以植入摻雜劑而限 定源/本體接觸區。 14. 根據申請專利範圍第1 3項之方法,其中所述之蝕刻 係執行至從該半導體之表面起算等於或小於約1微米之深 度。 15. 根據申請專利範圍第1 3項之方法,另包含於形成各 間隔物之前,在鄰接向外伸展之電介質層之半導體層中形 成各源區。 16. 根據申請專利範圍第1 5項之方法,另包含形成一源 極於各源區上及該電介質層上。 17. 根據申請專利範圍第1 6項之方法,另包含形成至少 一導電性通路於源極及源/本體接觸區之間。 18. 根據申請專利範圍第1 5項之方法,另包含形成一源 極於各源區上,該電介質層上及源/本體接觸區上。 19. 根據申請專利範圍第1 3項之方法,另包含移除各間 隔物。 2 0. 根據申請專利範圍第1 3項之方法,其中半導體層各 部分之移除係執行至自其表面起算等於或小於約1微米之 深度。 2 1. 根據申請專利範圍第1 3項之方法,其中該閘導電層 係退藏於該溝中從其一開口起在約0 . 2至0 . 8微米之範圍0: \72\72671-910621.ptc 第19頁 498429 _案號90117818_外年 < 月二/日 修正_ 六、申請專利範圍 内。 22. 根據申請專利範圍第1 3項之方法,另包含形成一本 體區於鄰接該溝之半導體層中。 23. 一種金氧半導體場效電晶體(MOSFET),包含: 一半導體層,其中有一溝; 襯墊該溝之一閘介質層; 在該溝之下面部分中之一閘導電層; 在該溝之上面部分及自該半導體層向外伸展之一電介 質層; 鄰接向外伸展之電介質層之各源區;及 側面與該閘導電層留間隔之源/本體接觸區。 2 4. 根據申請專利範圍第23項之MOSFET,另包含在各該 源區上及該電介質層上之一源極。 25. 根據申請專利範圍第24項之MOSFET,另包含在各該 源極與源/本體接觸區間之至少一導電性通路。 2 6. 根據申請專利範圍第23項之MOSFET,其中該源區之 一部分包括在該源/本體接觸區上之一凹處。 2 7. 根據申請專利範圍第23項之MOSFET,其中各該源區 之一部分包括暴露該源/本體接觸區之一開口 ,及另包在 各該源區上,在該電介質層上,及在各該源/本體接觸區 上之一源極。 2 8. 根據申請專利範圍第23項之MOSFET,其中該向外伸 展之電介質層從各該源區延伸等於或小於約1微米。 2 9. 根據申請專利範圍第23項之MOSFET,其中該閘係退O:\72\72671-91062i.ptc 第20頁 498429 _案號 90117818_外年Z月;/曰__ 六、申請專利範圍 藏於該溝中,在從其開口起算約0. 2至0 . 8微米之範圍内。 3 0 . 根據申請專利範圍第2 3項之Μ 0 S F E T,其中該源/本 體接觸區係退藏於鄰接該源區之半導體層内。 3 1. 根據申請專利範圍第3 0項之Μ 0 S F Ε Τ,其中該凹處之 上表面從該半導體之表面起乃係等於或小於約1微米之深 度。O:\72\72671-910621.ptc 第21頁
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US21985800P | 2000-07-20 | 2000-07-20 | |
US09/844,347 US6921939B2 (en) | 2000-07-20 | 2001-04-27 | Power MOSFET and method for forming same using a self-aligned body implant |
Publications (1)
Publication Number | Publication Date |
---|---|
TW498429B true TW498429B (en) | 2002-08-11 |
Family
ID=26914325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW090117818A TW498429B (en) | 2000-07-20 | 2001-07-20 | Power MOSFET and method for forming same using a self-aligned body implant |
Country Status (7)
Country | Link |
---|---|
US (2) | US6921939B2 (zh) |
JP (1) | JP3954493B2 (zh) |
CN (1) | CN1211844C (zh) |
AU (1) | AU2001276969A1 (zh) |
DE (1) | DE10196441B4 (zh) |
TW (1) | TW498429B (zh) |
WO (1) | WO2002009177A2 (zh) |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7345342B2 (en) * | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
US6916745B2 (en) | 2003-05-20 | 2005-07-12 | Fairchild Semiconductor Corporation | Structure and method for forming a trench MOSFET having self-aligned features |
FI120310B (fi) * | 2001-02-13 | 2009-09-15 | Valtion Teknillinen | Parannettu menetelmä erittyvien proteiinien tuottamiseksi sienissä |
KR100859701B1 (ko) * | 2002-02-23 | 2008-09-23 | 페어차일드코리아반도체 주식회사 | 고전압 수평형 디모스 트랜지스터 및 그 제조 방법 |
US7576388B1 (en) * | 2002-10-03 | 2009-08-18 | Fairchild Semiconductor Corporation | Trench-gate LDMOS structures |
US7652326B2 (en) | 2003-05-20 | 2010-01-26 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
US7368777B2 (en) | 2003-12-30 | 2008-05-06 | Fairchild Semiconductor Corporation | Accumulation device with charge balance structure and method of forming the same |
JP2007531988A (ja) * | 2004-03-01 | 2007-11-08 | インターナショナル レクティファイアー コーポレイション | トレンチデバイスのための自動整合された接点構造体 |
US7352036B2 (en) | 2004-08-03 | 2008-04-01 | Fairchild Semiconductor Corporation | Semiconductor power device having a top-side drain using a sinker trench |
DE102004057237B4 (de) * | 2004-11-26 | 2007-02-08 | Infineon Technologies Ag | Verfahren zum Herstellen von Kontaktlöchern in einem Halbleiterkörper sowie Transistor mit vertikalem Aufbau |
JP2006202931A (ja) * | 2005-01-20 | 2006-08-03 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7395405B2 (en) * | 2005-01-28 | 2008-07-01 | Intel Corporation | Method and apparatus for supporting address translation in a virtual machine environment |
CN101882583A (zh) * | 2005-04-06 | 2010-11-10 | 飞兆半导体公司 | 沟栅场效应晶体管及其形成方法 |
DE112006001516T5 (de) | 2005-06-10 | 2008-04-17 | Fairchild Semiconductor Corp. | Feldeffekttransistor mit Ladungsgleichgewicht |
US7385248B2 (en) * | 2005-08-09 | 2008-06-10 | Fairchild Semiconductor Corporation | Shielded gate field effect transistor with improved inter-poly dielectric |
DE102005055838B4 (de) * | 2005-11-23 | 2007-10-04 | Infineon Technologies Ag | Verfahren und Vorrichtung zum ermöglichen tiefliegender Halbleiterkontakte |
US7667265B2 (en) * | 2006-01-30 | 2010-02-23 | Fairchild Semiconductor Corporation | Varying mesa dimensions in high cell density trench MOSFET |
US7446374B2 (en) | 2006-03-24 | 2008-11-04 | Fairchild Semiconductor Corporation | High density trench FET with integrated Schottky diode and method of manufacture |
US7319256B1 (en) | 2006-06-19 | 2008-01-15 | Fairchild Semiconductor Corporation | Shielded gate trench FET with the shield and gate electrodes being connected together |
DE102006029750B4 (de) * | 2006-06-28 | 2010-12-02 | Infineon Technologies Austria Ag | Trenchtransistor und Verfahren zur Herstellung |
DE102006049354B3 (de) * | 2006-10-19 | 2008-06-05 | Infineon Technologies Ag | Verfahren zur Herstellung eines Anschlusskontakts auf einem Halbleiterkörper |
US7989882B2 (en) | 2007-12-07 | 2011-08-02 | Cree, Inc. | Transistor with A-face conductive channel and trench protecting well region |
US7772668B2 (en) | 2007-12-26 | 2010-08-10 | Fairchild Semiconductor Corporation | Shielded gate trench FET with multiple channels |
US7910439B2 (en) * | 2008-06-11 | 2011-03-22 | Maxpower Semiconductor Inc. | Super self-aligned trench MOSFET devices, methods, and systems |
WO2010008617A1 (en) * | 2008-07-15 | 2010-01-21 | Maxpower Semiconductor Inc. | Mosfet switch with embedded electrostatic charge |
TWI380448B (en) * | 2009-09-16 | 2012-12-21 | Anpec Electronics Corp | Overlapping trench gate semiconductor device and manufacturing method thereof |
JP2011134985A (ja) | 2009-12-25 | 2011-07-07 | Fuji Electric Co Ltd | トレンチゲート型半導体装置とその製造方法 |
US8432000B2 (en) | 2010-06-18 | 2013-04-30 | Fairchild Semiconductor Corporation | Trench MOS barrier schottky rectifier with a planar surface using CMP techniques |
JP5562917B2 (ja) | 2011-09-16 | 2014-07-30 | 株式会社東芝 | 半導体装置及びその製造方法 |
US9082746B2 (en) * | 2012-01-16 | 2015-07-14 | Infineon Technologies Austria Ag | Method for forming self-aligned trench contacts of semiconductor components and a semiconductor component |
JP6170812B2 (ja) | 2013-03-19 | 2017-07-26 | 株式会社東芝 | 半導体装置の製造方法 |
CN105097543A (zh) * | 2014-05-23 | 2015-11-25 | 北大方正集团有限公司 | 一种沟槽型vdmos器件及其制造方法 |
JP2016058679A (ja) * | 2014-09-12 | 2016-04-21 | 株式会社東芝 | 半導体装置およびその製造方法 |
DE102014115321B4 (de) * | 2014-10-21 | 2018-03-29 | Infineon Technologies Austria Ag | Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung mittels einer Ausrichtungsschicht |
CN104576743B (zh) * | 2015-01-28 | 2017-10-20 | 无锡新洁能股份有限公司 | 沟槽功率mos器件及其制造方法 |
CN106898549A (zh) * | 2015-12-21 | 2017-06-27 | 株洲南车时代电气股份有限公司 | 沟槽栅igbt及沟槽栅igbt制作方法 |
JP6784164B2 (ja) * | 2016-12-15 | 2020-11-11 | 株式会社豊田中央研究所 | 半導体装置 |
CN110047759A (zh) * | 2019-04-28 | 2019-07-23 | 矽力杰半导体技术(杭州)有限公司 | 沟槽型mosfet器件制造方法 |
CN112447844A (zh) * | 2019-09-03 | 2021-03-05 | 南通尚阳通集成电路有限公司 | 半导体器件的制造方法 |
Family Cites Families (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4694313A (en) * | 1985-02-19 | 1987-09-15 | Harris Corporation | Conductivity modulated semiconductor structure |
US5283201A (en) | 1988-05-17 | 1994-02-01 | Advanced Power Technology, Inc. | High density power device fabrication process |
KR940002400B1 (ko) * | 1991-05-15 | 1994-03-24 | 금성일렉트론 주식회사 | 리세스 게이트를 갖는 반도체장치의 제조방법 |
JPH05304297A (ja) | 1992-01-29 | 1993-11-16 | Nec Corp | 電力用半導体装置およびその製造方法 |
US5283452A (en) * | 1992-02-14 | 1994-02-01 | Hughes Aircraft Company | Distributed cell monolithic mircowave integrated circuit (MMIC) field-effect transistor (FET) amplifier |
GB9306895D0 (en) * | 1993-04-01 | 1993-05-26 | Philips Electronics Uk Ltd | A method of manufacturing a semiconductor device comprising an insulated gate field effect device |
US5349224A (en) * | 1993-06-30 | 1994-09-20 | Purdue Research Foundation | Integrable MOS and IGBT devices having trench gate structure |
JP3708998B2 (ja) | 1994-11-04 | 2005-10-19 | シーメンス アクチエンゲゼルシヤフト | 電界効果により制御可能の半導体デバイスの製造方法 |
US6008520A (en) * | 1994-12-30 | 1999-12-28 | Siliconix Incorporated | Trench MOSFET with heavily doped delta layer to provide low on- resistance |
US5592005A (en) * | 1995-03-31 | 1997-01-07 | Siliconix Incorporated | Punch-through field effect transistor |
US5567634A (en) * | 1995-05-01 | 1996-10-22 | National Semiconductor Corporation | Method of fabricating self-aligned contact trench DMOS transistors |
KR0143459B1 (ko) * | 1995-05-22 | 1998-07-01 | 한민구 | 모오스 게이트형 전력 트랜지스터 |
US6140678A (en) * | 1995-06-02 | 2000-10-31 | Siliconix Incorporated | Trench-gated power MOSFET with protective diode |
US5629543A (en) * | 1995-08-21 | 1997-05-13 | Siliconix Incorporated | Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness |
WO1997007548A1 (en) * | 1995-08-21 | 1997-02-27 | Siliconix Incorporated | Low voltage short channel trench dmos transistor |
US5847464A (en) * | 1995-09-27 | 1998-12-08 | Sgs-Thomson Microelectronics, Inc. | Method for forming controlled voids in interlevel dielectric |
US5721148A (en) * | 1995-12-07 | 1998-02-24 | Fuji Electric Co. | Method for manufacturing MOS type semiconductor device |
US5770878A (en) * | 1996-04-10 | 1998-06-23 | Harris Corporation | Trench MOS gate device |
US5981354A (en) * | 1997-03-12 | 1999-11-09 | Advanced Micro Devices, Inc. | Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process |
KR100225409B1 (ko) * | 1997-03-27 | 1999-10-15 | 김덕중 | 트렌치 디-모오스 및 그의 제조 방법 |
US6037628A (en) | 1997-06-30 | 2000-03-14 | Intersil Corporation | Semiconductor structures with trench contacts |
US5801082A (en) * | 1997-08-18 | 1998-09-01 | Vanguard International Semiconductor Corporation | Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits |
US6121089A (en) | 1997-10-17 | 2000-09-19 | Intersil Corporation | Methods of forming power semiconductor devices having merged split-well body regions therein |
US6429481B1 (en) * | 1997-11-14 | 2002-08-06 | Fairchild Semiconductor Corporation | Field effect transistor and method of its manufacture |
US6396102B1 (en) * | 1998-01-27 | 2002-05-28 | Fairchild Semiconductor Corporation | Field coupled power MOSFET bus architecture using trench technology |
JP3641547B2 (ja) * | 1998-03-25 | 2005-04-20 | 株式会社豊田中央研究所 | 横型mos素子を含む半導体装置 |
US6262453B1 (en) * | 1998-04-24 | 2001-07-17 | Magepower Semiconductor Corp. | Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate |
US6054365A (en) * | 1998-07-13 | 2000-04-25 | International Rectifier Corp. | Process for filling deep trenches with polysilicon and oxide |
US6351018B1 (en) * | 1999-02-26 | 2002-02-26 | Fairchild Semiconductor Corporation | Monolithically integrated trench MOSFET and Schottky diode |
US6351009B1 (en) * | 1999-03-01 | 2002-02-26 | Fairchild Semiconductor Corporation | MOS-gated device having a buried gate and process for forming same |
US6316806B1 (en) * | 1999-03-31 | 2001-11-13 | Fairfield Semiconductor Corporation | Trench transistor with a self-aligned source |
US6188105B1 (en) * | 1999-04-01 | 2001-02-13 | Intersil Corporation | High density MOS-gated power device and process for forming same |
US6413822B2 (en) * | 1999-04-22 | 2002-07-02 | Advanced Analogic Technologies, Inc. | Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer |
US6373098B1 (en) * | 1999-05-25 | 2002-04-16 | Fairchild Semiconductor Corporation | Trench-gated device having trench walls formed by selective epitaxial growth and process for forming device |
US20030060013A1 (en) * | 1999-09-24 | 2003-03-27 | Bruce D. Marchant | Method of manufacturing trench field effect transistors with trenched heavy body |
US6184092B1 (en) * | 1999-11-23 | 2001-02-06 | Mosel Vitelic Inc. | Self-aligned contact for trench DMOS transistors |
US6246090B1 (en) * | 2000-03-14 | 2001-06-12 | Intersil Corporation | Power trench transistor device source region formation using silicon spacer |
JP3773755B2 (ja) * | 2000-06-02 | 2006-05-10 | セイコーインスツル株式会社 | 縦形mosトランジスタ及びその製造方法 |
US6781195B2 (en) * | 2001-01-23 | 2004-08-24 | Semiconductor Components Industries, L.L.C. | Semiconductor bidirectional switching device and method |
-
2001
- 2001-04-27 US US09/844,347 patent/US6921939B2/en not_active Expired - Lifetime
- 2001-07-18 CN CNB018143776A patent/CN1211844C/zh not_active Expired - Lifetime
- 2001-07-18 WO PCT/US2001/022575 patent/WO2002009177A2/en active Application Filing
- 2001-07-18 AU AU2001276969A patent/AU2001276969A1/en not_active Abandoned
- 2001-07-18 DE DE10196441T patent/DE10196441B4/de not_active Expired - Lifetime
- 2001-07-18 JP JP2002514783A patent/JP3954493B2/ja not_active Expired - Fee Related
- 2001-07-20 TW TW090117818A patent/TW498429B/zh not_active IP Right Cessation
-
2005
- 2005-04-12 US US11/104,164 patent/US7501323B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2004515907A (ja) | 2004-05-27 |
CN1211844C (zh) | 2005-07-20 |
US6921939B2 (en) | 2005-07-26 |
CN1447982A (zh) | 2003-10-08 |
US20050184318A1 (en) | 2005-08-25 |
WO2002009177A2 (en) | 2002-01-31 |
US7501323B2 (en) | 2009-03-10 |
US20020008284A1 (en) | 2002-01-24 |
DE10196441B4 (de) | 2009-10-22 |
JP3954493B2 (ja) | 2007-08-08 |
AU2001276969A1 (en) | 2002-02-05 |
DE10196441T1 (de) | 2003-07-17 |
WO2002009177A3 (en) | 2002-06-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW498429B (en) | Power MOSFET and method for forming same using a self-aligned body implant | |
US9748375B2 (en) | Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact | |
US9466700B2 (en) | Semiconductor device and method of fabricating same | |
US8198154B2 (en) | Method of forming bottom-drain LDMOS power MOSFET structure having a top drain strap | |
US7211864B2 (en) | Fully-depleted castellated gate MOSFET device and method of manufacture thereof | |
US8399921B2 (en) | Metal oxide semiconductor (MOS) structure and manufacturing method thereof | |
US11594613B2 (en) | Sawtooh electric field drift region structure for planar and trench power semiconductor devices | |
TW476136B (en) | Method of forming a trench DMOS having reduced threshold voltage | |
JP2010505270A (ja) | 窪んだフィールドプレートを備えたパワーmosfet | |
US20090085107A1 (en) | Trench MOSFET with thick bottom oxide tub | |
TW201112398A (en) | High voltage MOSFET diode reverse recovery by minimizing P-body charges | |
US8129785B2 (en) | Semiconductor device | |
JP2008053397A (ja) | 半導体装置及びその製造方法 | |
TW201421683A (zh) | 具有低米勒電容之金氧半場效電晶體元件及其製作方法 | |
JP2005510088A (ja) | 多結晶シリコンソースコンタクト構造を有するトレンチ金属酸化膜半導体電界効果トランジスタデバイス | |
TW200834921A (en) | High withstand voltage trenched MOS transistor and manufacturing method thereof | |
JP7017733B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US6551937B2 (en) | Process for device using partial SOI | |
TW201248851A (en) | New and improved edge termination configurations for high voltage semiconductor power devices | |
TW201943081A (zh) | 半導體裝置及其製造方法 | |
CN109599399A (zh) | 在先进装置中用于增进装置效能的侧壁工程 | |
JP2007173379A (ja) | 半導体装置および半導体装置の製造方法 | |
JP5034151B2 (ja) | 半導体装置およびその製造方法 | |
JPH09321291A (ja) | 半導体装置 | |
KR100902585B1 (ko) | 트렌치 게이트형 모스트랜지스터 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MK4A | Expiration of patent term of an invention patent |