TW201421683A - 具有低米勒電容之金氧半場效電晶體元件及其製作方法 - Google Patents

具有低米勒電容之金氧半場效電晶體元件及其製作方法 Download PDF

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TW201421683A
TW201421683A TW101143944A TW101143944A TW201421683A TW 201421683 A TW201421683 A TW 201421683A TW 101143944 A TW101143944 A TW 101143944A TW 101143944 A TW101143944 A TW 101143944A TW 201421683 A TW201421683 A TW 201421683A
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epitaxial layer
gate trench
layer
gate
semiconductor device
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Yung-Fa Lin
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Anpec Electronics Corp
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Priority to CN201310012584.XA priority patent/CN103840000B/zh
Priority to US13/742,320 priority patent/US8969952B2/en
Publication of TW201421683A publication Critical patent/TW201421683A/zh

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Abstract

一種功率半導體元件，包含有一半導體基底，具有第一導電型；一磊晶層，位於該半導體基底上；一離子井，具有第二導電型，位於該磊晶層中，其中該離子井具有一接面深度；一閘極溝槽，位於該磊晶層中，且該閘極溝槽的深度大於該接面深度；一閘極氧化層，位於該閘極溝槽表面；一閘極，位於該閘極溝槽內；以及一口袋摻雜區，具有該第二導電型，位於該磊晶層中，緊鄰並至少覆蓋該閘極溝槽的轉角部分。

Description

具有低米勒電容之金氧半場效電晶體元件及其製作方法
本發明係有關於半導體元件技術領域，特別是有關於一種具有低米勒電容之金氧半場效電晶體(MOSFET)元件及其製作方法。
在傳統功率電晶體中，平面型功率元件(DMOS)因來自於通道區域(channel region)、聚集層(accumulation layer)以及接面場效電晶體(JFET)的貢獻，而使得導通電阻(on-resistance)上升。
為了降低上述區域之電阻，溝渠型功率元件(UMOS)於是被提出來，更因為UMOS結構不存在之JFET區域，因此可以縮小UMOS元件尺寸(cell size)以提高通道密度(channel density)，可以進一步降低導通電阻，但另一方面，UMOS元件也因其結構的關係導致閘汲間電容(米勒電容)上升而使得開關速度變慢。
因此，本發明之目的，即在提供一種溝渠型功率半導體元件及其製作方法，以降低米勒電容。
根據本發明之較佳實施例，本發明提供一種功率半導體元件，包含有一半導體基底，具有第一導電型；一磊晶層，位於該半導體基底上；一離子井，具有第二導電型，位於該磊晶層中，其中該離子井具有一接面深度；一閘極溝槽，位於該磊晶層中，且該閘極溝槽 的深度大於該接面深度；一閘極氧化層，位於該閘極溝槽表面；一閘極，位於該閘極溝槽內；以及一口袋摻雜區，具有該第二導電型，位於該磊晶層中，緊鄰並至少覆蓋該閘極溝槽的轉角部分。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
請參閱第1圖至第8圖，其為依據本發明一實施例所繪示的溝渠型功率電晶體元件之製造方法示意圖。首先，如第1圖所示，提供一半導體基底10，例如N型重摻雜之矽基底，其可作為電晶體元件的汲極(drain)。接著，利用一磊晶製程於半導體基底10上形成一磊晶層11，例如N型磊晶矽層。接著，可以在磊晶層11表面形成一墊層110，例如，矽氧墊層。
如第2圖所示，接著於磊晶層11上沈積一硬遮罩層120，例如氮化矽層，然後，利用光阻以及微影、蝕刻等製程，於硬遮罩層120中形成開口112。接著將光阻去除，然後，利用乾蝕刻製程，經由硬遮罩層120中的開口112，蝕刻磊晶層11至一預定深度，如此形成閘極溝槽122。閘極溝槽122包含有一底部122a、銜接底部122a的轉角部分122b，及垂直側壁122c。
如第3圖所示，接著可以進行一氧化製程，於閘極溝槽122表面形成一犧牲氧化層(圖未示)，再將此犧牲氧化層去除。然後，將硬遮罩層120以及墊層110去除，顯露出磊晶層11的主表面11a。
如第4圖所示，接著進行一熱氧化製程，於顯露出來的磊晶層11的表面以及閘極溝槽122的表面，包括底部122a、轉角部分122b及垂直側壁122c，形成一閘極氧化層18，接下來，進行一化學氣相沈積製程，全面沈積一多晶矽層(圖未示)，填滿閘極溝槽122。接著進行一蝕刻製程，將部分厚度的多晶矽層蝕除，顯露出閘極氧化層18，而剩下的多晶矽層則構成溝渠閘極20a。
接著，如第5圖所示，進行一離子佈植製程，於磊晶層11中形成一離子井210，例如P型井。然後，繼續進行一熱驅入製程，將植入磊晶層11中的摻質活化。根據本發明實施例，離子井210的接面深度小於閘極溝槽122的深度，換言之，閘極溝槽122的底部122a及轉角部分122b均位於磊晶層11中。根據本發明另一實施例，形成離子井210的離子佈植製程及熱驅入製程亦可以在閘極溝槽122形成之前進行。
如第6圖所示，利用微影製程及離子佈植製程，分別於磊晶層11表面形成一源極摻雜區22，例如N+源極摻雜區，以及於磊晶層11中在靠近閘極溝槽122的轉角部分122b形成一口袋摻雜區26，例如，P型摻雜區，其中，口袋摻雜區26可以橫跨離子井210與磊晶層11之接面，其至少覆蓋住閘極溝槽122的轉角部分122b，或者可以進一步延伸至閘極溝槽122的底部122a，如第9圖所示。如此即可降低米勒電容。
根據本發明實施例，口袋摻雜區26的佈植濃度大於磊晶層11的佈植濃度。根據本發明實施例，形成口袋摻雜區26的離子佈植製程係在形成源極摻雜區22的離子佈植製程之前進行者。根據本發明 實施例，在形成口袋摻雜區26及源極摻雜區22的離子佈植製程依序完成後，進行熱驅入製程，同時活化口袋摻雜區26及源極摻雜區22的摻質。
根據本發明實施例，形成口袋摻雜區26的離子佈植次數可以是單次或多次，能量可以介於200KeV至2MeV之間，而劑量可以介於1E11 atoms/cm2至1E14 atoms/cm2之間。
最後，如第7-8圖所示，進行接觸洞及金屬化製程，包括形成層間介電層30，於層間介電層30中以及磊晶層11表面蝕刻出一接觸洞230，於接觸洞230底部以離子佈植製程形成接觸摻雜區250，例如P+摻雜區，然後沈積阻障層32及金屬層34，並使金屬層34填滿接觸洞230，構成接觸件34a。本發明由於增加了口袋摻雜區26，使得垂直通道200可以延伸進入磊晶層11至接近閘極溝槽122的底部122a，進而降低了米勒電容。
請參閱第10圖至第14圖，其為依據本發明另一實施例所繪示的溝渠型功率電晶體元件之製造方法示意圖。首先，如第10圖所示，同樣先提供一半導體基底10，例如N型重摻雜之矽基底，其可作為電晶體元件的汲極。接著，利用一磊晶製程於半導體基底10上形成一磊晶層11，例如N型磊晶矽層。接著，可以在磊晶層11表面形成一墊層110，例如，矽氧墊層。接著，進行一離子佈植製程，於磊晶層11中形成一離子井210，例如P型井。然後，繼續進行一熱驅入製程，將植入磊晶層11中的摻質活化。根據本發明實施例，離子井210的接面深度小於閘極溝槽122的深度，換言之，閘極溝槽122的底部122a及轉角部分122b均位於磊晶層11中。
如第11圖所示，接著於磊晶層11上沈積一硬遮罩層120，例如氮化矽層，然後，利用光阻以及微影、蝕刻等製程，於硬遮罩層12中形成開口112。接著將光阻去除，然後，利用乾蝕刻製程，經由硬遮罩層12中的開口112，蝕刻磊晶層11至一預定深度，如此形成閘極溝槽122。閘極溝槽122包含有一底部122a、銜接底部122a的轉角部分122b，及垂直側壁122c。
接著，進行離子佈植製程，例如斜角度離子佈植製程，經由閘極溝槽122，於磊晶層11中在靠近閘極溝槽122的轉角部分122b形成一口袋摻雜區26，例如，P型摻雜區，其中，口袋摻雜區26可以橫跨離子井210與磊晶層11之接面，其至少覆蓋住閘極溝槽122的轉角部分122b。根據本發明實施例，口袋摻雜區26的佈植濃度需大於磊晶層11的佈植濃度。根據本發明實施例，形成口袋摻雜區26的離子佈植次數可以是單次或多次，能量可以介於200KeV至2MeV之間，而劑量可以介於1E11 atoms/cm2至1E14 atoms/cm2之間。
如第12圖所示，接著可以進行一氧化製程，於閘極溝槽122表面形成一犧牲氧化層(圖未示)，再將此犧牲氧化層去除。然後，將硬遮罩層120以及墊層110去除，顯露出磊晶層11的主表面11a。
如第13圖所示，接著進行一熱氧化製程，於顯露出來的磊晶層11的表面以及閘極溝槽122的表面，包括底部122a、轉角部分122b及垂直側壁122c，形成一閘極氧化層18，接下來，進行一化學氣相沈積製程，全面沈積一多晶矽層(圖未示)，填滿閘極溝槽122。接著進行一蝕刻製程，將部分厚度的多晶矽層蝕除，顯露出閘極氧化層 18，而剩下的多晶矽層則構成溝渠閘極20a。
如第14圖所示，利用微影製程及離子佈植製程，於磊晶層11表面形成一源極摻雜區22，例如N+源極摻雜區。然後，可以進行熱驅入製程，同時活化口袋摻雜區26及源極摻雜區22的摻質。
最後，進行接觸洞及金屬化製程(步驟同第7-8圖)，包括形成層間介電層30，於層間介電層30中以及磊晶層11表面蝕刻出一接觸洞230，於接觸洞230底部以離子佈植製程形成接觸摻雜區250，例如P+摻雜區，然後沈積阻障層32及金屬層34，並使金屬層34填滿接觸洞230，構成接觸件34a。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧半導體基底
11‧‧‧磊晶層
11a‧‧‧主表面
18‧‧‧閘極氧化層
20a‧‧‧閘極
22‧‧‧源極摻雜區
26‧‧‧口袋摻雜區
30‧‧‧層間介電層
32‧‧‧阻障層
34‧‧‧金屬層
34a‧‧‧接觸件
110‧‧‧墊層
112‧‧‧開口
120‧‧‧硬遮罩層
122‧‧‧閘極溝槽
122a‧‧‧底部
122b‧‧‧轉角部分
122c‧‧‧垂直側壁
210‧‧‧離子井
230‧‧‧接觸洞
250‧‧‧接觸摻雜區
第1圖至第8圖為依據本發明一實施例所繪示的溝渠型功率電晶體元件之製造方法示意圖。
第9圖例示口袋摻雜區進一步延伸至閘極溝槽的底部的示意圖。
第10圖至第14圖為依據本發明另一實施例所繪示的溝渠型功率電晶體元件之製造方法示意圖。
10‧‧‧半導體基底
11‧‧‧磊晶層
18‧‧‧閘極氧化層
20a‧‧‧閘極
22‧‧‧源極摻雜區
26‧‧‧口袋摻雜區
122a‧‧‧底部
122b‧‧‧轉角部分
122c‧‧‧垂直側壁
210‧‧‧離子井

Claims (8)

  1. 一種功率半導體元件，包含有：一半導體基底，具有第一導電型；一磊晶層，位於該半導體基底上；一離子井，具有第二導電型，位於該磊晶層中，其中該離子井具有一接面深度；一閘極溝槽，位於該磊晶層中，且該閘極溝槽的深度大於該接面深度；一閘極氧化層，位於該閘極溝槽表面；一閘極，位於該閘極溝槽內；以及一口袋摻雜區，具有該第二導電型，位於該磊晶層中，緊鄰並至少覆蓋該閘極溝槽的轉角部分。
  2. 如申請專利範圍第1項所述之功率半導體元件，其中另包含有一源極摻雜區，位於該磊晶層表面並緊鄰該閘極溝槽。
  3. 如申請專利範圍第2項所述之功率半導體元件，其中該源極摻雜區具有該第一導電型。
  4. 如申請專利範圍第1項所述之功率半導體元件，其中該第一導電型為N型，該第二導電型為P型。
  5. 如申請專利範圍第1項所述之功率半導體元件，其中該磊晶層具有該第一導電型。
  6. 如申請專利範圍第1項所述之功率半導體元件，其中該口袋摻雜區橫跨該離子井與該磊晶層之接面。
  7. 如申請專利範圍第1項所述之功率半導體元件，其中該口袋摻雜區的佈植濃度大於該磊晶層的佈植濃度。
  8. 如申請專利範圍第1項所述之功率半導體元件，其中該口袋摻雜區延伸至該閘極溝槽的底部。
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