CN1447982A - 功率mosfet及利用自对准体注入制作其的方法 - Google Patents
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Abstract
一种制造功率MOSFET的方法,该方法包括:在半导体层内制作一个沟槽,制作用于排列沟槽的栅极绝缘层,在沟槽的下部制作一个栅极导电层,然后制作用于填充沟槽之上部的绝缘层。去除绝缘层侧面附近的半导体层部分,从而其上部从半导体层向外延伸。在向外延伸的绝缘层上部的侧面附近制作隔层,使用隔层作为用于限定源/体接触区域的自对准掩模。
Description
有关申请
本申请基于申请日期为2000年7月20日,申请号为60/219,858的在先未决临时申请,这里全文引用其公开作为参考。
技术领域
本发明涉及半导体领域,更确切地说,涉及利用沟槽作为栅极(以沟槽作为栅极的)功率MOSFET。
背景技术
电子行业已经表现出对具有低接通电阻(RDSon)、大旁路电压(VDSBR)、低栅极电荷和足够强度的小型离散功率MOSFET的大量需求。强度限定设备的安全工作区域(SOA)和松开电感转换(UIS)。通过最优组合以上特性,能够获得非常低的开态功率损耗以及开关损耗,导致诸如DC-DC转换器之类的***中高功率转换效率。
为了满足以上需求,人们开发出超密度利用沟槽作为栅极功率MOSFET技术。通过减少元件节距,即,通过减少功率MOSFET的尺寸,在每平方面积的硅片上制作更多功率MOSFET,实现比较低的接通电阻。但是通常会降低设备强度。为了解决负面影响,必须设计具有缩减元件节距的设备,以便在灾难故障出现前承受更多能量(包括DC和动态耗散功率)。
以下参照图1-3说明利用沟槽作为栅极功率MOSFET技术的基本概念。图1表示常规利用沟槽作为栅极功率MOSFET 10。栅极12位于沟槽14内,在P阱16内制作沟槽14。至于制作源/体接触区域18,对应蚀刻掩模必须对准沟槽14。源电极22和栅极氧化层24之间的介电层20覆盖N+源区域26的平面的一部分。根据最大栅极-源额定值,确定覆盖N+源区域26的介电层20的尺寸。因此,常规结构的最小元件节距受源/体接触掩模非准直公差和表面介电层20占据的间隔的限制。
通过使用图2和图3所示的沟槽技术,消除以上限制。在由此生成的设备结构28中,将栅极12凹下到沟槽14内,从而保留对介电层20足够大的凹槽区域。根据最大栅极-源额定值,确定凹槽区域的深度,其深度确定介电层20的最终厚度。在淀积介电层20后,通过使用硅平面32作为终点进行深蚀刻。
与图1所示的常规利用沟槽作为栅极功率MOSFET 10相比,设备28提供更高的通道密度。图3a和3b分别表示图2中3a和3b标记的不同位置的设备28的截面图。为了在不需要源/体接触蚀刻掩模工序的情况下制作具有超小元件节距的设备28,截断P+源/体接触区域18,并且沿N+条周期放置P+源/体接触区域18,其中完全去除N+源区域26。
不幸的是,周期放置P+源/体接触区域18将增加设备28的接通电阻,以及基极电阻和寄生BJT的共基极电流增益。寄生BJT是由N+源区域26、P阱16和N外延层9组成的。因此,将以非常低的电流打开寄生BJT,导致较差的SOA和较低的UIS能力。
发明内容
考虑到上述背景,本发明的目的在于提供一种具有较低接通电阻的利用沟槽作为栅极功率MOSFET,以及制作此类MOSFET的方法。
本发明的另一目的在于,在不降低设备强度的情况下提供利用沟槽作为栅极功率MOSFET。
利用制作功率MOSFET的方法,提供根据本发明之上述和其他优点、特征和目的,该方法包括:在半导体层制作一个沟槽,制作用于排列沟槽的栅极绝缘层,在沟槽的下部制作一个栅极导电层,以及制作用于填充沟槽上部的绝缘层。
该方法最好还包括:去除绝缘层侧面附近的半导体层部分,从而其上部从半导体层向外延伸。最好在向外延伸的绝缘层上部之侧面附近制作隔层,并且最好使用隔层作为限定源/体接触区域的自对准掩模。
在不降低设备强度的情况下,利用较低的接通电阻,制作由此合成的利用沟槽作为栅极功率MOSFET。由于每个MOSFET均具有一个源/体接触区域,所以能够降低接通电阻。源/体接触区域提供MOSFET之源和体区域之间的有效短路。因此,能够增加设备强度。
另外,通过把绝缘层完全做在沟槽内来降低功率MOSFET的元件节距,所以能够降低接通电阻。换句话说,绝缘层不在源区域的表面上,从而能够将源区域和源电极之间的接触区域减到最小程度。
降低功率MOSFET之接通电阻和元件节距的另一个因素是使用隔层作为自对准掩模的结果,其中自对准掩模用于将搀杂物注入体区域,以便限定源/体接触区域。由于隔层利用向外延伸的绝缘层进行自对准,所以能够避免源/体接触掩模的非准直公差。
本发明的另一种实施方式使用隔层作为自对准掩模,以便在限定源/体接触区域前,去除未被隔层覆盖的半导体层的一部分。通过去除一部分半导体层,只需较低能级注入制作源/体接触区域的搀杂物。
另外,由于去除了一部分半导体层,所以可以在半导体层内的更深位置制作源/体接触区域。这能降低基极电阻以及寄生BJT的共基极电流增益,从而提高设备强度,即,增加安全工作范围(SOA)和功率MOSFET的松开电感转换(UIS)。
半导体层的去除部分的厚度小于等于1微米。栅极导电层凹下在沟槽内,距其开口约0.2至0.8微米。例如,制作的功率MOSFET的元件节距约为0.5微米。利用沟槽作为栅极功率MOSFET或者为n通道或者为p通道功率MOSFET。
本发明的另一方面在于一种MOSFET,包括其内具有沟槽的半导体层,排列沟槽的栅极绝缘层以及位于沟槽下部的栅极导电层。MOSFET最好还包括位于沟槽上部并从半导体层向外延伸的绝缘层。源区域最好与向外延伸的绝缘层相邻,而源/体接触区域最好从侧面与栅极导电层隔开。
功率MOSFET的另一种实施方式与源区域有关,其中源区域的一部分包括位于源/体接触区域之上的凹槽。在另一种实施方式中,源区域包括用于暴露体区域的一个开口,从而源电极与源/体接触区域之间相连。
附图说明
图1表示根据现有技术的常规利用沟槽作为栅极功率MOSFET。
图2表示利用根据现有技术之沟槽技术制作的利用沟槽作为栅极功率MOSFET的上平面视图。
图3a和3b表示分别沿线段3a和3b拍摄的图2所示的利用沟槽作为栅极功率MOSFET的截面图。
图4是一个流程图,表示根据本发明制作利用沟槽作为栅极功率MOSFET的方法。
图5-13为表示根据本发明之工序的利用沟槽作为栅极功率MOSFET的一部分的截面图。
图14-15为相邻利用沟槽作为栅极功率MOSFET的之一部分的截面图,表示基于根据本发明之源/体接触区域之深度的雪崩击穿电流的通路。
具体实施方式
以下参照表示本发明之最佳实施方式的附图,更彻底地说明本发明。然而,可以采用多种不同方式实现本发明,并且本发明并不限于本文阐述的实施方式。提供各种实施方式的目的是使得本公开既详尽又完整,并向熟练技术人员完整表达本发明的范围。相同参考号数指相同元件。为了更加清晰,可以放大附图中各层以及各区域的尺寸。
现在参照图4,该图表示用于制造根据本发明之利用沟槽作为栅极功率MOSFET的方法。开始时(块40),在块42中,在半导体层上形成一个沟槽,在块44中,形成一个栅极绝缘层,以排列沟槽。在块46中,在沟槽的下部形成一个栅极导电层。在块48中,形成一个绝缘层,以填充沟槽的上部。
该方法还包括:在块50中,去除绝缘层侧面附近的半导体层部分,从而其上部从半导体层开始向外延伸。在块52中,在向外延伸的绝缘层上部的侧面附近,形成隔层,并且在块54中,利用隔层作为限定源/体接触区域的自对准掩模。
根据本发明之方法能够提供高密度功率MOSFET,其中源/体接触区域是采用使用隔层的自对准方式形成的。由于隔层与向外延伸的绝缘层是自对准的,所以功率MOSFET的最小元件节距不受源/体接触掩模非准直公差的限制。
另外,由于各MOSFET均具有源/体接触区域,所以能够降低接通电阻。这有助于降低基极电阻和寄生BJT的共基极电流增益。将以较高电流接通寄生BJT,导致经过改良的SOA和更高的UIS能力。
另外,通过把绝缘层完全做在沟槽内来降低功率MOSFET的元件节距,所以能够降低接通电阻。换句话说,绝缘层不在源区域的表面上,从而能够将源区域和源电极之间的接触区域减到最小程度。
以下参照图5-13说明用于制造根据本发明之利用沟槽作为栅极功率MOSFET的工序。正如熟练技术人员能够理解的那样,尽管在附图中举例说明n通道MOSFET 70,但是该工序同样适用于制造p通道功率MOSFET。
在半导体基底8上制造n型外延层9。半导体基底8也是n型,并且最好为硅。正如熟练技术人员理解的那样,外延层承受功率MOSFET 70之漏极到源的击穿电压。
焊盘氧化层72被生长在外延层9上,然后是p型掺杂物注入,以构成功率MOSFET 70的p阱或体区域16。例如,利用1E13/cm2至5E14/cm2范围内的剂量,以及40至200keV范围内的能级,注入p型掺杂物,如硼。
在焊盘氧化层72的表面上制作掩模74,以限定沟槽14。例如,掩模74可以为低温氧化层。正如图5所示,对体区域16和外延层9进行蚀刻,以形成沟槽14。然后去掉掩模74。
栅极绝缘层24被生长在沟槽14的侧壁和底面上,以及体区域16的表面上。栅极绝缘层24的厚度在10至100nm的范围内。正如图6所示,在沟槽14内部和栅极绝缘层24的表面上,淀积诸如多晶硅之类的导电材料25。
现在参照图7,去掉p阱16表面的多晶硅25,并在沟槽14内进行深蚀刻,以便在功率MOSFET 70之沟槽14的下部限定凹下栅极12。凹下在沟槽14内的栅极12的深度在距离沟槽开口0.2至0.8微米的范围内。
在栅极绝缘层24的表面和栅极12的表面上,淀积绝缘层76。绝缘层76用于隔离栅极12。正如图8所示,去掉表面绝缘层76,并且平整体区域16的上表面以及沟槽14内的介电层20的上表面。
在平整体区域16的上表面以及沟槽14内的介电层20的上表面之后,将n型搀杂物注入到绝缘层附近的体区域16中,以限定功率MOSFET 70的源区域26。例如,利用2E15/cm2至2E16/cm2范围内的剂量,以及40至200keV范围内的能级,注入诸如砷或磷之类的n型掺杂物。然后在900至1,100℃的温度范围内进行退火。
正如图9所示,去掉绝缘层侧面附近的表面部分,从而介电层20的一部分向外延伸。被去掉的表面部分的厚度在0.1至1微米的范围内。正如下面详细说明的那样,向外延伸的介电层20能够制作自对准隔层。
由于在蚀刻表面层时能够减少源区域26的搀杂物浓度,所以可以执行另一个源注入,以增强源区域的掺杂浓度。可以利用上面讨论的相同剂量和能级,实现这种增强。作为所公开工序的一种选择,也可以在去掉绝缘层侧面附近的表面部分后,注入限定源区域26的n型搀杂物,以限定向外延伸的介电层20。此时,限定源区域26只需要进行一次注入。
然后在介电层20和源区域26上进行氮化物淀积。正如图10所示,蚀刻氮化物淀积,以制作隔层80。
通过使用隔层80作为自对准掩模,将p型搀杂物注入到体区域16中,以限定源/体接触区域82。以高能级注入诸如硼之类的搀杂物,以穿透源区域26。例如,利用2E15/cm2至2E16/cm2范围内的剂量,以及120至400keV范围内的能级,注入硼。然后在900至1100℃的温度范围内进行退火。
去掉隔层80,然后在源区域26上制作源电极84。该方法还包括:在源电极84和源/体接触区域82之间形成至少一个导电通路86。漏极在基底8的下面。
源/体接触区域82在体区域16和源区域26之间保持连续接触。换句话说,每个功率MOSFET均包括一个源/体接触区域82。这有助于降低功率MOSFET 70的接通电阻。也有助于降低基极电阻以及寄生BJT的共基极电流增益。以较高电流接通寄生BJT,导致经过改良的SOA以及更高的UIS能力。
另外,通过把介电层20完全做在沟槽14内,来降低功率MOSFET70的元件节距,所以能够降低接通电阻。换句话说,介电层20不在源区域26的表面上,从而能够将源区域和源电极84之间的接触区域减到最小程度。因此,体区域16、栅极12、源区域26和源/体接触区域82限定了约为0.5微米的元件节距。
假如使用隔层80作为去除未被该隔层覆盖的源区域26之一部分的自对准掩模,则可以使用低能级而不是高能级来注入限定源/体接触区域82的搀杂物。正如图12说明的那样,已经去除了未被隔层80覆盖的源区域26的一部分。利用参考号数70′表示该功率MOSFET 70。
去除源区域26之一部分的优点在于,能够利用低能级限定源/体接触区域82。例如,利用2E15/cm2至2E16/cm2范围内的剂量,以及40至120keV范围内的能级,注入诸如硼之类的p型搀杂物。正如上面说明的那样,在900至1,100℃的温度范围内进行退火。在图12中,利用参考号数70′表示该功率MOSFET。
作为另一种实施方式,完全去除未被隔层80覆盖的源区域26的所有部分。在利用低能级限定源/体接触区域82之后,源电极84与接触区域直接相连。在图13中,利用参考号数70″表示该功率MOSFET。
去除未被隔层80覆盖的源区域26的所有部分,以及体区域16下面之部分区域的优点在于,可以在体区域16内的更深位置制作源/体接触区域82。从而能够降低寄生BJT的共基极电流增益,这有助于提高设备强度,即,增加安全工作范围(SOA)并提高功率MOSFET的未钳位电感切换(UIS)。
正如图14和15所示,源/体接触区域82的深度还影响雪崩击穿电流的通道。例如,正如图14所示,当利用隔层80蚀刻源区域26,从而进入深度为0.5微米的体区域16时,模拟雪崩击穿电流90在到达源/体接触区域82之前,流动到沟槽14的下部。这相当于39.67V的旁路电压(VDSBR)。
然而,正如图15所示,通过将蚀刻深度提高到0.8微米,模拟雪崩击穿电流90具有较短的流动通道,由于该电流不会流动到沟槽14的下部。这相当于36.75V的旁路电压(VDSBR)。因此,图15所示的利用沟槽作为栅极功率MOSFET设备比图14所示的设备更坚固。
本发明的另一方面在于按照以上公开的工序结果制作的功率MOSFET 70。功率MOSFET 70包括其内具有沟槽14的半导体层8、9,衬在沟槽上的栅极绝缘层24,以及沟槽下部的栅极导电层12。
介电层20位于沟槽14的上部,并且从半导体层8、9向外延伸。源区域26与向外延伸的介电层20相邻,并且源/体接触区域82从侧面与栅极导电层12隔离。
正如图12表示的那样,功率MOSFET 70′的另一种实施方式与源区域26有关,其中源区域的一部分包括位于源/体接触区域上面的一个凹槽。正如图13表示的那样,在功率MOSFET 70″的另一种实施方式中,源区域26包括用于暴露体区域16的一个开口,从而源电极84与源/体接触区域82直接相连。
根据上述说明以及关联附图中展示的教导,本领域的技术人员可以对本发明做出许多修改和其他实施方式。因此,可以理解,本发明并不限于所公开的特定实施方式,并且所附的权利要求书也包括上述修改和其他实施方式。
Claims (31)
1.一种形成MOSFET的方法,包括:
在半导体层上形成一个沟槽;
形成衬在该沟槽上的栅极介电层;
在沟槽的下部形成一个栅极导电层;
形成用于填充沟槽的上部的一个介电层;
去除与介电层横向相邻的半导体层部分,从而使其上部从半导体层向外延伸;
形成与向外延伸的介电层上部横向相邻的隔层;以及
使用该隔层作为限定源/体接触区域的自对准掩模。
2.根据权利要求1的方法,其中使用隔层作为自对准掩模包括注入用于限定源/体接触区域的搀杂物。
3.根据权利要求1的方法,其中使用隔层作为自对准掩模包括蚀刻未被隔层覆盖的半导体层。
4.根据权利要求3的方法,其中蚀刻被进行到与半导体层之表面的距离小于或等于1微米的深度。
5.根据权利要求1的方法,还包括:在形成隔层前,在与向外延伸的介电层相邻的半导体层中形成源区域。
6.根据权利要求1的方法,还包括:在源区域和介电层上形成源电极。
7.根据权利要求6的方法,还包括:在源电极和源/体接触区域之间形成至少一条导电通路。
8.根据权利要求5的方法,还包括:在源区域、介电层和源/体接触区域上形成一个源电极。
9.根据权利要求1的方法,还包括:去除隔层。
10.根据权利要求1的方法,其中去除半导体层的部分的处理被进行到与其表面的距离小于等于1微米的深度。
11.根据权利要求1的方法,其中将栅极导电层置于沟槽内距其开口的约为0.2至0.8微米的范围内。
12.根据权利要求1的方法,还包括:在沟槽附近的半导体层中形成一个体。
13.一种用于形成MOSFET的方法,该方法包括:
在半导体层上形成一个沟槽;
形成衬在沟槽上的栅极介电层;
在沟槽的下部形成一个栅极导电层;
形成用于填充沟槽上部的介电层;
去除与介电层横向相邻的半导体层部分,从而使其上部从半导体层向外延伸;
形成与介电层的该向外延伸的上部横向地相邻的隔层;
使用隔层作为自对准掩模,蚀刻未被隔层覆盖的半导体层;以及
使用隔层作为自对准掩模,注入用于限定源/体接触区域的搀杂物。
14.根据权利要求13的方法,其中蚀刻被进行到与半导体层之表面的距离小于等于1微米的深度。
15.根据权利要求13的方法,还包括:在形成隔层前,在与向外延伸的介电层相邻的半导体层中形成源区域。
16.根据权利要求15的方法,还包括:在源区域和介电层上形成源电极。
17.根据权利要求16的方法,还包括:在源电极和源/体接触区域之间形成至少一条导电通路。
18.根据权利要求15的方法,还包括:在源区域、介电层和源/体接触区域上形成一个源电极。
19.根据权利要求13的方法,还包括:去除隔层。
20.根据权利要求13的方法,其中去除半导体层的部分的处理被进行到与其表面的距离小于等于1微米的深度。
21.根据权利要求13的方法,其中栅极导电层被置于沟槽内与其开口的距离约为0.2至0.8微米的范围内。
22.根据权利要求13的方法,还包括:在沟槽附近的半导体层中形成一个体区域。
23.一种MOSFET,包括:
其中具有沟槽的半导体层;
衬在列沟槽上的栅极介电层;
位于沟槽下部的栅极导电层;
位于沟槽上部并从所述半导体层向外延伸的介电层;
与向外延伸的介电层相邻的源区域;以及
沿横向与所述栅极导电层隔开的源/体接触区域。
24.根据权利要求23的MOSFET,还包括:位于所述源区域和所述介电层上的源电极。
25.根据权利要求24的MOSFET,还包括:在所述源电极和所述源/体接触区域之间的至少一条导电通道。
26.根据权利要求23的MOSFET,其中所述源区域的一部分包括所述源/体接触区域上的一个凹下部分。
27.根据权利要求23的MOSFET,其中所述源区域的一部分包括用于暴露所述源/体接触区域的一个开口;并且还包括位于所述源区域、所述介电层和所述源/体接触区域上的一个源电极。
28.根据权利要求23的MOSFET,其中所述向外延伸的介电层从所述源区域延伸小于等于1微米的距离。
29.根据权利要求23的MOSFET,其中在栅极被置于沟槽内与其开口的距离约为0.2至0.8微米的范围内。
30.根据权利要求23的MOSFET,其中所述源/体接触区域被置于所述源区域附近的所述半导体层中。
31.根据权利要求30的MOSFET,其中凹槽的一个上表面与半导体层之上表面的距离小于等于1微米。
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- 2001-07-18 WO PCT/US2001/022575 patent/WO2002009177A2/en active Application Filing
- 2001-07-18 AU AU2001276969A patent/AU2001276969A1/en not_active Abandoned
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- 2001-07-18 JP JP2002514783A patent/JP3954493B2/ja not_active Expired - Fee Related
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CN105097543A (zh) * | 2014-05-23 | 2015-11-25 | 北大方正集团有限公司 | 一种沟槽型vdmos器件及其制造方法 |
CN105990434A (zh) * | 2014-09-12 | 2016-10-05 | 株式会社东芝 | 半导体装置及其制造方法 |
CN105529256A (zh) * | 2014-10-21 | 2016-04-27 | 英飞凌科技奥地利有限公司 | 半导体器件和使用对准层制造半导体器件的方法 |
CN105529256B (zh) * | 2014-10-21 | 2018-07-17 | 英飞凌科技奥地利有限公司 | 半导体器件和使用对准层制造半导体器件的方法 |
US10903321B2 (en) | 2014-10-21 | 2021-01-26 | Infineon Technologies Austria Ag | Semiconductor device and method of manufacturing a semiconductor device using an alignment layer |
US11699725B2 (en) | 2014-10-21 | 2023-07-11 | Infineon Technologies Austria Ag | Semiconductor device having an alignment layer with mask pits |
Also Published As
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JP2004515907A (ja) | 2004-05-27 |
CN1211844C (zh) | 2005-07-20 |
US6921939B2 (en) | 2005-07-26 |
TW498429B (en) | 2002-08-11 |
US20050184318A1 (en) | 2005-08-25 |
WO2002009177A2 (en) | 2002-01-31 |
US7501323B2 (en) | 2009-03-10 |
US20020008284A1 (en) | 2002-01-24 |
DE10196441B4 (de) | 2009-10-22 |
JP3954493B2 (ja) | 2007-08-08 |
AU2001276969A1 (en) | 2002-02-05 |
DE10196441T1 (de) | 2003-07-17 |
WO2002009177A3 (en) | 2002-06-13 |
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