TW312844B - - Google Patents

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Publication number
TW312844B
TW312844B TW085102110A TW85102110A TW312844B TW 312844 B TW312844 B TW 312844B TW 085102110 A TW085102110 A TW 085102110A TW 85102110 A TW85102110 A TW 85102110A TW 312844 B TW312844 B TW 312844B
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TW
Taiwan
Prior art keywords
carrier
item
patent application
module
integrated circuit
Prior art date
Application number
TW085102110A
Other languages
English (en)
Inventor
Manabu Bonkohara
Original Assignee
Nippon Electric Co
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=12476134&utm_source=***_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TW312844(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Nippon Electric Co filed Critical Nippon Electric Co
Application granted granted Critical
Publication of TW312844B publication Critical patent/TW312844B/zh

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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Description

A7 _B7_ 五、發明説明（，） 兹明背署 本發明像有鼷一種將大型積醞電路（LSI)安裝於其上 的半導體封裝及其封裝的方法。更具體而言，本發明傷 有鬭一種將大型積醱電路晶Η以三度空間方式高密度地 • ______ —— 堆叠的半導體封裝堆疊模组及其製造方法。 半導髅封裝有各式各樣的堆叠模組結構，已知.之製造 方法如下所述。. (1) TSOPs{薄小外引線封裝）或類拟造模的封裝是經由 延伸出封裝外的引線堆叠建接在一起（習用技術1)。 (2) 直接將大型積醱電路晶Η堆璺在一起（習用技術2)β 此種技術镍利用導線作接合，因此晶Η的周圍提供了適 合連接的形態。這些晶Η被裝配在一糎蓮載基板上，且 藉由導線和連接至基扳。 (3) 晶片缛由TAB的連接堆叠的模組形態中（習知技術3) 。在這値情形下，TAB導線幫曲地接到蓮載基底上β (4) 在堆璺中，經由TAB連接在一起的半導體元件連接 到引線框的島狀物上，而由樹脂密裝整饀總成 < 習知技 術4>。 經濟部中央揉率局I·工消费合作社印製 (5) 在日本專利特許公開No.6卜101067中提及一種記 億體楔組結構（習用技術5 )。明確地說，記億體積鱧電路 被安裝在陶瓷封裝中，而陶瓷封裝中有一俱空腔以及連 接稹體電路和晶Η載體用的霄極。連接晶Μ載體用的® 極由金屬的薄導線電氣連接到積醱電路的電極上，然後 用樹脂密封起來。許多數在其周函有將電搔導引到外部 本紙張尺度適用中國國家標準（CNS ) A4规格（210X2.97公釐） 312844 A7 B7 五、發明説明（ 用之電極蘭案的載醴被堆昼起來，之後再將那些電極画 案彼此電氣連接。載體是經由載體容器的外壁連接，而 晶片是經由線焊連接的。 (6)在日本專利特許公開Ho.2-310957中提及一種具習 知造模封裝之半導髏元件在其相對的兩面（頂和底面）上 提供以引線（習用技術6)。許多數此種半導體元件藉由 引線而堆叠和連接起來。 U)用於堆昼連接的金靨藉由橄影像、氣化、金颶形 成的程序或類似的技術形成於半導體元件表面的邊緣上。 (8) —種以一多尖端形態蓮載記憶體半導體元件的QFP 正在量産中β此種QFPs藉由QFPs本身的引線堆疊與連接 —起。 (9) 習知積體電路封裝藉由一値母板和數個子板堆叠 與連接一起。 請 先 閲 背 面 之 注 意 事 項 再 養 題 問 的 列 下 有 具 術 技 用 習 .述 上 習 的 度 程 當 相 有 具 裝 封 個 每 於 在 點 的 1 術 接 .1 線 導 由 藉 像 〇 Η 小 晶縮 於易 由.不 0 於 厚至 過以 組大 模太 锢態 整形 成模 造造 ，其 度致 厚導 經濟部中央橾準局I-工消费合作社印裝 是 於 來 起 接 的 値 個 1 Η 晶 將 須 必 2 術 加 增 的 本 成 造 製 和 間 時 造 0 Ms 成 造 是 的« .CM 堆 於 由 外 無的 則片 否晶 成接 完連 裝線 組電· 組.供 模為 個 ， 整者 非再 除 O P 成試過 造測削 ，行切 H進器 晶3：機 的晶用 露別須 裸痼必 始對緣 原法邊 試 測 行 進 X 晶 B A T 的 別 個 對 以 可 3 術 技 用 習 然 郵 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 312844 A7 B7
央 橾 率 局 工 消 費 合 作 社 印 装 五、發明説明（々） 一値痼地安裝晶Μ卻增加了成本，此外還造成一锢體積 龐大的模组由於TAB晶片堆昼在一起的高度tb —般QFP 封裝還來的高，所以不可能做到高密度的封裝》再者， TAB造成包括安裝在内的多種的處理方式不易實行。 <4)習用技術4之成本高昂，此外由於使用ΪΑΒ連接， 因而需要堅固的半導體元件，所以半導體元件必須有相 當的厚度，而其.厚度絶對不能低於0.3mii (毫米）。因此 ，整個QFP封裝在厚度上無法縮減。 (5)習用技術5同樣依賴導線連接，再加上放置載體 的容器經由自己的外壁去連接，造成模組體積的增大和 導線長度的增長。此外，由於各晶Η載體的厚度比堆畳 前個別的半導體元件的厚度多了好幾倍，所以這個模組 不適合作高密度的封裝。再者，以多级的方式連接半導 體元件更進一步地降低了封裝的密度。 (6 )習用技術6將造模樹脂中的半導體元件以傾斜位 置配置著。因此造模的厚度比半導體元件和引線框的總 厚度要多出數倍，所以並不利於高密度的封裝。而以多 级的方式連接此種的半導體元件更進一步地降低了封装 的密度。 (7) 習用技術7在技術上不易實行，而且需要騖人的 設備的投資額。 (8) 習用技術8由於個別的QFP封裝比半導體元件厚了 好幾倍，亦不適用於^密度封裝。而且以多鈒的方式連 接封裝更進一步地降低了封裝的密度。 請 先 閲 背 之 注 意 事 項 再
A 者 裝
本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） A7 B7 _ 五、發明説明（（） (9 )習用技術9只是彳夺具有習知厚度的積體電路封裝以 多级的方式接在一起，所以在增高封裝密度上不符要求 »此外，母板和子板也進一步地降低了封裝的密度。 發明槪沭 本發明之目的即在^^供一需要最短的導線長度、達到 所需的電子待性之又小、又薄、密度又高、成本低廉而 且可靠的半導體封裝堆叠模組，以及其製造方法。 根據本發明，一種半導體封裝具有（：）一 Μ載體；貫 穿，其在載體上或在載體末端面形成；一導體懦案，其 至少在載體的正面的形成；内部連接用的襯墊，其在載 體的背面形成而且以可導電的方式連接到該等貫穿孔； 以及一値大型積體電路晶Η,藉由襯墊和載體接著在一 起。 經濟部中央樣準局贫工消费合作社印策 此外，根據本發明，在一具有許多載體堆昼在一起之 半導體封裝模組中，各値載體具有：貫穿孔，其在載體 上或在載體末端面形成；一導體圖案，其至少在載體的 正面形成；内部連接用的襯墊，其在載體的背面形成而 且以可導電的方式連接到該等貫穿孔；以及一大型積體 電路晶片由襯墊和載體接著在一起。載體經由該等貫穿 孔三度空間地連接在一起。 另外，依照本發明，一種製造半導體堆蠱模組的方法 中具有一個連接一陶瓷蓮載基底和一大型積醴電路晶Η 的步驟，這橱步驟僳關於在各自有***物的陶瓷蓮載基 底和大型積體電路晶Η之間注入密封用的樹脂，經由抛 本紙張尺度適用中國國家標隼（CNS ) Α4規格（210X297公釐） 經濟部中央梂準局I·工消費合作社印裝 A7 _ B7_ 五、發明説明（r ) 光、碾磨、表面碾磨或蝕刻的方法來減少大型積體電路 晶Η連接到陶瓷蓮載基底的厚度，以及堆疊輿焊接各載 有大型積體電路晶Η的許多數陶瓷蓮載基底的方法。 此外，依據本發明，在一半導體堆《模組中，一種由 互不分離的許多數載體組成的多載體本體較為容易進行 連接大型積體電路晶片，經由***物連接大型積體電路 晶Η和載體、以樹脂密封、打薄、燒線測試、多级連接 、電性测試等步驟，之後才以雷射、銘刻標記、切片或碎開 (c h 〇 c 〇 - b r a k i n g )之一的方式分離。 附圖簡沭 本發明上述及其他目的、特黏及優黠可由下文配合附 圖的詳細說明而呈更易了解，其中： 圖1和圖2分別顯示一特別之習知半導體封裝堆鲞模 組； 漏3 A到圖3 C顯示根據本發明之半導體封裝堆簦模組之 第一和第二較佳實施例； 圖4纟到_4£顯示製造如圖3A到圖3C中所顯示之模組之 流程步驟； 圖5A到圖5D顯示本發明之第三和第四較佳實施例； 圖6顯示本發明之第五較佳實施例； ' 圖7A到圖7D顯示製造第五較佳實施例之模组之流程步 驟》 圖8顯示本發明之第六較佳實施例； 第9 A到圖9C顯示本發明之第七較佳實施例； 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -裝. 丁 -番 312844 Α7 Α7 Β7 五、發明説明（心 第10 A到圖10 B顯示本發明 第11A到鼷1 1B顯示本發明 第12顯示本發明之第十較 圖13A和圖13B顯示本發明 較隹奮掄例銳明 為更進一步地瞭解本發明 封裝堆曼模組，如鼷1中所 體積體電路34像安装在傾別 具一空腔以及用於連接稹體 Η載體之電極33。電極33僳 路34和積體電路電極32，而 起來。許多數在其外圍具有 ，而那些電極圖案是將電極 等電極圖案彼此電氣連接。 和焊劑的部份。晶片34由線 其容器的外壁進行連接。 圔2 Α和圖2 Β顯示前文提到 2-310957中所提及的習用技 出的半導體元件4Q在其相對 裝的上下由造模物38所形成 半導體元件40經由引線37連 然而，以上所提到的習知 有各式各樣的間題。 根據本發明之半導體封裝 ~ 8 - 之第八較佳實施例； 之第九較佳實施例； 佳實施例；以及 之第十一較佳實施例 請 先 閱 .讀 背 Λ 之 注
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I 經濟部中央揉準局Λ-工消費合作社印裝 ，將簡要 示。如圖 之陶瓷封 電路之電 由薄金屬 最後副總 電極圖案 導引到外 檩號3 1和 焊進行連 論及一習知 示，在模組 裝中。各陶 極3 2和用於 導線連接到 成像由樹脂 的載體被堆 部用的。然 3 6分別指示 接，而載體 半導體 中記億 瓷封裝 連接晶 積髑電 3 5密封 叠起來 後，該 出陶瓷 是經由 在日本專利特許公開No. 術6。如圖2A中所示，製造 的兩侧具有引線37,而其封 。然後，如圖2B中所示，此 接成多级。 結構，如前文所提到的，具 堆叠模組之較佳實施例將如 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 五、發明説明（ 7 A7 B7 經濟部中央搮率局资工消费合作社印装 下所述，在該等實施例中，相同的結溝性部件將以相同 的檫號標示。 第_.二窨掄剜 如龌3A-3C所示，半導體封裝堆叠模組具有以四百萬 位元組動態隨機存取記億體（4M-DRAM)晶片為實例之大 型積體電路晶H U各晶Η的大小為4.5·βΧ 12.0ΒΒ而且 具有26鍤輸入/.輸出端。在實施例中，陶瓷蓮載基底2 將以150# Β厚的玻璃陶瓷基底為例，各蓮載基底2的大 小為5.flBaxl3.4B«而且在晶片1預定安裝的表面及其 内部具有導線導體3,所用的導體3像以耙銀（Ag-Pd)合 金形成的導電混合物所製成。蓮載基底2在本身與其他 蓮載基底彼此電氣連接的部份有貫穿孔5,每德運載基底2的 正面和背面由一導醱將彼此連接在一起，各晶Ml藉由 鉛（Pb-Sn)焊劑所形成的***物4連接到蓮載基底2,標 號12所指出的是母板β 上述堆曼模組藉由以下的程序連接在一起。首先，在 各晶Η 1上形成***物4。接箸，將糊狀焊劑印在運載 基底2的襯塾上，然後將晶片1放置在基底2上。基底 2和晶片1經由230°C下回流而連接在一起（讎4Α)。基底 2具有一電容10於其中。環氣基樹脂或密封樹脂6被注 入到上述副總成中然後硬化藉以加強連接部份和晶Η 1 的可靠度’（圖4Β)β晶片1由0.6Β»厚的矽晶圓所製成， 經由磨平（ground)、抛光、表面磨平（surface ground) 、蝕刻或其他處理變薄到O.Ibb厚（圖4C)e 請 先 聞 讀 背 面 之 注 項 頁 本紙張尺度逋用中國躅家標準（CNS ) A4規格（210X297公嫠） 經濟部中央標準局淤工消费合作社印東 A7 B7 五、發明説明（δ ) 四糎各運載薄晶HI於上面的運載基底2被堆叠一起 而且藉由***物7電氣連接一起。***物7是由直徑 的銅球覆蓋以鉛錫焊劑所構成。待別地，在每锢 基底2的襯墊上印著拗狀焊劑，然後覆蓋有焊劑的箱球 被安置在基底2上，再以熱焊接的方式，形成***物7 (鼷4DU在每锢基底2的另一面也印著拗狀焊劑。其次， 四値基底2被堆盤在一起經由加熱使彼此連接在一起， 然後以樹脂8固定起來。最後的堆叠棋組偽如圖4E所示。 於該描繪之實施例中，四鏞四百萬位元組動態隨機存 取記億體晶H (4M-DRAM)堆叠起來形成一籲一千六百萬 位元組動態随機存取記億體晶片（16H-DRAM)。因為該模 組的厚度傜開放選擇的，梅別的半導釀原件的厚由0 . 1 nil 0.3ibo 於該實施例中，基底2是非常乎的，其凹凸不平的程 度只有20// 1B左右或或更低β在基底2之連接部份，銀 .耙導髅上鍍著錬（Ni)和金（AU)以增加焊劑的黏濕性。 在該實施例中，基底2由以硼硅酸鉛（lead borosilicate)為底的玻璃陶瓷所形成。其可用的替換私有硼 链酸鈴遍^(lead borosilicate-based)塊滑石、IJI橄攬石 (forsterite)、董青石、耐火矽酸鹽或類似的玻璃陶瓷 、或是礬土、耐火矽酸鹽、二氮化三鉛、四氮化三矽或 類似的陶瓷。當基底2是由如此堅固的陶瓷形成時，在 組裝時就較不易變形《因此，這锢堆巖棋組在有令人滿 意的可操作性和可靠度。 -10- 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 以鉛錫為主要成 主要成分的焊劑取 ，所以選擇一個適 等等是必須的。 ***物可由所甩 、鐵或類似的金屬 臃13來取代，如顧 此外，晶Η 1和 可由導電的黏著物 含有銀、銅、金或 在圖3Α中，當礬 有高熱導電性材料 底2在左右方向可 以扮演散熱器的角 第二奮施例 這個實Ife例除了 施例相當的類似。 度100 #进的聚醯亞 裝晶片1之各蓮載 四β蓮載薄晶Η 下面敘述的程序藉 7是用直徑150 # β 狀物印在各薄膜之 焊劑的銅球排列的 經濟部中央揉準局Ι-工消費合作社印裝 312844 Α7 Β7 五、發明説明（？ 分的焊劑可以錫銀、錫鋅、金或絪為 代。因為各材料都有特別特定的熔點 當成分組合的焊劑和合適的處理溫度 的焊劑材料作成，如銅蕊球、或是鎳 蕊球來做。***物亦可由導電性的接 3Β和3C中所示。 基底2之間以及該等基底2本身之間 連接在一起。導電性的黏著物可以是 類似導電金屬粒子的環氣基樹脂。 土、玻璃陶瓷、二氮化三鉛或類似擁 被使用時，正如在圖3Α中所見，各基 延展開來。如此一來，使該基底2得 色。 以蓮戴薄膜替代蓮載基底外，和第一實 蓮載薄膜像以大小5.0ΒΒΧ 13. .4ββ厚 胺薄膜製成。銅線導體3像形成於安 薄膜之表面上。 1於其上具有上述形態的蓮載薄膜以 由***物7電氣連接在一起。***物 的銅球覆蓋以鉛錫焊劑作成的。當糊 正面和背面的襯墊上之後，將覆蓋有 薄膜上。接著，將薄膜堆《在一起然 -1 1 - 本紙張尺度適用中國國家標準（CNS ) Α4规格（210Χ297公釐） 請 先 閱 6 之 注 意 事 項 再 經
央 揉 率 局 頁.. 工 消 費 合 作 社 A7 B7 五、發明説明（、。） 後加熱使焊劑熔化。然後薄膜會以棋組的形式連接在一 起。在薄膜建接的部份，镅導艟鍍上鍊或金以增加焊劑 的黏濕性。 第三窨施例_ 隱5A顯示了單一的蓮載基底，雖然許多數該等基底可 以堆叠在一起形成一堆叠模組。在該實施例中，基底僳 以10fl# 厚的變__作成，而導線導龌是以鉬（Mo)金屬製 成。如圖示，基底中有空腔21用來裝載一個大型積雔電 路晶H。 而用來接著晶Η和基底的***物是用金錫焊 劑製成的。堆昼在一起的基底是用錫鋅焊劑連接在一起》 第四窗掄例 如國5Β中所示，該實施例中除了以運載基底取代運載 薄膜外，其他都和第三實施例相類似。該導線導體係由 銅製成。薄膜在相對應於空腔21的位置具有1Q0#®厚， 而在其他部份為2 50# 1!厚0 於第三或第四實施例中具有空腔21的載體在堆ft和保 護晶片避免被損壊方面很容易處理。這種封裝具高度的 可靠性。 如圖5C和5D中所示，除了***物7必須接著在母板12 上外，相近的載體或所有在堆疊中的載體可以一起用一 非導電性樹脂14密封起來。這增加了模组的抗潮濕性》 當然，非導電性樹脂14也可慝用在没有空腔的載餵上》 第.五奮.旃例 如圖6中所示，此實施例類似於第一與第二實施例， -12- 本紙張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐） 五、發明説明（ A7 B7 經濟部中央揉準f工消費合作社印裝 除了各載體都具有一空腔和邊緣貫穿孔5'之外^圖以到 7 D指出組裝如圖6堆昼的程序。具備金屬或***物的大 型積體電路晶片1面朝下方地連接在具有空腔21的載體 2,並且將晶H1上的電極和載體2上的電極電氣連接 在一起（鼷7 A)。接箸，由樹脂6密封該副總成（圖7Β>β 然後晶HI的背面用拋光、磨平、蝕刻或其他方式處理 到0.1ΒΠ!至ί).3ΒΒ.厚（圖7C)。最後，載體堆《起來並經由 邊緣貫穿孔5'藉由金屬、導電性樹脂或類似的材料連接 在一起（圖？D)。 於上述程序中，當四痼載體封裝在一起時，整傾堆叠 的厚度約從〇 · 4m®到1 . 2βηι,而這値厚度等於0 . lBBi時， 舆當今最薄的封裝技術TSOP比起來，此實施例在封裝密 度上為TSOP的四倍，用於高密度半導體元件相當方便。 藍.六實施.例 _ 8顯示了單一的蓮載基底2,然而許多數的基底可 以堆疊在一起以形成堆叠模組。如圖示，大型積體電路 晶H1經由***物4面朝下地黏到基底2的半導體襯墊 上。陶瓷基底2僳200# B厚。為了增加處理速度和封裝 密度，釋放由該晶H1所産生的熱能以及匹配之阻抗特 性是必須的。有鑑於此，於實施例中，一導體層11形成 於基底2相對於安裝晶片1的該面。導電層11司作為導 熱的散熱器使用，所以可將導體層11接地。該實施例中 的導體層11是用鎢製成的，當然即使主成分是銀、金、 銅、銀耙合金、鉬或類似金靨也能逹成上述目的。 13 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 請 先 閲 讀 背 面 之 注
I 裝 訂 312844 at B7 五、發明説明（ 經濟部中央搮準工消費合作社印簟 於此實施例中 然而，載體2也 陶瓷材料來形成 和7是用銀蒭球 隹十奮施例 如画9A到9C中 除了把陶瓷蓮載 2取代之外。為 該面形成散熱器 及匹配特性阻抗 可以使用實心、 熱器9用的是銅 钼或類似的金屬 所示，散熱器9 達期望厚度的晶 笛導體3也是 分別覆蓋以錫銀 墊處，鋦導髏上 第八窨掄例 譖10 A和1.0 B顯 ，陶瓷載體2是用三氮化二鋁形成的〇 可用第一實施例中所提到的玻璃陶瓷和 。導線導體3是用箱製成的。***物4 而分別覆蓋以錫銀焊劑和金製成的。 所示，此實施例與第六實施例相類似， 華底2用50# 1厚的聚酵亞胺蓮載薄膜 了散熱，在薄膜2相對於安裝晶Κ1的 9。以該散熱器9 ,可以將熱量發散以 以降低雜訊β該散熱器{或稱導體層）9 網狀或類似的圈形。雖然該實施例中散 薄片，其實使用錁、不銹銷、鎢、鋁、 薄Η也是可以的β而且，如圖9Β和9C中 藉由金臈或導熱性良好的樹脂接合於已 片1的背面。 用銅製成時，***物7和4是用銀蕊球 焊劑和金而製成的。在接***物7的襯 鍍有鎳和金。 示出具有熱輻射效應的載體2在堆疊中 之情形之一實施例《如圖1QB中所示，各散熱器9都為 應而被延長〇由於散熱器9的散熱效應 本身的厚度，較佳地，晶Hi和載體2 零。如果該距離不為零，晶片1和載體 了加強散熱的效 正比於散熱器9 之間的距離應為 -1 4 - 本紙張尺度逍用中國國家標準（CNS ) A4规格（210X297公釐〉 請 先 閲 讀 背 之 注 項 再 填 寫 本 頁 A7 B7 五、發明説明（〇 ) 2間之空隙應塗滿具有高導熱性的矽橡膠或油之化合物， 圏10A和10B示出各散熱器9接觸於相關晶片1的背面 ，當然，該散熱器9也可以接觸於載體2的背面》 第九窨施例 如圖11 A和11B中所示，分別具有散熱器9的晶片1被 安裝於母板12上。散熱器9的表面和相關的載體2的背 面如圖11A中所示用金屬或具有高導熱性的樹脂接合在 一起，或如圏11 B中所示用***物接合在一起。此種結 構使得半導體封裝堆叠模組具有高密度和高散熱率的待 性。 第+奮施例 如圖12中所示，形成於最上層載體2上方的電壓15覆 蓋有一絶緣體16，例如聚醯亞胺形式的薄Η。絶緣體16 在其一面塗有黏著層。於此情況下，即使當任何導電雜 質沈澱於電極15上時，整値封裝也不會短路。在堆昼安 裝於母板之後，絶緣體1 6可以被去除以方便.利用電極1 5 作為測試襯墊。 第+ —審旃例 請. 先 閲 背 面 之 注.
項 | ί裝 買I 訂 經濟部中央橾準局I-工消費合作社印装 除 示 所 ，全 17後 孔然 穿， 貫接 成連 13形18 圖處體 如距導 節由 外 之 5 孔 穿 體 載 den 在 的 當 適 上 接端 .1 a地 體接 載到 合接 適連 以部 1 片 端晶 地一 接S 到到 接受 連免 ΒΙ被避 A<v . L 1 2 以 圖層圍 ，體周 孔另 穿在 貫 〇 間面 之方 邊 沿 示 載 的 ο 2 層 體 導 備 具 供 提 導 該 0 2 Η 晶 在 繞 環 ο 2 層 體 〇 導擾 該干 本紙張尺度適用中國國家標準（CNS ) A4规格（21〇X：297公釐） A7 B7 經濟部中央標準§工消費合作社印裝 五、發明説明 ( 4- ) * 1 1 第 十 二 實 施 例 • 1 1 如 面 麗 4 A -4E或 7A- 7D中 所 示 之 由 數 β 載 體 R-HU 2 形 成 之 一 多 1 1 載 體 本 歷 0 晶 片 1 藉 由 隆 起 物 連 接 到 多 載 歷 本 體 上 〇 然 請 1 先 1 後 將 密 封 樹 脂 6 注 入 晶 Μ 1 和 相 對 的 載 體 2 之 間 0 接 下 閲 來 在 多 載 歷 的 組 態 下 9 各 晶 η 1 的 背 面 經 由 磨 平 S 抛 光 背 面 1 之 X 蝕 刻 或 其 他％ 方 法 達 到 預 定 的 厚 度 〇 注 $ I 於 上 述 多 Mp. 載 aatt 髖 本 體 中 > m 起 物 7 是 由 球 11 狀 焊 劑 法 N 糊 事 項 1 I 1 ^ I 狀 劑 印 刷 法 、 分 配 法 或 類 似 的 技 術 製 造 f-R- 坊6 預 定 的 高 度 Q 填产 '寫 本 、1 袭 由 値 别 晶 片 1 延 伸 至 相 對 載 體 2 的 接 腳 是 用 來 在 燒 線 頁 1 | 测 試 之 前 、 之 中 之 後 作 為 测 試 電 子 特 性 用 的 0 值 得 注 1 I 意 的 是 在 晶 Η 1 安 裝 在 多 載 m 歷 本 體 後 9 在 任 何 預定級作 這 | 樣 的 測 Kj 都 是 有 效 的 〇 進 行 以 上 的 測 試 預 定 數 鳌 的 載 體 1 被 訂 定 位 〇 當 使 用 金 屬 接 著 時 » 載 m 麗 是 利 用 回 梳 、 熔 接 或 1 類 似 的 方 法 連 接 在 —- 起 當 使 用 的 是 導 電 樹 脂 時 9 載 JMtr 體 1 是 利 用 熱 固 化 、 紫 外 線 硬 化 或 類 似 的 技 術 接 箸 在 一 起 〇 I 1 I 接 下 來 9 經 由 切 片 、 雷 射 畫 線 Ν 碎 開 或 類 似 的 技 術 製 成 锢 別 獨 立 的 半 導 emt 體 元 件 〇 在 不 考 慮 碎 開 法 的 情 形 之 1 下 初 始 的 多 載 *na> m 本 體 疋 帶 有 制 動 凹 糟 的 〇 最 後 如 果 有 » 必 要 的 話 9 可 以 進 行 電 子 待 性 測 試 0 測 試 時 9 是 由 經 由 1 • 1 探 針 或 直 接 面 對 面 接 to 觸 的 方 式 連 接 至 為 了 m 結 堆 昼 和 在 1 I 載 體 頂 部 底 部 、 相 對 侧 的 襯 墊 上 〇 1 1 雖 然 之 刖 的 例 子 著 重 在 動 態 隨 機 存 取 記 億 體 上 i 本 發 1 1 明 亦 可 以 適 用 於 甚 至 徹 處 理 晶 片 閛 陣 列 或 是 其 他 大 型 1 | 積 體 電 路 晶 Η 上 ό 1 總 而 之 9 可 以 見 到 的 是 本 發 明 提 供 的 半 導 體 封 裝 堆 1 | - 1 Ε - 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 五、發明説明（u ) 叠模組及其製造方法具有多項空前的優點，茲列舉如下： 請 先 閲 讀 背 面 之 注 I 項 再』 (1) 本模姐又小又薄又稠密，而且具有期望之電子特性 β不論是傾別或是在模組中9 載體的導'線長度都是最 短的。 (2) 預定數量之具有相對應晶片的蓮載基底或蓮載薄膜 可以集中起來堆疊連接成一値模組。此提高了作業的效 率以及降低了製逭的成本。各載體的電路圖案可以部份 連接或部分分離以形成待定的電路功能β如果每個載體 上有獨自的符號或編號，就可以用預期的方式組合電子 電路〇 (3) 由於大型積體電路晶片是安裝於値別的蓮載基底 或運載薄膜上，所以可以在載體上進行晶片測試，因此 只有合格的産品才被堆叠起來，預定數量的具有相對應 晶Η之蓮載基底或蓮載薄膜可以集中起來堆畳連接成一 個模組，此提高了作業的效率以及降低了製造的成本。 另外，連接晶Η用的陵起物可以由具有高熔點的焊劑製 成〇 <4)該封裝具有期望的散熱方式以及已匹配的特性阻 抗〇 經濟部中央梂準0^工消费合作杜印裝 (5)當使用陶瓷載髏時，基底相當的平坦而且具有抗 潮濕性。此外，陶瓷載髅在組裝中較容易處理β另外， 由於此種載體在進行回流時表面仍保持平坦，所以提高 了連接的可靠度。 對熟知此技藝者可依本發明之說明作種種不同的修飾 ,而不會背離本發明之範圍。 17- 本紙張尺度適用中國國家標準（CNS ) A4規格（21 OX297公董)

Claims (1)

  1. A8 B8 C8 D8 六、申請專利範圍 第851 0 2110號「半導體封裝堆曼楔組及其製造方法 專利案 _ 年豕月月17 Λ申請專利範圍： ___ 1. 一種半導體封裝，包括： 一載醱； 後數貫穿孔，形成於該載髅中或在該載體末端面處 ，且藉由電氣連接載體用之睡起物逹成三度空間之連 接； 一導體匾案，其至少在該載醱之正面形成； 内部接合用襯墊，於該載龌之背面形成且電氣連接 到該等貢穿孔，其中内部接合用之該等襯墊&含*** 物；以及一大型積體電路晶Μ，藉由該等襯塾1接該載 鼸，其中該大型積腾《路晶κ面朝下地安裝於該載體 .上。 2. 如申請專利範圍第1項之半導腥封裝，其中内部接.合 用之該等襯墊以及用於連接載«之該等***扬像由主 成分為鉛錫合金、錫銀合金、錫鋅合金、金錫合金、 金或絪之焊劑所形成c 3. 如申請專利範圍第1項之半導醮封裝，尚包含一緊密 地接觸於該載體或該大型積«電路晶片之散熱器。 4. 如申誚專利範圍第3項之半導體封裝，尚包含一緊密 地接觸於該載體之導體案。 -1- 本紙張尺度適用中囷國家揉率（CNS > A4規格（210X297公釐） --l·--e---(裝-- (請先閲^^面之注項再填寫本頁) 、11 經濟部中央標準局負工消费合作社印装 .A8 B8 C8 ' D8 六、申請專利範圍 φ 5.如申鲭專利範圍第4項之半導饅封裝，其中該導髖匾 案偽接地。 6 ,如申請專利範圍第1項之半導髏封裝，其中該載齷包 含一用於放置該大型積髏電路晶Μ之空腔。 7. 如申讅專利範醒第6項之半導體封裝，其中該空腔具 有一深度較大於該大型積髏電路晶Μ上所形成之II起 物之商度。 ^ 8. 如申誚專利範圍第1項之半導儺封裝，其中該載醱中 含有一電容器。 9. 如申誚專利範圍第8項之半導醱封裝，其中該電容器 電氣連接於一笛源與地線之間。 10. 如申諝專利範圍第1項之半導體封裝，其中該載饅 包含一似薄膜似之燒結陶瓷基板，一可撓曲膜以及一 印刷電路板。 11. 如申誚專利範圍第10項之半導臛封裝，尚包含一絕 錁鼸覆S於該半導體封裝最上層正面上所形成之電..極 終端12。 12. 如申請專利範臞第1項之半導醱封裝，尚包含一形 經濟部中央梯準局貝Η消費合作社印策 ml -II - nn f 1^1 -r^K— m HI - - - u (請先閱讀背面之注意事項再填寫本頁) ^ 成於該載體之上或沿該載體邊緣部份且接地之導塍層。 . 13. 如申譴專利範圍第1項之半導體封裝，尚包含在適 當間距下以陣列形成於該載體遴緣部分中之貫穿孔， 且無一例外地接地。 14. 一種半導匾封裝堆叠槙组，其中許多數載腥一健疊 -2- 本紙張尺度逍用中國囷家標準（CNS ) Α4規格（210X297公釐） 經濟部中央榡準局員工消費合作社印氧 A8 B8 C8 D8 六、申請專利範團 箸一傾地堆昼在一起，而各該許多數載齦包含在該載 體之中或表面邊緣所形成之貫穿孔，一至少被形成於 該載鼸正面之導歷圓案，在該載體背面所形成之内部 接合用襯墊，與該等貫穿孔連接在一起，以及一大型 積鼯«路晶μ藉由該等襯墊與該載醱連接在一起，該 許多數載醱由該等貫穿孔三度空間地連接在一起。 15. 如申請專利範圍第14項之棋組，其中該等貫穿孔偽 形成於該載醱中，且藉由電氣連接用於連接載釀之隆 起物連成三度空間之連接。 16. 如申請專利範圍第14項之模组，其中該大型積體霣 路晶Μ僳面朝下地安裝於該載體上，且其中用於内部 接合之該等襯魅包含滕起物。 17. 如申請專利範圔第16項之模組，其中用於内部接合 之該等襯塾和用於連接載鼸之該等***物偽由主成分 為鉛錫合金、錫銀合金、餳鋅合金、金錫合金、.金或 铟之焊劑所形成。 1δ.如申請專利範圍第14項之模組，尚包含一介於安裝 在任一該許多數載賸上之該大型積髏電路晶Η與該柑 鄰之載體間之敗熱器，且緊密地接觸於該載饅或該大 型積髅電路晶Μ。 19. 如申請專利範國第18項之模組，肖包含一緊密地接 觴於該載醱上之導艨鼷案。 20. 如申謫專利範國第19項之棋組，尚包含一具弯离導 -3- 本紙張適用中國國家橾準（CNS ) Α4«^ ( 210X297公釐） (請先閣讀背面之注^^項再填寫本頁) 訂--- 經濟部中央標準局員工消費合作社印装 A8 B8 C8 D8 々、申請專利範圍 熱性材料且置入於該大型積髏電路晶Η與該載體以及 該散熱器之間。 21. 如申讅專利範圍第14項之模組，其中一密封樹脂镇 滿於各預定作内部連接之大型積體電路晶Μ與一相關 之該等載體之間。 22. 如申請專利範圍第14項之模組，其中該等載體中含 有一電容器。 23. 如申讅專利範圍第22項之模組，其中該電容器像電 氣連接於一電源和地線之間。 24. 如申譆專利範圍第14項之模組，其中該載體包含一 似薄膜之燒結陶瓷基底，可撓曲膜以及一印刷電路板。 25. 如申讅專利範圈第14項之模組，尚包含一絕緣體覆 蓋在形成於最上層載體正面之電極終端。 26. 如申請專利範圍第14項之模組，尚包含一形成於該 載體之上或沿該載體邊緣部份之導電層且接地。 27. 如申請專利範圍第14項之模組，尚包含在適當間距 下以陣列形成於該載體邊縐部分中之貫穿孔，且無一 例外地接地。 28. —種製造半導體封裝堆曼模組之方法，包括下列步 驟： (a) 將一陶瓷運載碁底和一個大型積體電路晶Η連 接在一起； (b) 在各自有***物之該陶瓷蓮載基底舆該大型積 -4- 本紙張尺度逋用中國國家標準（CNS ) 格（2.10X297公釐） (請先閱讀背面之注意事項再填寫本買) A "ΐ A8 B8 C8 D8 J12844 申請專利範圍 體電路晶μ之間注入一密封用樹脂； (C)以抛光、碾磨、表面碾磨及蝕刻方法來減少該 大型積體電路晶Μ安裝於該陶瓷運載基底之厚度以 及 (d)堆叠與焊接各自運載一大型積體電路晶Η之許 多數陶瓷蓮載基底。 29.—種半導體封裝堆曼模組，其中一安裝大型積髏電 路晶Μ、經由***物將該大型積體電路晶Η連接到該 許多數載體，以樹脂密封、打薄、燒線測試、多級連 接及電性測試等步驟之多載體本體僳由互不分離之許 多數載體形成，且然後藉由雷射、銘刻標記、切Κ及 碎開將該許多數載匾分離開來。 1I — (請先閱讀背面之注意事項再填寫本頁) ^a4 經濟部中央摞準局員工消費合作社印裝 本紙張尺度逋用中國國家標準（CNS ) A4规格（210X297公釐）
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KR970000214B1 (ko) * 1993-11-18 1997-01-06 삼성전자 주식회사 반도체 장치 및 그 제조방법
EP0658937A1 (en) * 1993-12-08 1995-06-21 Hughes Aircraft Company Vertical IC chip stack with discrete chip carriers formed from dielectric tape

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI397155B (zh) * 2009-12-24 2013-05-21 Powertech Technology Inc 形成矽穿孔之多晶片堆疊過程
TWI512862B (zh) * 2013-03-25 2015-12-11 Toshiba Kk Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
EP0729184A3 (en) 1999-11-03
US6188127B1 (en) 2001-02-13
KR100231366B1 (ko) 1999-11-15
JP2944449B2 (ja) 1999-09-06
EP0729184A2 (en) 1996-08-28
JPH08236694A (ja) 1996-09-13

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