TW201212297A - Power surface mount light emitting die package - Google Patents

Power surface mount light emitting die package Download PDF

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Publication number
TW201212297A
TW201212297A TW100139850A TW100139850A TW201212297A TW 201212297 A TW201212297 A TW 201212297A TW 100139850 A TW100139850 A TW 100139850A TW 100139850 A TW100139850 A TW 100139850A TW 201212297 A TW201212297 A TW 201212297A
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Taiwan
Prior art keywords
substrate
die package
semiconductor die
reflector
lens
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TW100139850A
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English (en)
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TWI538255B (zh
Inventor
Peter S Andrews
Ban P Loh
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Cree Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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    • H—ELECTRICITY
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

201212297 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種功率式表面安裝之發光晶粒封裝。 【先前技術】 本發明係關於封裝半導體裝置領域，更特定言之，係關 於封裝發光二極體。 發光二極體（LED)經常封裝於引線框封裝之内。引線框 封裝通常包括一模製塑性體，其密封有一 LEd ' 一透鏡部 分及連接至該LED並延伸至該塑性體之外之薄金屬引線。 引線框封裝之金屬引線充當為LED提供電能之管道，且同 時可吸取熱量遠離LED ^當對LED施加能量以使其發光時 LED將產生熱量。引線之一部分自封裝體向外延伸以連接 至引線框封裝之外部的電路。 LED產生之部分熱量由塑性封裝體耗散；然而大部分 熱量經由封裝之金屬組件被吸取而遠離LED。金屬引線通 常很薄且具有一小橫截面。因此，金屬引線自LED移除熱 量之能力是有限的。此限制了可發送至LED之能量的量’ 藉此限制了 LED可產生之光的量。 在LED封裝設計中’於LED封裝内金屬引線之下置放一 散熱棒以增加LED封裝之散熱能力。該散熱棒增加了 LED 封裝之散熱能力；然而，散熱棒增加了 LED封裝之尺寸、 物質及成本。尺寸、物f及成本之增加非吾人所要。 在另一 LED封裝設計中，引線框之引線（以不同形狀及 組態）延伸至LED封裝體之緊接邊緣之外。此增加了引線部 157582.doc 201212297 分曝露於周圍空氣之表面區域。經延伸之引線所增加之曝 露表面區域亦使得led封裝之散熱能力增加；然而’引線 之延伸增加了 LED封裝之尺寸、物質及成本。 §前引線框封裝設計之另一不良方面係關於與封裝之熱 膨脹相關之問題。當熱量產生時，LED封裝會產生熱膨 脹。LED封裝之每一部分具有不同之熱膨脹係數（CTE)。 舉例而言，LED之CTE、封裝體之CTE、引線之CTE及透 鏡之CTE皆互不相同。為此原因，當加熱時，每一此等部 为產生之不同程.度熱膨脹導致封裝之部分之間的機械應 力’藉此不利地影響了封裝之可靠性。 因此，需要改良LED封裝以克服或減輕先前技術封裝之 一或多個缺點。 【發明内容】 本發明之實施例提供諸如發光二極體之半導體晶粒之 裝’㈣裝包括=-基板’其具有可於安裝塾上連接至 光二極體之導電元件’·-反射板’其耦合至基板且實質 環繞安裝墊；及透鏡，其實質上覆蓋安裝墊。 本發明之其它實施例提供包括一底部散熱片及一頂部 熱片之半導體晶粒封裝。該底部散熱片在其上表面上可 有跡線。半導體晶片可安裝至底部散熱片上表面之上並 連接至跡線。頂部散熱片可機械耦合至底部散熱片。 在其它實施例中，底部散熱片可包括_且有第—及第 表面之導熱導電板°該板可包含諸如鋼、紹或任一者心 金之金屬。薄的導熱絕緣薄膜形成於金屬板之第一表面 157582.doc -4- 201212297 部分上或可形成於金屬板之其它表面上。 可於陶瓷/聚合薄膜上形成諸如金屬跡線及/或金屬引線 之導電元件。由於陶瓷/聚合薄膜絕緣，導電跡線不會與 金屬板電接觸。導電元件可形成或電連接至適用於接收諸 如LED之電子裝置之安裝墊。 在某些貫施例中，可形成穿過基板之一或多個通孔。在 某些貫施例中，通孔可在内部塗覆有諸如陶究/聚合薄膜 之絕緣材料。可於通孔中形成諸如導電跡線之導電體以將 基板之第一表面上之導電元件電連接至基板之第二表面上 之導電元件。 根據本發明之實施例，基板亦可包括諸如基納（zener)二 極體及/或一連接於一或多個導電元件之間的電阻網路之 電子電路系統以實現靜電放電保護（ESD)及/或過電壓保 護。 以下之詳細描述結合伴隨之圖式以實例方式說明了本發 明之原則，由此將使本發明之其它態樣及優點變得顯而易 見。 【實施方式】 現參考圖1至圖10B來描述本發明，其說明了本發明之各 種實施例。如圖式中之說明，誇示各層或區域之尺寸以達 成說明之目的，且因此用以說明本發明之總體結構。此 外’參考形成於基板或其它層或結構上之_層或結構來描 述本發明之各種態樣。如將為熟習此項技術者所瞭解，= 於形成於另一層或基板”上，，的層的論述涵蓋了額外層可插 157582.doc 201212297 入。本文中將對於形成於另一層或基板上而不含***層的 層的論述描述為"直接在”層或基板上形成。此夕卜，如圖式 中之說明’本文中使用諸如在下方之相關術語來描述一層 或區域與另一層或區域之間的關係。應瞭解，&等術語意 欲包括除圖中所描繪方位之外之設備的不同方位。舉例而 。右圖中之裝置翻轉π ’則描述為在其它層或區域"下 方之層或區域將被定向為在此等其它層或區域之"上方 ’’。在此情形中術語"下方"意欲包括上方及下方。全文中 類似數字表示類似元件。 如圖中為達成說明之目的所示’藉由發光晶粒封裝來舉 例說明本發明之實施例，該封裝包括：—底部散熱片（基 板），其具有用以在安裝墊上連接至發光二極體之跡線； 及一頂部散熱片（反射板），其實質上環繞安裝墊。透鏡覆 蓋女裝墊上有。實際上，根據本發明之某些實施例之晶粒 封裝包含一兩部分散熱片，其中使用底部散熱片（除用於 吸取及消散熱量之外）作為基板以在其上安裝及連接LED , 且使用頂部散熱片（除用於吸取及消散熱量之外）作為反射 板以引導由LED產生的光線。由於底部及頂部散熱片皆可 使LED散熱’更多電能可被傳遞至LED，且LED可藉此產 生更多的光》 此外’在本發明中，晶粒封裝本身可充當自Led移除熱 1並將其消散的散熱片。因此，本發明之LED晶粒封裝可 不需要自封裝延伸出去之獨立的散熱棒或引線。因此，根 據本發明之LED晶粒封裝比先前技術之晶粒封裝可更緊 I57582.doc 201212297 密、更可靠且製造成本更低β 圖1Α為根據本發明之一實施例之半導體晶粒封裝丨〇之透 視圖，且圖1B為圖1A之半導體封裝之分解透視圖。參看 圖1A及圖1B ’本發明之發光晶粒封裝1〇包括一底部散熱 片20、一頂部散熱片4〇及一透鏡5〇。 圖2A至圖2D更詳細地說明了底部散熱片2〇。圖2A、 2B、2C及2D分別為圖ία之底部散熱片2〇之俯視圖、側視 圖、則視圖及仰視圖。此外，除底部散熱片2〇之前視圖 外，圖2C中亦展示了 LED組件60〇圖1B中亦說明了 [ED組 件60。參看圖1A至圖2D，底部散熱片2〇為電跡線22及 24 ’焊墊26、32及34以及LED組件60提供支撐。因此，亦 將底部散熱片20稱為基板20。在圖中，僅代表性焊墊％、 32及34標記有參考數字以避免混亂。可使用導電材料來製 ie跡線22及24以及焊墊26、32及34。此外，額外之跡線及 連接可製造於基板20之頂面、側面或底面或分層於基板2〇 之内。可使用已知之方法（例如通孔）將跡線22及24、焊墊 26、32及34以及其它連接以任何組合彼此互連。 在某些貫施例中’基板20可由例如氮化|呂（A1N)或氧化 銘（A12〇3)之具有南熱傳導率而電絕緣之材料來製得。在 諸如如下結合圖7A至圖10B描述之實施例之其它實施例 中’基板20可包含既導電又導熱之材料。在此等實施例 中’可藉由基板之部分上形成之絕緣薄膜來使金屬引線或 導電跡線22及24或兩者皆與基板相隔離，如下文中將詳細 描述。基板20之尺寸可視應用及用於製造晶粒封裝1〇之方 157582.doc 201212297 法而有很大的變化。舉例而t，在例示性實施例中，基板 20之尺寸可介於零點幾毫米（馳）至幾十毫米之範圍内。雖 然本發明並不限於特定尺寸，本發明之晶粒封裝1〇的具體 實施例在圖中係說明為標示有尺寸。中展示之所有尺寸 皆以毫米(用於長度、寬度、高度或半徑)及度數(用於角度 計，除了其它於圖中或本文之說明書中或兩者中另外所指 示° 基板20具有-頂面21 ’該頂面21包括電跡線22及24。跡 線22及24提供自焊墊（例如頂部焊墊26)至安裝墊“之電連 接。頂部焊墊26可包含通常接近基板2〇側面之跡線^及以 之部分。頂部焊墊26電連接至側面焊墊32。安裝墊28為安 裝有LED組件60之頂面（包括跡線22之部分或跡線24之部分 或兩者）之一部分。通常，安裝墊28實質上安置於接近頂 面21之中心處。在本發明之替代性實施例中，可由其它半 導體電路或晶片來置換LED組件60。 跡線22及24提供電子路徑以允許LED組件6〇電連接至焊 墊26、32或34。因此，將某些跡線稱為第一跡線22而將其 匕跡線稱為第二跡線2 4。在例示性實施例中’安裝塾2 8包 括第一跡線22及第二跡線24之部分。在例示性實施例中， 將LED組件60置放於安裝墊28之第一跡線22部分上以藉此 與第一跡線22相接觸。在例不性實施例中，LED組件60及 第二跡線24之頂部經由接線62彼此連接。視LED組件60之 構造及方位而定，第一跡線22可為LED組件60提供陽極（正 極）連接且第二跡線24可為LED組件60提供陰極（負極）連接 157582.doc 201212297 (或反之亦然）。 LED組件60可包括額外元件。舉例而言，在圖ΐβ及圖2c 中LED 且件60係說明為包括LED接線次組件μ 及叙光一極體(LED)66。該LED次組件64在此項技術中已 為吾人所知’為討論本發明之目的而在此說明，並不意欲 限制本發明。在圖中’展示之led組件的晶粒附著於基板 20在替代)·生貫把例中，可組態安裝墊28以允許l印組件 60之覆曰曰附著。此外，可於安裝墊28上安裝多個組 件。在替代性實施例中，LED組件6〇可安裝於多條跡線之 上。若使用覆晶技術更是如此。 跡線22及24之拓撲可與圖中所說明之拓撲有很大不同同 時仍然保持在本發明範嘴之内。在圖中，展示了三個獨立 的陰極（負極）跡線24以說明可於安裝墊28上置放三個LED 組件，每一組件連接至不同之陰極（負極）跡線；因此，三 個LED組件可分別是可電控的。跡線22及24由諸如金、 銀、錫或其它金屬之導電材料製得。跡線^及以可具有如 圖說明之尺寸且視應用而定其厚度可為大約幾微米或幾十 微米。舉例而言，跡線22及24可為15微米厚。圖1A及圖 2A說明了方位標記27。即使在組裝晶粒封裝丨〇之後亦可使 用此等標記來辨識晶粒封裝1〇之正確方位。跡線22及 24(如所說明）可自安裝墊28延伸至基板2〇之側面。 繼續參看圖1A至圖2D，基板20界定了半圓筒空間23及 接近其側面之四分之一圓筒空間25。在圖中，僅代表性空 間23及25標記有參考數字以避免混亂。當晶粒封裝1〇附著 157582.doc 201212297 至印刷電路板（PCB)或晶粒封裝1〇為其一組件之另一設備 (未圖示）時，半圓筒空間23及四分之一圓筒空間25為焊接 ^ 間以使其經由s亥等空間流動（flow-through)及在該等 工間内凝固（sohify-in)。此外，在製造過程期間半圓筒空 間23及四分之一圓筒空間25提供方便之花紋及折點。 可將基板20製成具有複數個相鄰部分之帶狀物之一個別 4刀，每一相鄰部分為一基板2〇。或者，可將基板製成 陣列。卩分之一個別部分，該陣列具有相鄰部分之多個列 及夕個行。在此組態中，在製造過程期間可使用半圓筒空 間23及四分之一圓筒空間乃作為該帶狀物或陣列之把手。 此外半圓筒空間23及四分之一圓筒空間25結合該等部 分之間的切割槽或其它蝕刻輔助將每一個別基板與帶狀物 或曰曰圓77 % °可藉由通過使帶狀物或晶圓發生彎曲來將物 理應力引至蝕刻線(穿過半圓筒空間23及四分之一圓筒空 間25)從而實現分離。此等特徵簡化了製造過程，從而藉 由免去在製造過程期間使用特別載體固定裝置來處理帶狀 物或晶®的需要來降低成本。此外圓筒空間23及四分 之圓筒空間25可充當通孔以連接頂部坪塾、側面焊塾 32及底部焊墊34。 面29。可使用諸如金、 之其它材料之高熱傳導 基板20具有包括熱接觸塾％之底 銀、錫或包括（但不限於）稀有金屬 率材料來製造熱接觸墊。 圖3說明了圖1Α及圖1Β之半導俨 圖 千导體封裝之部分的剖示, 。更特疋5之，圖3說明·?· TS .ΑΓΤ #，J·, 月了頂邛放熱片40及透鏡50. 157582.doc -10- 201212297 不側視圖。參看圖ΙΑ、圖1B及圖3頂部散熱片40由諸如 鋁、銅、陶瓷、塑膠、複合物或此等材料之組合之高熱傳 導率材料製得。可使用高溫、高機械強度、介電材料來塗 覆跡線22及24(中央晶粒附著區域除外）以密封跡線22及24 並提供保護以免發生諸如到痕、氧化之物理及環境損害。 塗覆過程可為基板製造過程之一部分。使用外塗層亦使基 板20與頂部散熱片4〇相隔離β接著，外塗層可由諸如熱介 面材料之向溫黏著劑覆蓋，該熱介面材料可由結合基板2〇 及頂部散熱片4〇之熱固性物（THERMOSET)製得。 頂部散熱片40可包括實質上環繞安裝於安裝墊28(圖2Α 及圖2C中）上之LED組件60之反射表面42。該反射表面42 反射來自LED組件60之部分光，如樣本光射線63所說明。 光之其匕部分不經反射表面42反射，如樣本光射線61所說 明。例示性光射線61及63並不意謂代表光學技術中通常使 用之光跡線。頂部散熱片40較佳由可經抛光或鑄造或兩者 皆可之材料製得以達成光的有效反射。或者，可使光學反 射表面42或整個散熱片4〇上鍍敷或沈積諸如銀、鋁或能實 現此目的之其它物質之高反射性材料以達成高反射率。因 此，亦將頂部散熱片4〇稱為反射板4〇。若需要封裝1〇之熱 性能及當需要封裝丨〇之熱性能時，該反射板40可由具有高 熱傳導率之材料製得。 在例示性實施例中，反射表面42係說明為相對於反射板 之水平面成一定角度（例如45度）之一平面。本發明並不限 於例示丨生實施例。舉例而言，反射性表面U可相對於反射 157582.doc 201212297 板之水平面成不同角度。或者’反射板可為拋物線形或其 它形狀。 反射板40包括突出部分44以支撐並耦合透鏡5〇。使用諸 如（例如僅為）聚矽氧之密封材料46將LED組件60密封於（圖 1A及圖1B中之）晶粒封裝10之内。密封材料46較佳為具有 商光透射率及與透鏡50之折射率相匹配之折射率之高溫聚 合物。 透鏡50由諸如（例如僅為）玻璃、石英、高溫塑膠或此等 材料之組合之高光透射率材料製得。可置放透鏡5〇使其與 密封材料46相接觸。因此，當晶粒封裝1〇被加熱並產生熱 膨脹時藉由密封材料46可使透鏡50減震，使得可保護透鏡 50免受晶粒封裝10之其它部分之熱膨脹產生之機械應力的 影響。在某些實施例中，透鏡5〇界定了淺溝槽52，其可填 充有光學化學物質，例如磷、諸如碳酸鈣之光擴散劑、諸 如螢光材料之中心頻率位移材料或此等材料之組合。 圖4說明了晶粒封裝1〇耦合至外部散熱片7〇。參看圖4， 可使用環氧樹脂、焊料或其它任何導熱黏著劑、導電黏著 劑或既導熱又導電黏著劑74來將熱接觸墊36附著至外部散 熱片70。外部散熱片70可為自晶粒封裝丨〇吸取熱量之印刷 電路板（PCB)或其它結構。外部散熱片可包括各種組態之 電路元件（未圖示）或熱消散片72。 圖5至圖6D展示了本發明之具有某一替代組態之一實施 例。此第二實施例之部分與圖丨A至圖4中說明之第一實施 例之相應部分相類似。為方便起見，圖5至圖6D中說明之 157582.doc -12· 201212297 夂去奴：施例刀相類似之第二實施例部分指定為相同之 " 字類似而已改變之部分則指定為帶有字母"a”之 才同參考數子’且不同部分指定為不同參考數字。 圖5為根據本發明其它實施例之led晶粒封裝10a之剖示 透視圖》參考圖5’本發明之發光晶粒封裝1〇a包括一底部 ，，、、片（基板）20a、—頂部散熱片（反射板）術及一透鏡 50 ° 圖6A、6B、6C及6D分別提供圖5之基板2〇a之俯視圖、 側視圖、則視圖及仰視圖。參看圖5至圖6d，在例示性實 她例令，基板20a包括一正跡線22a及四條負跡線24a。此 等跡線22a及24a之組態與圖2Α中之跡線22及24之配置不 同。基板20a包括凸緣3 1，其界定了閉鎖空間33以接收反 射板40a之支腳35，藉此機械地將反射板4〇a與基板2〇a嚙 合0 圖7A至圖10B說明了本發明之其它實施例。根據此等實 施例，用於高功率發光裝置之基板包括具有第一及第二表 面之導熱導電板。該板可包含諸如銅、鋁或任一者之合金 之金屬。在金屬板第一表面上形成薄的、導熱絕緣薄膜。 在某些實施例中，導熱絕緣材料包含陶瓷/聚合薄膜，諸 如可自Chanhassen, MN，USA之Bergquist公司購得之熱包 層薄膜（Thermal Clad Him)。 可於陶瓷/聚合薄膜上形成諸如金屬跡線及/或金屬引線 之導電元件。由於陶瓷/聚合薄膜絕緣，導電跡線不會與 金屬板電接觸。導電元件可形成或電連接至適用於接收電 157582.doc • 13· 201212297 子裝置之安裝墊。如上文中連接圖1_6中說明之實施例所 討論’金屬跡線之拓撲可有很大的變化同時仍然保持在本 發明之範嘴之内。 可藉由例如焊接、熱音波結合或熱壓縮結合將LED組件 結合至安裝墊。LED產生的熱至少部分可經由金屬板消 散。由於基板本身可充當散熱片，可減少或免去將額外散 熱片結合至該結構之需要。然而，可置放額外散熱片使之 與金屬板熱連通，如此可更有效地吸取熱量遠離操作裝 置。 ’ 在一實施例中，可形成一或多個通孔穿過絕緣薄膜及金 屬板。該通孔可在内部塗覆有諸如陶瓷/聚合薄膜之絕緣 材料。諸如導電跡線之導電體可形成於通孔中且可將基板 之第一表面上之導電元件電連接至基板之第二表面上之導 電元件無需使用金屬引線即可將根據此實施例之基板安 裝至諸如印刷電路板之表面上，此可導致機械性更強之封 裝。 根據本發明之實施例之基板亦可包括諸如離散基納二極 體及/或電阻網路之電子電路以實現靜電放電（ESD)及/或過 電壓保護。 雖然未於圖7-10中說明，基板可進一步包括諸如半圓筒 空間及四分之一圓筒空間、方位標記、側面結合墊、凸緣 及如圖1-6中說明之其它特徵之特徵。 圖7A至圖1 〇B中說明之實施例之部分與圖i至圖6D中說 明之實施例之相應部分相類似。為方便起見，圖7 A至圖 157582.doc 201212297 1 OB中所說明之蛊笸_昝# ,, 貫轭例之部分相類似之實施例部分 指定為相同之參考蛰宝，来s , 致予類似而已改變之部分則指定為帶 有字母”b”之相同參者動宝 η π 专数子且不同部分指定為不同參考 數字。 參看圖A 明了根據本發明之另一實施例之基板 20b圖7A及圖7B分別提供了基板鳥之俯視圖及箭視 圖此外除基板2〇b之前視圖之外圖7B中還展示了 LED 組件6〇。基板2〇b包括具有帛一表面5U及f二表面51b之 導熱導电板51。板51可包含諸如銅、紹或任一者之合金之 金屬I金屬板51之第一表面51a之至少部分上形成薄 的、導熱絕緣薄膜48。在某些實施例中，導熱絕緣薄膜48 包含陶究/聚合薄膜，諸如可自Chanhassen，MN，USA之 Bergquist公司購得之熱包層薄膜。此外，可於板^之第二 表面5 lb及側面上形成導熱絕緣薄膜49。 基板2〇b為諸如電跡線22及24之導電元件、焊墊26及 LED組件60提供支撐。此外，可將額外跡線或連接製造於 基板20b之頂面、側面或底面上，或分層於基板2〇b之内。 可使用已知之方法（例如通孔）將跡線22及24、焊墊26及其 它任何連接以任何組合形式彼此互連。 基板2〇b具有一頂面21b ’該頂面21b包括電跡線22及 24 °跡線22及24提供自焊墊（例如頂部焊墊26)至安裝墊28 之電連接。頂部焊墊26可包含通常接近基板2〇1?側面之跡 線22及24之部分。安裝墊28為安裝LED組件60之頂面（包括 跡線22之部分或跡線24之部分或兩者）之一部分。通常， 157582.doc -15· 201212297 將安裝墊28實質上定位於接近頂面21b之中心處。在本發 明之替代性實施例中，可由其它半導體電路或晶片來置換 LED組件60。 跡線22及24之拓撲可與圖中說明之拓撲有很大的不同同 時仍然保持於本發明之範疇之内。在圖中，僅展示了一條 陰極（負極）及一條陽極（正極）跡線。然而，基板2〇b上可包 括多條陰極或陽極跡線以方便安裝墊28上之複數個led組 件之安裝，每一組件連接至不同陰極或陽極跡線；因此， 三個LED組件可分別為可電控的。跡線22及24由諸如金、 銀、錫或其它金屬之導電材料製得。 基板20b具有包括熱接觸墊36之底面29b。該熱接觸墊可 使用諸如金、銀、錫或其它材料（包括但不限於稀有金屬） 之高導熱性材料來製得。 圖7C說明了沿圖7A之截面線A-A所取之基板20b之部分 的剖示前視圖。如圖7C中所示，可形成一或多個通孔 45a、45b穿過基板20b。該等通孔45a、45b可在内部塗覆 有諸如陶瓷/聚合薄膜之絕緣材料。諸如導電跡線47a、 47b之導電體可形成於通孔中，且可將基板第一表面上之 導電元件電連接至基板第二表面上之導電元件。如圖7(：所 說明’通孔45a中之導電跡線47a將基板2〇b上之第一側面 21b或頂面21b上之跡線24連接至基板20b之第二側面29b或 底面29b上之焊墊34。同樣地，延伸穿過通孔45b之導電跡 線47b將導電跡線22連接至結合墊38。 無需使用金屬引線即可將根據此實施例之基板安裝於諸 157582.doc 201212297 如印製電路板之表面上，此可導致機械性更強之封裝。 如上所述，可使用高溫、高機械強度、絕緣材料來塗覆 跡線22及24(中央晶粒附著區域28除外）以密封跡線22及 24，並為其提供保護以免受諸如到痕、氧化之物理及環境 損害。該塗覆過程可為基板製造過程之一部分。使用外塗 層亦使跡線22及24與頂部散熱片40相隔離。接著，外塗層 可由諸如熱介面材料之高溫黏著劑覆蓋，該熱介面材料可 由結合基板20b及頂部散熱片40之熱固性物製得。 圖8及圖9中說明了未使用通孔之其它實施例。如圖8中 所說明，導電跡線22及24可形成或附著至金屬引線39、 41，該等金屬引線自封裝延伸出去或可直接安裝至電路 板。在此實施例中，僅基板2〇b之第一表面21b可包括電絕 緣導熱薄膜48。 圖9說明了一實施例，其中導電跡線22及24沿基板2〇b之 側壁向下延伸以接觸基板2013之第二表面上之結合墊34及 38。此組態可允許無需使用金屬引線或通孔而直接將封裝 女裝至電路板。 如圖10A及圖10B中所說明，可組態基板2〇b以使其包括 諸如離散基納二極體65、電阻網路67、其它電子元件或此 等之任意組合之電子電路。可將此等電子電路連接於可作 為陽極/或陰極元件操作之跡線22與24之間。該電子電路 可用於多種目的，例如用以防止靜電放電（ESD)或過電壓 保4或兩者皆可。在例示性實例中，如圖丨〇B中說明之連 接於跡線22與24之間的基納二極體D1 65可防止將過大 157582.doc -17· 201212297 電壓施加至安裝於基板20b上之光電裝置。類似地，諸如 印刷電阻S7之電阻網路67可為安裝於基板2〇上之裝置提供 ESD保護。 如前所述，本發明之新穎及其優於當前技術之優點是顯 而易見的。儘管上文描述及說明了本發明之特定實施例， 本發明不限於所描述及說明部分之特定形式或配置。舉例 而言，可使用不同組態、尺寸或材料來實施本發明。本發 明受限於以下之申請專利範圍。下文中，為利用35 USC§112之"裝置項或方法項"（"means 〇r steps f〇r")規定所 起草之申請專利範圍係由短語·，裝置+功能"（"means f〇r") 來表現。 【圖式簡單說明】 圖1A為根據本發明之一實施例之半導體晶粒封裝的透視 圖， 圖1B為圖1A之半導體封裝之分解透視圖； 圖2A為圖1A之半導體封裝之一部分的俯視圖； 圖2B為圖1A之半導體封裝之一部分的側視圖； 圖2C為圖1A之半導體封裝之一部分的前視圖； 圖2D為圖1A之半導體封裝之一部分的仰視圖； 圖3為圖1A之半導體封裝部分之剖示側視圖； 圖4為具有附加元件之圖1 a之半導體封裝之側視圖； 圖5為根據本發明之另一實施例之半導體晶粒封裝之分 解透視圖； 圖όΑ為圖5之半導體封裝之一部分的俯視圖； 157582.doc -18- 201212297 圖6B為圓5之半導體封裝之—部分的側視圖； 圖6C為圖5之半導體封裝之—部分的前視圖； 圖6D為圖5之半導體封裝之一部分的仰視圖； 圖7A為根據本發明之另-實施例之半導體封裝之-部分 的俯視圖； 圖7B為圖7A之半導體封裝之部分的前視圖； 圖7C為圖7A中沿線A_A所取之半導體封裝之部分的剖示 前視圖； 圖8為根據本發明之另一實施例之半導體封裝之一部分 的側視圖； 圖9為根據本發明之另一實施例之半導體封裝之一部分 的側視圖； 圖10A為根據本發明之另一實施例之半導體封裝之一部 分的俯視圖； 圖1 為根據本發明之另一實施例之半導體封裝之—部 刀的俯視圖。 【主要元件符號說明】 10 發光晶粒封裝 20 基板/底部散熱片 20a 基板 20b 基板 21 基板20之頂面 21b 基板20b之第一表面/頂面/側面 22 跡線 157582.doc •19- 201212297 22a 正跡線 23 半圓筒空間 24 跡線 24a 負跡線 25 四分之一圓筒空間 26 悍墊 27 方位標記 28 安裝墊 29 基板20之底面 29b 基板20b之第二表面/底面/側面 31 凸緣 32 焊墊 33 閉鎖空間 34 結合墊/焊墊 35 支腳 36 熱接觸墊 38 結合墊 39 金屬引線 40 頂部散熱片/反射板 40a 頂部散熱片/反射板 41 金属引線 42 光學反射表面 44 突出部分 45a 通孑L 157582.doc -20- 201212297 45b 通孔 47a 導電跡線 47b 導電跡線 48 薄膜 49 薄膜 50 透鏡 51 金屬板 51a 金屬板51之第一表面 51b 金屬板51之第二表面 52 淺溝槽 60 LED組件 62 LED結合接線 64 LED分組合件 66 發光二極體（LED) 65 離散基納二極體 67 電阻網路 70 外部散熱片 72 散熱片 74 黏著劑 S7 印刷電阻 -21 · 157582.doc

Claims (1)

  1. 201212297 七、申請專利範圍： 1. ·種半導體晶粒封裝’包含* 一基板，其具有一第一表面； 一導熱電絕緣薄膜，其覆蓋該第一表面之至少—部 分； 在該絕緣薄膜上之複數個導電元件，該等導電元件係 藉由該絕緣薄膜與該基板相絕緣；其中該等導電元件之 至少一者包含一安裝墊； 一發光二極體’其安裝至該安裝墊； 一反射器，其耦合至該基板並實質上圍繞該安裝墊及 反射表面且該反射器包 該發光二極體，該反射器定義一 含一複合層形成於其内；及 透鏡’其貫質上覆蓋該安裝$及該發光二極體，並 藉由該反射器之該複合層支標。 ’其中該發光二極體係密 其中該密封體包含一彈 如請求項1之半導體晶粒封裝 封於一密封體内。 如請求項2之半導體晶粒封裝 性材料。 其中該基板包含一電絕 如請求項1之半導體晶粒封裝， 緣材料。
    J57582.doc 其進一步包含一耦合至 裝’其中該基板包含具有一 與該外部散熱片耦合。 201212297 7. 如請求項1之半導體晶粒封裝，其中該等導電元件之至 少一者自該基板之一頂部表面延伸至該基板之一側。 8. 如請求項1之半導體晶粒封裝，其中該基板包含複數個 凸緣’其沿著本身之至少一側與該反射器機械性地接 合。 9. 如請求項1之半導體晶粒封裝，其中該反射器係由具高 導熱性之一材料所組成。 10. 如請求項1之半導體晶粒封裝，其中該反射器包含複數 個支腳’其與該基板機械地接合，用以增加熱接觸區 域。 11. 如請求項1之半導體晶粒封裝，其中該透鏡係由選自以 下之一群組之一材料所構成：玻璃、石英及一高溫塑膠 材料。 12. 如請求項1之半導體晶粒封裝，其中該透鏡包含發光轉 換磷光體。 13. 如请求項1之半導體晶粒封裝，其中該透鏡包含一光學 擴散劑。 14. 如請求項1之半導體晶粒封裝，其中該透鏡包含一磷光 體。 15. 如請求項1之半導體晶粒封裝，其中該透鏡包含選自一 包含玻璃及石英之群組之一材料。 16·如請求項1之半導體晶粒封裝，其中該透鏡係由一高透 明塑膠材料組成。 17 · 士吻求項1之半導體晶粒封裝，其中該反射器及該基板 157582.doc 201212297 在封裝操作期間作為相關之頂部及底部散熱片以自該發 光二極體移除熱。 18. 如請求項1之半導體晶粒封裝，其中該反射器圍繞該安 裝墊而留下該基板之該頂部表面之其他部分及利用部份 定義一光學腔之該反射器來曝光之該等導電元件之部 分。 19. 一種半導體晶粒封裝，包含： 一基板，其具有一第一表面； 一導熱電絕緣薄膜’其覆蓋該第一基板之至少一部 分； 在該絕緣薄膜上之複數個導電元件，該等導電元件係 錯由§亥絕緣薄膜與該基板相絕緣；其中該等導電元件之 至少一者包含一安裝塾； 一發光二極體，其安裝至該安裝墊； 一反射器，其耦合至該基板並實質上圍繞該安裝墊及 該發光二極體，該反射器定義一反射表面且該發光二極 體係密封於一密體内；及 一透鏡’其實質上覆蓋該安裝墊及該發光二極體，其 中該透鏡係置於該密封體並緊貼該密封體，俾使該透鏡 係安置於該密封體上。 20. 如請求項19之半導體晶粒封裝，其中該反射器圍繞該安 裝墊而留下該基板之該頂部表面之其他部分及利用部份 疋義一光學腔之該反射器來曝光之該等導電元件之部分 時。 157582.doc
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