MX170655B - Metodo y dispositivo de circuito para recuperar una señal de sincronizacion de bitio, a partir de una señal de comunicacion recibida - Google Patents
Metodo y dispositivo de circuito para recuperar una señal de sincronizacion de bitio, a partir de una señal de comunicacion recibidaInfo
- Publication number
- MX170655B MX170655B MX016197A MX1619789A MX170655B MX 170655 B MX170655 B MX 170655B MX 016197 A MX016197 A MX 016197A MX 1619789 A MX1619789 A MX 1619789A MX 170655 B MX170655 B MX 170655B
- Authority
- MX
- Mexico
- Prior art keywords
- signal
- counter
- bit
- frequency
- synchronization signal
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 3
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
- H03L7/0993—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider and a circuit for adding and deleting pulses
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Communication Control (AREA)
- Luminescent Compositions (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Electrophonic Musical Instruments (AREA)
- Separation Of Suspended Particles By Flocculating Agents (AREA)
- Dc Digital Transmission (AREA)
- Manipulation Of Pulses (AREA)
- Mobile Radio Communication Systems (AREA)
- Television Systems (AREA)
Abstract
La presente invención se refiere a método para recuperar una sincronización de bitio a partir de una señal de comunicación digital recibida, en donde un generador de señal de sincronización o de reloj en el extremo receptor general una señal de reloj de referencia cuya frecuencia es N veces la frecuencia de la señal de sincronización de bitio, en donde un contador que opera como un divisor de frecuencias y que tiene por lo menos N estados de cuenta, es incrementado cíclicamente por la señal de reloj de referencia, a fin de dividir la señal de reloj de referencia a la frecuencia de la señal de sincronización de bitio, que se entrega en una de sus salidas, en donde el período de la señal de sincronización de bitio es dividida en N porciones de tiempo iguales, y en donde el borde de pulso efectivo de la señal de sincronización de bitio, provista en la salida del contador, ocurre en la cuenta determinada por N/2; caracterizado dicho método porque un lógico evaluador de fase determina las cuentas a las que ocurren el borde delantero y el borde trasero de cada pulso recibido de la señal de comunicación, e independientemente de la duración de un pulso recibido, el lógico evaluador de fase suministra una señal de corrección de fase al contador si el borde de pulso de la señal de sincronización de bitio, provista por el contador, no queda en el centro del pulso recibido de la señal de comunicación.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE3818843A DE3818843A1 (de) | 1988-06-03 | 1988-06-03 | Verfahren und schaltungsanordnung zur rueckgewinnung eines bittaktes aus einem empfangenen digitalen nachrichtensignal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| MX170655B true MX170655B (es) | 1993-09-03 |
Family
ID=6355738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| MX016197A MX170655B (es) | 1988-06-03 | 1989-05-26 | Metodo y dispositivo de circuito para recuperar una señal de sincronizacion de bitio, a partir de una señal de comunicacion recibida |
Country Status (14)
| Country | Link |
|---|---|
| US (1) | US5025461A (es) |
| EP (1) | EP0345564B1 (es) |
| JP (1) | JPH0761067B2 (es) |
| CN (1) | CN1011460B (es) |
| AT (1) | ATE117482T1 (es) |
| AU (1) | AU614138B2 (es) |
| CA (1) | CA1308448C (es) |
| DE (2) | DE3818843A1 (es) |
| ES (1) | ES2070143T3 (es) |
| FI (1) | FI97584C (es) |
| MX (1) | MX170655B (es) |
| NO (1) | NO180138C (es) |
| PT (1) | PT90723A (es) |
| ZA (1) | ZA894069B (es) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW255079B (en) * | 1994-09-30 | 1995-08-21 | At & T Corp | Communications unit with data and clock recovery circuit |
| JPH0923220A (ja) * | 1995-05-05 | 1997-01-21 | Philips Electron Nv | クロック信号回復用の回路、制御ループ及びそれらからなる送信システム |
| US6522188B1 (en) | 1998-04-10 | 2003-02-18 | Top Layer Networks, Inc. | High-speed data bus for network switching |
| US7002982B1 (en) * | 1998-07-08 | 2006-02-21 | Broadcom Corporation | Apparatus and method for storing data |
| FR2781943B1 (fr) | 1998-07-30 | 2000-09-15 | Thomson Multimedia Sa | Procede de recuperation d'horloge lors de l'echantillonnage de signaux de type numerique |
| US6343364B1 (en) * | 2000-07-13 | 2002-01-29 | Schlumberger Malco Inc. | Method and device for local clock generation using universal serial bus downstream received signals DP and DM |
| US6862332B2 (en) | 2001-02-27 | 2005-03-01 | Toa Corporation | Clock reproduction circuit |
| US6888905B1 (en) | 2001-12-20 | 2005-05-03 | Microtune (San Diego), Inc. | Low deviation index demodulation scheme |
| JP3949081B2 (ja) * | 2003-06-09 | 2007-07-25 | 株式会社東芝 | サンプリング周波数変換装置 |
| US7135905B2 (en) * | 2004-10-12 | 2006-11-14 | Broadcom Corporation | High speed clock and data recovery system |
| EP1813029B1 (en) * | 2004-11-12 | 2009-04-22 | Analog Devices, Inc. | Timing system and method for a wireless transceiver system |
| CN100397356C (zh) * | 2004-12-17 | 2008-06-25 | 上海环达计算机科技有限公司 | Pci测试卡及其测试方法 |
| US8705680B2 (en) * | 2006-06-29 | 2014-04-22 | Nippon Telegraph And Telephone Corporation | CDR circuit |
| KR101381359B1 (ko) * | 2006-08-31 | 2014-04-04 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 클록 생성 회로 및 이 클록 생성 회로를 구비한 반도체장치 |
| DE102007002302A1 (de) * | 2007-01-16 | 2008-07-24 | Austriamicrosystems Ag | Anordnung und Verfahren zur Rückgewinnung eines Trägersignals und Demodulationseinrichtung |
| US7719256B1 (en) * | 2008-03-20 | 2010-05-18 | The United States Of America As Represented By The Secretary Of The Navy | Method for determining a separation time |
| US20160112223A1 (en) * | 2013-05-10 | 2016-04-21 | Mitsubishi Electric Corporation | Signal processing device |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3668315A (en) * | 1970-05-15 | 1972-06-06 | Hughes Aircraft Co | Receiver timing and synchronization system |
| US3697689A (en) * | 1970-12-23 | 1972-10-10 | North American Rockwell | Fine timing recovery system |
| DE2354103A1 (de) * | 1973-10-29 | 1975-05-07 | Siemens Ag | Schaltungsanordnung zur regelung der phasenlage eines taktsignals |
| DE2435687C3 (de) * | 1974-07-24 | 1979-06-07 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Schaltungsanordnung zum Empfangen von isochron binär modulierten Signalen in Fernmeldeanlagen |
| JPS5541074A (en) * | 1978-09-19 | 1980-03-22 | Fujitsu Ltd | Timing pick up system |
| DE2935353A1 (de) * | 1979-09-01 | 1981-03-19 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Einrichtung zum synchronisieren des empfangsbittaktes eines datenempfaengers entsprechend den bituebergaengen des datensignals |
| US4546394A (en) * | 1982-01-29 | 1985-10-08 | Sansui Electric Co., Ltd. | Signal reconstruction circuit for digital signals |
| JPS59143444A (ja) * | 1983-02-04 | 1984-08-17 | Hitachi Ltd | デイジタルフエ−ズロツクドル−プ回路 |
| US4535461A (en) * | 1983-06-01 | 1985-08-13 | Cincinnati Electronics Corporation | Digital clock bit synchronizer |
| JPS60251741A (ja) * | 1984-05-28 | 1985-12-12 | Fujitsu Ltd | 識別回路 |
| DE3679351D1 (de) * | 1985-05-15 | 1991-06-27 | Siemens Ag | Schaltungsanordnung zur rueckgewinnung des taktes eines isochronen binaersignales. |
| IT1222405B (it) * | 1987-07-30 | 1990-09-05 | Gte Telecom Spa | Estrattore digitale di segnale orologio con aggancio e correzione di fase per segnali bipolari |
| US4789996A (en) * | 1988-01-28 | 1988-12-06 | Siemens Transmission Systems, Inc. | Center frequency high resolution digital phase-lock loop circuit |
| US4896337A (en) * | 1988-04-08 | 1990-01-23 | Ampex Corporation | Adjustable frequency signal generator system with incremental control |
-
1988
- 1988-06-03 DE DE3818843A patent/DE3818843A1/de not_active Withdrawn
-
1989
- 1989-05-22 AU AU35024/89A patent/AU614138B2/en not_active Ceased
- 1989-05-26 AT AT89109517T patent/ATE117482T1/de active
- 1989-05-26 DE DE58908897T patent/DE58908897D1/de not_active Expired - Lifetime
- 1989-05-26 MX MX016197A patent/MX170655B/es unknown
- 1989-05-26 EP EP89109517A patent/EP0345564B1/de not_active Expired - Lifetime
- 1989-05-26 ES ES89109517T patent/ES2070143T3/es not_active Expired - Lifetime
- 1989-05-29 ZA ZA894069A patent/ZA894069B/xx unknown
- 1989-05-29 NO NO892151A patent/NO180138C/no unknown
- 1989-05-31 FI FI892643A patent/FI97584C/fi not_active IP Right Cessation
- 1989-06-02 JP JP14092589A patent/JPH0761067B2/ja not_active Expired - Lifetime
- 1989-06-02 PT PT90723A patent/PT90723A/pt not_active Application Discontinuation
- 1989-06-02 CN CN89103670A patent/CN1011460B/zh not_active Expired
- 1989-06-02 CA CA000601616A patent/CA1308448C/en not_active Expired - Lifetime
- 1989-06-05 US US07/362,802 patent/US5025461A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5025461A (en) | 1991-06-18 |
| ATE117482T1 (de) | 1995-02-15 |
| AU614138B2 (en) | 1991-08-22 |
| ES2070143T3 (es) | 1995-06-01 |
| FI892643A0 (fi) | 1989-05-31 |
| CN1011460B (zh) | 1991-01-30 |
| ZA894069B (en) | 1990-09-26 |
| FI97584B (fi) | 1996-09-30 |
| EP0345564A2 (de) | 1989-12-13 |
| NO180138B (no) | 1996-11-11 |
| FI97584C (fi) | 1997-01-10 |
| EP0345564B1 (de) | 1995-01-18 |
| NO892151D0 (no) | 1989-05-29 |
| DE58908897D1 (de) | 1995-03-02 |
| CN1038736A (zh) | 1990-01-10 |
| NO180138C (no) | 1997-02-19 |
| PT90723A (pt) | 1989-12-29 |
| AU3502489A (en) | 1989-12-07 |
| NO892151L (no) | 1989-12-04 |
| JPH0250643A (ja) | 1990-02-20 |
| CA1308448C (en) | 1992-10-06 |
| FI892643A (fi) | 1989-12-04 |
| EP0345564A3 (de) | 1991-04-10 |
| DE3818843A1 (de) | 1989-12-07 |
| JPH0761067B2 (ja) | 1995-06-28 |
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