JP2011109080A - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP2011109080A JP2011109080A JP2010235083A JP2010235083A JP2011109080A JP 2011109080 A JP2011109080 A JP 2011109080A JP 2010235083 A JP2010235083 A JP 2010235083A JP 2010235083 A JP2010235083 A JP 2010235083A JP 2011109080 A JP2011109080 A JP 2011109080A
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- film
- oxide semiconductor
- conductive film
- insulating film
- electrode
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Abstract
【解決手段】絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、酸化物半導体膜上に、チタン、モリブデンまたはタングステンを含む第1の導電膜を形成し、第1の導電膜上に、電気陰性度が水素より低い金属を含む第2の導電膜を形成し、第1の導電膜及び第2の導電膜をエッチングすることでソース電極及びドレイン電極を形成し、酸化物半導体膜、ソース電極及びドレイン電極上に、酸化物半導体膜と接する絶縁膜を形成する半導体装置の作製方法。
【選択図】図1
Description
チャネルエッチ構造のボトムゲート型の薄膜トランジスタを例に挙げ、半導体装置の作製方法について図1乃至図3を用いて説明する。
チャネルエッチ構造のボトムゲート型の薄膜トランジスタを例に挙げ、半導体装置の作製方法について図4を用いて説明する。
チャネルエッチ構造のボトムゲート型の薄膜トランジスタを例に挙げ、半導体装置の作製方法について図5を用いて説明する。
チャネルエッチ構造のボトムゲート型の薄膜トランジスタを例に挙げ、半導体装置の作製方法について図6を用いて説明する。
本実施の形態では、チャネル保護構造のボトムゲート型の薄膜トランジスタを例に挙げ、半導体装置の作製方法について図7、図8及び図9を用いて説明する。なお、実施の形態1と同一部分又は同様な機能を有する部分、及び工程は、実施の形態1と同様に行うことができるため、繰り返しの説明は省略する。
本実施の形態では、ボトムコンタクト型の薄膜トランジスタを例に挙げ、半導体装置の作製方法について図10及び図11を用いて説明する。なお、実施の形態1と同一部分又は同様な機能を有する部分、及び工程は、実施の形態1と同様に行うことができるため、繰り返しの説明は省略する。
本実施の形態では、本発明の一態様に係る半導体表示装置の作製方法について、図12乃至図17を用いて説明する。
本実施の形態では、本発明の作製方法を用いて形成される半導体表示装置の一つである、電子ペーパー或いはデジタルペーパーと呼ばれる半導体表示装置の構成について説明する。
アクティブマトリクス型の半導体表示装置のブロック図の一例を図19(A)に示す。表示装置の基板5300上には、画素部5301、第1の走査線駆動回路5302、第2の走査線駆動回路5303、信号線駆動回路5304を有する。画素部5301には、複数の信号線が信号線駆動回路5304から延伸して配置され、複数の走査線が第1の走査線駆動回路5302、及び第2の走査線駆動回路5303から延伸して配置されている。なお走査線と信号線との交差領域には、各々、表示素子を有する画素がマトリクス状に配置されている。また、表示装置の基板5300はFPC(Flexible Printed Circuit)等の接続部を介して、タイミング制御回路5305(コントローラ、制御ICともいう)に接続されている。
本発明の一態様に係る液晶表示装置は、移動度及びオン電流が高く、なおかつ信頼性の高い薄膜トランジスタを用いているため、コントラスト及び視認性が高い。本実施の形態では、本発明の一態様に係る液晶表示装置の構成について説明する。
本実施の形態では、本発明の一態様に係る薄膜トランジスタを画素に用いた、発光装置の構成について説明する。本実施の形態では、発光素子を駆動させるためのトランジスタがn型の場合における、画素の断面構造について、図25を用いて説明する。なお図25では、第1の電極が陰極、第2の電極が陽極の場合について説明するが、第1の電極が陽極、第2の電極が陰極であっても良い。
11 配線
12 配線
13 配線
14 配線
15 配線
21 入力端子
22 入力端子
23 入力端子
24 入力端子
25 入力端子
26 出力端子
27 出力端子
31 トランジスタ
32 トランジスタ
33 トランジスタ
34 トランジスタ
35 トランジスタ
36 トランジスタ
37 トランジスタ
38 トランジスタ
39 トランジスタ
40 トランジスタ
41 トランジスタ
42 トランジスタ
43 トランジスタ
51 電源線
52 電源線
53 電源線
100 基板
101 ゲート電極
102 ゲート絶縁膜
103 酸化物半導体膜
104 酸化物半導体膜
105a 導電膜
105b 導電膜
105c 導電膜
105d 導電膜
105e 導電膜
106 ソース電極
107 ドレイン電極
108 酸化物半導体膜
109 絶縁膜
110 トランジスタ
111 バックゲート電極
112 絶縁膜
120 薄膜トランジスタ
126 ソース電極
127 ドレイン電極
128 酸化物半導体膜
129 絶縁膜
130 薄膜トランジスタ
136 ソース電極
137 ドレイン電極
138 酸化物半導体膜
139 絶縁膜
140 薄膜トランジスタ
146 ソース電極
147 ドレイン電極
148 酸化物半導体膜
149 絶縁膜
300 基板
301 ゲート電極
302 ゲート絶縁膜
303 酸化物半導体膜
304 酸化物半導体膜
305a 導電膜
305b 導電膜
306 ソース電極
307 ドレイン電極
309 絶縁膜
310 薄膜トランジスタ
311 チャネル保護膜
312 バックゲート電極
313 絶縁膜
400 基板
401 ゲート電極
402 ゲート絶縁膜
403 酸化物半導体膜
404 酸化物半導体膜
405a 導電膜
405b 導電膜
406 ソース電極
407 ドレイン電極
409 絶縁膜
410 薄膜トランジスタ
700 画素部
701 信号線駆動回路
702 走査線駆動回路
703 画素
704 トランジスタ
705 表示素子
706 保持容量
707 信号線
708 走査線
710 画素電極
711 対向電極
712 マイクロカプセル
713 ドレイン電極
714 樹脂
800 基板
801 ゲート電極
802 ゲート絶縁膜
803 酸化物半導体膜
804 酸化物半導体膜
805 酸化物半導体膜
806 導電膜
806a 導電膜
806b 導電膜
807 ソース電極
808 ドレイン電極
809 絶縁膜
813 薄膜トランジスタ
814 画素電極
815 透明導電膜
816 透明導電膜
819 保持容量
820 端子
821 端子
822 容量配線
1401 薄膜トランジスタ
1402 ゲート電極
1403 ゲート絶縁膜
1404 酸化物半導体膜
1406a 導電膜
1406b 導電膜
1407 絶縁膜
1408 絶縁膜
1410 画素電極
1411 配向膜
1413 対向電極
1414 配向膜
1415 液晶
1416 シール材
1417 スペーサ
1420 基板
1601 液晶パネル
1602 拡散板
1603 プリズムシート
1604 拡散板
1605 導光板
1606 反射板
1607 光源
1608 回路基板
1609 FPC
1610 FPC
5300 基板
5301 画素部
5302 走査線駆動回路
5303 走査線駆動回路
5304 信号線駆動回路
5305 タイミング制御回路
5601 シフトレジスタ
5602 サンプリング回路
5603 トランジスタ
5604 配線
5605 配線
6031 トランジスタ
6033 発光素子
6034 電極
6035 電界発光層
6036 電極
6037 絶縁膜
6038 隔壁
6041 トランジスタ
6043 発光素子
6044 電極
6045 電界発光層
6046 電極
6047 絶縁膜
6048 隔壁
6051 トランジスタ
6053 発光素子
6054 電極
6055 電界発光層
6056 電極
6057 絶縁膜
6058 隔壁
7001 筐体
7002 表示部
7011 筐体
7012 表示部
7013 支持台
7021 筐体
7022 表示部
7031 筐体
7032 筐体
7033 表示部
7034 表示部
7035 マイクロホン
7036 スピーカー
7037 操作キー
7038 スタイラス
7041 筐体
7042 表示部
7043 音声入力部
7044 音声出力部
7045 操作キー
7046 受光部
Claims (12)
- 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜上に、チタン、モリブデンまたはタングステンを含む第1の導電膜を形成し、
前記第1の導電膜上に、電気陰性度が水素より低い金属を含む第2の導電膜を形成し、
前記第1の導電膜及び前記第2の導電膜をエッチングすることでソース電極及びドレイン電極を形成し、
前記酸化物半導体膜、前記ソース電極及び前記ドレイン電極上に、前記酸化物半導体膜と接する絶縁膜を形成する半導体装置の作製方法。 - 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜上に、チタン、モリブデンまたはタングステンを含む第1の導電膜を形成し、
前記第1の導電膜上に、電気陰性度が水素より低い金属を含む第2の導電膜を形成し、
前記第2の導電膜が露出した状態で、不活性雰囲気下において加熱処理を施し、
前記第1の導電膜及び前記第2の導電膜をエッチングすることでソース電極及びドレイン電極を形成し、
前記酸化物半導体膜、前記ソース電極及び前記ドレイン電極上に、前記酸化物半導体膜と接する絶縁膜を形成する半導体装置の作製方法。 - 請求項2において、前記加熱処理は、200℃以上450℃以下で行う半導体装置の作製方法。
- 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜上に、チタン、モリブデンまたはタングステンを含む第1の導電膜を形成し、
前記第1の導電膜上に、電気陰性度が水素より低い金属を含む第2の導電膜を形成し、
前記第2の導電膜をエッチングにより除去した後、電気陰性度が水素より低い金属を含む第3の導電膜を形成し、
前記第1の導電膜及び前記第3の導電膜をエッチングすることでソース電極及びドレイン電極を形成し、
前記酸化物半導体膜、前記ソース電極及び前記ドレイン電極上に、前記酸化物半導体膜と接する絶縁膜を形成する半導体装置の作製方法。 - 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜上に、チタン、モリブデンまたはタングステンを含む第1の導電膜を形成し、
前記第1の導電膜上に、電気陰性度が水素より低い金属を含む第2の導電膜を形成し、
前記第2の導電膜が露出した状態で、不活性雰囲気下において加熱処理を施し、
前記第2の導電膜をエッチングにより除去した後、電気陰性度が水素より低い金属を含む第3の導電膜を形成し、
前記第1の導電膜及び前記第3の導電膜をエッチングすることでソース電極及びドレイン電極を形成し、
前記酸化物半導体膜、前記ソース電極及び前記ドレイン電極上に、前記酸化物半導体膜と接する絶縁膜を形成する半導体装置の作製方法。 - 請求項5において、前記加熱処理は、200℃以上450℃以下で行う半導体装置の作製方法。
- 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜上に、チタン、モリブデンまたはタングステンを含む第1の導電膜を形成し、
前記第1の導電膜上に、電気陰性度が水素より低い金属を含む第2の導電膜を形成し、
前記第2の導電膜をエッチングにより除去した後、電気陰性度が水素より低い金属を含む第3の導電膜を形成し、
前記第3の導電膜上に、チタン、モリブデンまたはタングステンを含む第4の導電膜を形成し、
前記第1の導電膜、前記第3の導電膜及び前記第4の導電膜をエッチングすることでソース電極及びドレイン電極を形成し、
前記酸化物半導体膜、前記ソース電極及び前記ドレイン電極上に、前記酸化物半導体膜と接する絶縁膜を形成する半導体装置の作製方法。 - 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜上に、チタン、モリブデンまたはタングステンを含む第1の導電膜を形成し、
前記第1の導電膜上に、電気陰性度が水素より低い金属を含む第2の導電膜を形成し、
前記第2の導電膜が露出した状態で、不活性雰囲気下において加熱処理を施し、
前記第2の導電膜をエッチングにより除去した後、電気陰性度が水素より低い金属を含む第3の導電膜を形成し、
前記第3の導電膜上に、チタン、モリブデンまたはタングステンを含む第4の導電膜を形成し、
前記第1の導電膜、前記第3の導電膜及び前記第4の導電膜をエッチングすることでソース電極及びドレイン電極を形成し、
前記酸化物半導体膜、前記ソース電極及び前記ドレイン電極上に、前記酸化物半導体膜と接する絶縁膜を形成する半導体装置の作製方法。 - 請求項8において、前記加熱処理は、200℃以上450℃以下で行う半導体装置の作製方法。
- 請求項1乃至請求項9のいずれか1項において、前記電気陰性度が水素より低い金属は、アルミニウムまたはマグネシウムである半導体装置の作製方法。
- 請求項1乃至請求項10のいずれか1項において、前記絶縁膜は、酸化珪素または酸化窒化珪素を含む第1の絶縁膜と、窒化珪素、窒化酸化珪素、窒化アルミニウム、または窒化酸化アルミニウムを含む第2の絶縁膜とが順に積層された構造を有している半導体装置の作製方法。
- 請求項1乃至請求項11のいずれか1項において、前記ゲート絶縁膜は、窒化珪素、窒化酸化珪素、窒化アルミニウム、または窒化酸化アルミニウムを含む第1のゲート絶縁膜と、酸化珪素または酸化窒化珪素を含む第2のゲート絶縁膜とが順に積層された構造を有している半導体装置の作製方法。
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