JP2011014758A - リードフレーム及びこれを用いた電子部品 - Google Patents
リードフレーム及びこれを用いた電子部品 Download PDFInfo
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- JP2011014758A JP2011014758A JP2009158460A JP2009158460A JP2011014758A JP 2011014758 A JP2011014758 A JP 2011014758A JP 2009158460 A JP2009158460 A JP 2009158460A JP 2009158460 A JP2009158460 A JP 2009158460A JP 2011014758 A JP2011014758 A JP 2011014758A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】本発明に係るリードフレーム1は、ICチップが配置されるダイパッド2と、ICチップと外部素子との電気的接続を中継するリード3と、ダイパッド2の辺部15に形成された突起部4とを備える。また、突起部4は、ICチップ又は外部素子の空き端子処理におけるボンディングポイントとして利用されると共に、ICチップをダイパッド2上に配置する際の位置決めの基準として利用される。
【選択図】図1
Description
以下、図面を参照して本発明の実施の形態について説明する。図1は、本実施の形態に係るリードフレーム1の構造を示している。リードフレーム1は、各種電子部品の内部配線として用いられ、銅合金、鉄ニッケル合金等からなる薄板であり、ダイパッド2、リード3、突起部4を備えている。
図3及び図4は、上記リードフレーム1の使用状態を例示している。図3は、ダイパッド2上にICチップ21を配置した状態(マウント工程後)を示している。図4は、ダイパッド2上に配置されたICチップ21の端子とリード3とをボンディングワイヤ24により接続した状態(ボンディング工程後)を示している。
図5及び図6は、上記リードフレーム1の他の使用状態を例示している。図5は、ダイパッド2上にICチップ31を配置した状態(マウント工程後)を示している。図6は、ダイパッド2上に配置されたICチップ31の端子とリード3とをボンディングワイヤ24により接続した状態(ボンディング工程後)を示している。
図7及び図8は、上記リードフレーム1の他の使用状態を例示している。図7は、ダイパッド2上にICチップ41,42を配置した状態(マウント工程後)を示している。図8は、ダイパッド2上に配置されたICチップ41,42の端子とリード3とをボンディングワイヤ24により接続した状態(ボンディング工程後)を示している。
2 ダイパッド
3 リード
4 突起部
11 フレーム部
15 辺部
21,31,41,42 ICチップ
24 ボンディングワイヤ
25 第1のダイパッドボンディングポイント
26 第2のダイパッドボンディングポイント
27 第3のダイパッドボンディングポイント
Claims (6)
- ICチップが配置されるダイパッドと、
前記ICチップと外部素子との電気的接続を中継するリードと、
前記ダイパッドの辺部に形成された突起部と、
を備えるリードフレーム。 - 前記突起部は、前記ICチップ又は前記外部素子の空き端子処理におけるボンディングポイントとして利用される、
請求項1記載のリードフレーム。 - 前記突起部は、前記ICチップを前記ダイパッド上に配置する際の位置決めの基準して利用される、
請求項1又は2記載のリードフレーム。 - 前記突起部は、1つの前記辺部に複数且つ等間隔に配置される、
請求項3記載のリードフレーム。 - 前記リードは、該リードと前記辺部との間、及び該リードと前記突起部との間に、一定値以上の隙間が確保可能な形状を有する、
請求項1〜4のいずれか1つに記載のリードフレーム。 - 少なくとも1つのICチップがリードフレームに搭載された電子部品であって、
前記リードフレームは、
前記ICチップが配置されるダイパッドと、
前記ICチップと外部素子との電気的接続を中継するリードと、
前記ダイパッドの辺部に形成された突起部とを備え、
前記ICチップ又は外部素子の空き端子と、前記突起部とが電気的に接続されている、
電子部品。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009158460A JP2011014758A (ja) | 2009-07-03 | 2009-07-03 | リードフレーム及びこれを用いた電子部品 |
US12/783,857 US20110001226A1 (en) | 2009-07-03 | 2010-05-20 | Lead frame, and electronic part using the same |
CN2010102131339A CN101944522A (zh) | 2009-07-03 | 2010-06-22 | 引线框架及使用引线框架的电子部件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009158460A JP2011014758A (ja) | 2009-07-03 | 2009-07-03 | リードフレーム及びこれを用いた電子部品 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011014758A true JP2011014758A (ja) | 2011-01-20 |
JP2011014758A5 JP2011014758A5 (ja) | 2012-04-05 |
Family
ID=43412184
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009158460A Pending JP2011014758A (ja) | 2009-07-03 | 2009-07-03 | リードフレーム及びこれを用いた電子部品 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20110001226A1 (ja) |
JP (1) | JP2011014758A (ja) |
CN (1) | CN101944522A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2024062819A1 (ja) * | 2022-09-22 | 2024-03-28 | 株式会社オートネットワーク技術研究所 | 車両用回路基板 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5762548A (en) * | 1980-10-01 | 1982-04-15 | Nec Corp | Semiconductor device |
JPH0263553U (ja) * | 1988-11-02 | 1990-05-11 | ||
JPH045656U (ja) * | 1990-04-28 | 1992-01-20 | ||
JPH06318667A (ja) * | 1993-05-10 | 1994-11-15 | Nec Kansai Ltd | 半導体装置 |
JPH0745778A (ja) * | 1993-07-29 | 1995-02-14 | Sumitomo Electric Ind Ltd | リードフレーム及び半導体装置 |
JPH1140721A (ja) * | 1997-07-15 | 1999-02-12 | Matsushita Electron Corp | リードフレーム、半導体装置およびそれらの製造方法 |
JP2000236060A (ja) * | 1999-02-16 | 2000-08-29 | Matsushita Electronics Industry Corp | 半導体装置 |
JP2002093987A (ja) * | 2000-09-13 | 2002-03-29 | Sharp Takaya Denshi Kogyo Kk | 認識パターン付リードフレーム |
JP2002110889A (ja) * | 2000-09-28 | 2002-04-12 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2005243902A (ja) * | 2004-02-26 | 2005-09-08 | Matsushita Electric Ind Co Ltd | 半導体装置および半導体装置の製造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0373560A (ja) * | 1989-08-14 | 1991-03-28 | Nec Corp | 半導体装置 |
KR0149798B1 (ko) * | 1994-04-15 | 1998-10-01 | 모리시다 요이치 | 반도체 장치 및 그 제조방법과 리드프레임 |
US20080079124A1 (en) * | 2006-10-03 | 2008-04-03 | Chris Edward Haga | Interdigitated leadfingers |
-
2009
- 2009-07-03 JP JP2009158460A patent/JP2011014758A/ja active Pending
-
2010
- 2010-05-20 US US12/783,857 patent/US20110001226A1/en not_active Abandoned
- 2010-06-22 CN CN2010102131339A patent/CN101944522A/zh active Pending
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5762548A (en) * | 1980-10-01 | 1982-04-15 | Nec Corp | Semiconductor device |
JPH0263553U (ja) * | 1988-11-02 | 1990-05-11 | ||
JPH045656U (ja) * | 1990-04-28 | 1992-01-20 | ||
JPH06318667A (ja) * | 1993-05-10 | 1994-11-15 | Nec Kansai Ltd | 半導体装置 |
JPH0745778A (ja) * | 1993-07-29 | 1995-02-14 | Sumitomo Electric Ind Ltd | リードフレーム及び半導体装置 |
JPH1140721A (ja) * | 1997-07-15 | 1999-02-12 | Matsushita Electron Corp | リードフレーム、半導体装置およびそれらの製造方法 |
JP2000236060A (ja) * | 1999-02-16 | 2000-08-29 | Matsushita Electronics Industry Corp | 半導体装置 |
JP2002093987A (ja) * | 2000-09-13 | 2002-03-29 | Sharp Takaya Denshi Kogyo Kk | 認識パターン付リードフレーム |
JP2002110889A (ja) * | 2000-09-28 | 2002-04-12 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2005243902A (ja) * | 2004-02-26 | 2005-09-08 | Matsushita Electric Ind Co Ltd | 半導体装置および半導体装置の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2024062819A1 (ja) * | 2022-09-22 | 2024-03-28 | 株式会社オートネットワーク技術研究所 | 車両用回路基板 |
Also Published As
Publication number | Publication date |
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CN101944522A (zh) | 2011-01-12 |
US20110001226A1 (en) | 2011-01-06 |
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