CN101944522A - 引线框架及使用引线框架的电子部件 - Google Patents
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Abstract
本发明涉及引线框架及使用引线框架的电子部件。引线框架包括裸片焊盘,其上安装至少一个IC芯片;多条引线,所述多条引线电气地连接IC芯片和至少一个外部元件;以及多个突起,所述多个突起形成在裸片焊盘的至少一个边缘中。突起用作与IC芯片的至少一个自由端子相连接的至少一个焊接点或者当IC芯片被布置在裸片焊盘上时进行定位的基准。
Description
通过引用引入
本申请基于并且要求2009年7月3日提交的日本专利申请No.2009-158460的优先权,其内容通过引用整体并入这里。
技术领域
本发明涉及其上安装IC(集成电路)芯片的引线框架的结构。
背景技术
引线框架用作各种电子部件中诸如CPU(中央处理单元)、存储器的IC芯片的内部布线。图9示出传统的通常的引线框架101的结构。引线框架101包括其上安装IC芯片102的裸片焊盘103和多条引线104。在本示例中,通过一体地形成有裸片焊盘103的框架部件111支撑每条引线104。在最后的制造工艺切断框架部件111。通过由键合线105连接IC芯片102的端子和特定引线104,并且连接引线104和外部元件来电气地连接IC芯片102和外部元件(其它电子部件、布线等等)。
图10示出制造具有上述引线框架的电子部件的工艺。首先,IC芯片102被布置并且被安装在引线框架101的裸片焊盘103上(安装工艺)。接下来,通过键合线105将引线框架104连接至IC芯片102的端子(焊接工艺)。图9示出其中焊接工艺完成的状态。接下来,通过由模树脂等等制成的封装110密封裸片焊盘103和IC芯片102(密封工艺)。最后,封装110外部的框架部件111被切断,并且延伸在封装110的外部的引线104被形成为具有想要的形状(引线形成工艺)。
在上述焊接工艺中,IC芯片102中的自由端子被处理。IC芯片102通常包括诸如输入端子、输出端子、输入和输出端子等等的多个端子。这些端子中的一些是根据电子部件等等的功能而没有连接至任何地方的自由端子。一些自由端子需要进行处理,诸如接地连接。对于自由端子的处理之一包括通过键合线将自由端子连接至裸片焊盘103的空间的方法。使用裸片焊盘103中的空间执行到裸片焊盘103的焊接。该空间在图9中被示出为裸片焊盘焊接点120。
日本未经审查专利申请公开No.3-73560公布了下述结构,其中当IC芯片被安装在引线框架上时相对于引线框架的XY轴旋转IC芯片的XY轴。此技术使得能够防止IC芯片的角部被集中。
发明内容
然而,当使用图9中所示的传统的引线框架101时,很难在芯片112具有等于裸片焊盘103的面积时,在裸片焊盘103上确保用于提供裸片焊盘焊接点120(参见图9)的空间,如图11中所示。在这样的情况下,必须使用尺寸较大的引线框架或者新设计引线框架。因此很难在各种类型的电子部件当中共同地使用具有同一标准的引线框架,这增加制造成本和制造时间。尽管图11示出其中安装了具有大尺寸的一个IC芯片112的示例,当因为多个IC芯片被安装在多芯片模块中的裸片焊盘103上时在裸片焊盘103上不存在任何空间,因此类似地发生相同的问题。
通过日本未经审查专利申请公开No.3-73560不能够解决此种问题。另外,在日本未经审查专利申请公开No.3-73560中,当安装旋转的芯片或者多个芯片时,很难以较高的精确度安装芯片。
本发明的第一示例性方面是引线框架,该引线框架包括裸片焊盘,其上安装至少一个IC芯片;多条引线,所述多条引线电气地连接IC芯片和至少一个外部元件;以及多个突起,所述多个突起形成在裸片焊盘的至少一个边缘中。
本发明的第二示例性方面是电子部件,该电子部件包括被安装在引线框架上的至少一个IC芯片,该引线框架包括裸片焊盘,其上安装至少一个IC芯片;多条引线,所述多条引线电气地连接IC芯片和至少一个外部元件;以及多个突起,所述多个突起被形成在裸片焊盘的至少一个边缘中,其中外部元件或者IC芯片的至少一个自由端子被电气地连接至突起。
突起被用作裸片焊盘焊接点,IC芯片的定位的基准等。突起从裸片焊盘的边缘往外突起。因此,即使IC芯片具有等于裸片焊盘的面积的大面积,或者多个IC芯片被安装在裸片焊盘上,突起也能够确定地被用于裸片焊盘焊接点。另外,突起能够通过引线用于裸片焊盘焊接点,从而突起不仅能够被连接至被安装在引线框架上的IC芯片的自由端子而且能够被连接至外部元件(被安装在其它电子部件上的IC芯片等)的自由端子。此外,突起可以用作当根据突起的布置、数目、形状等等将IC芯片安装在裸片焊盘上时进行定位的基准。
根据本发明,即使IC芯片具有等于裸片焊盘的面积,也能够确定地确保用于裸片焊盘焊接的空间。因此,具有大面积的IC芯片或者大量的IC芯片能够被安装在裸片焊盘上而无需考虑用于裸片焊盘焊接的空间。另外,在各种电子部件当中能够广泛地共同使用具有同一标准的引线框架,这减少了制造成本、制造时间等等。此外,使用突起作为用于当IC芯片被安装在裸片焊盘上时进行定位的基准能够以较高的精确度安装IC芯片。
附图说明
结合附图,根据某些示例性实施例的以下描述,以上和其它示例性方面、优点和特征将更加明显,其中:
图1是示出本发明的第一示例性实施例的引线框架的结构的视图;
图2是示出第一实施例的引线框架中的边缘、突起以及引线当中的间隙的部分放大图;
图3是示出第一示例性实施例的第一示例中安装工艺之后的引线框架的状态的视图;
图4是示出第一示例中焊接工艺之后的引线框架的状态的视图;
图5是示出第一示例性实施例的第二示例中安装工艺之后的引线框架的状态的视图;
图6是第二示例中焊接工艺之后的引线框架的状态的视图;
图7是示出第一示例性实施例的第三示例中安装工艺之后的引线框架的状态的视图;
图8是示出第三示例中的焊接工艺之后的引线框架的状态的视图;
图9是示出背景技术的一个示例的引线框架的使用状态和结构的视图,
图10是示出生产背景技术的电子部件的通常工艺的视图;以及
图11是示出背景技术的另一示例的引线框架的使用状态的视图。
具体实施方式
[第一示例性实施例]
接下来,参考附图解释本发明的第一示例性实施例。图1是示出第一示例性实施例的引线框架1的结构的视图。引线框架1被用作各种电子部件的内部布线。引线框架1是由铜合金、铁镍合金等等制成的薄板。引线框架1包括裸片焊盘2、引线3、以及突起4。
裸片焊盘2是其中布置并且固定至少一个IC芯片的区域。在本示例性实施例中,裸片焊盘2基本上位于整个引线框架1的中心并且具有方形。
引线3是被放射状地延伸以围绕裸片焊盘2的梳状部件。引线3电气地连接被安装在裸片焊盘2上的IC芯片和外部元件(安装在其它电子部件上的IC芯片、布线等等)。通过一体地形成有裸片焊盘2的框架部件11支撑引线3中的每一条。在引线3中的每一条与裸片焊盘2之间,确保预定的间隙。稍后将会描述此间隙。
突起4形成在裸片焊盘2的边缘15中。突起4中的每一个从边缘15朝着引线3突起。在本示例性实施例中,边缘15中的每一个具有以相等的距离布置的5个突起4。突起4用作裸片焊盘焊接点,并且还用作当IC芯片被安装在裸片焊盘2上时进行定位的基准。
图2是示出边缘15、突起4、以及引线3当中的间隙的部分放大图。在引线3的尖端和边缘15之间确保距离A。在引线3的尖端和突起4之间确保距离B。考虑用于通过按压加工生产引线框架1的模具的刀片的厚度设置距离A和B。距离A和B具有相同的值。
[第一示例]
图3和图4均示出引线框架1的使用状态。图3示出其中IC芯片21被布置在裸片焊盘2上的状态(安装工艺之后)。图4示出其中通过键合线24连接被布置在裸片焊盘2上的IC芯片21的端子和引线3的状态(焊接工艺之后)。
如图3中所示,IC芯片21具有等于裸片焊盘2的面积的面积。因此在裸片焊盘2上几乎不存在空间。然而,因为突起4从裸片焊盘2的边缘15向外突起所以确保了用于裸片焊盘焊接的空间。
在本示例中,如图4中所示,一些突起4被用作第一至第三裸片焊盘焊接点25、26、27。第一裸片焊盘焊接点25连接至安装在裸片焊盘2上的IC芯片21的自由端子。第二裸片焊盘焊接点26通过引线3连接至安装在另一电子部件上的IC芯片(另一IC芯片)的自由端子。第三裸片焊盘焊接点27连接至IC芯片21和另一IC芯片的自由端子。
这样,即使IC芯片21具有等于裸片焊盘2的面积的面积,通过形成突起4也确定地确保了用于裸片焊盘焊接的空间。因此,具有大面积的IC芯片或者大量的IC芯片能够被安装在裸片焊盘2上而无需考虑用于裸片焊盘焊接的空间。另外,在各种电子部件中能够广泛地共同使用具有同一标准的引线框架1,这减少制造成本、制造时间等等。
[第二示例]
图5和图6均示出引线框架1的另一使用状态。图5示出其中IC芯片31被布置在裸片焊盘2上的状态(安装工艺之后)。图6示出其中通过键合线24连接被布置在裸片焊盘2上的IC芯片31的端子和引线3的状态(焊接工艺之后)。
如图5中所示,相对于裸片焊盘2的面积,本示例的IC芯片31具有相对小的面积。在这样的情况下,很难以高精确度安装IC芯片31。然而,因为在本示例性实施例中,边缘15中的每一个具有等距离的相等数量的突起4,所以突起4能够被用作定位的基准。
另外,如图6中所示,一些突起4被用作第一至第三裸片焊盘焊接点25、26、27。第一裸片焊盘焊接点25连接至安装在裸片焊盘2上的IC芯片31的自由端子。第二裸片焊盘焊接点26通过引线3连接至安装在另一电子部件上的IC芯片(另一IC芯片)的自由端子。第三裸片焊盘焊接点27连接至另一IC芯片和IC芯片31的自由端子。
这样,突起4还有效地提高了当安装相对于裸片焊盘2具有相对小的面积的IC芯片时进行定位的精确度。
[第三示例]
图7和图8均示出引线框架1的另一使用状态。图7示出其中IC芯片41、42被布置在裸片焊盘2上的状态(安装工艺之后)。图8示出其中通过键合线24连接被布置在裸片焊盘2上的IC芯片41、42的端子和引线3的状态(焊接工艺之后)。
如图7中所示,在本示例中,安装两个IC芯片41、42。相对于裸片焊盘2的面积,IC芯片41、42中的每一个的占据面积相对小。然而,相对于裸片焊盘2的面积,芯片41、42的整个占据面积相对大。
在这样的情况下,很难以高精确度安装IC芯片41、42,并且很难找到用于裸片焊盘焊接的空间。与第二示例相类似,使用突起4的位置作为基准解决了安装位置的问题。此外,如图8中所示,与第一和第二示例相类似,使用一些突起4作为第一至第三裸片焊盘焊接点25、26、27解决了用于裸片焊盘焊接的空间的问题。
虽然已经按照若干示例性实施例和示例描述了本发明,但是本领域的技术人员将理解本发明可以在所附的权利要求的精神和范围内以各种修改来实践,并且本发明并不限于上述的示例。
此外,本领域技术人员能够根据需要组合示例。
此外,权利要求的范围不受到上述示例性实施例和示例的限制。
此外,注意的是,申请人意在涵盖所有权利要求要素的等价物,即使在后期的审查过程中对权利要求进行过修改亦是如此。
Claims (6)
1.一种引线框架,包括:
裸片焊盘,在所述裸片焊盘上安装至少一个IC芯片;
多条引线,所述多条引线电气地连接所述IC芯片和至少一个外部元件;以及
多个突起,所述多个突起形成在所述裸片焊盘的至少一个边缘中。
2.根据权利要求1所述的引线框架,其中所述突起用作与所述IC芯片或者所述外部元件的至少一个自由端子相连接的至少一个焊接点。
3.根据权利要求1所述的引线框架,其中当所述IC芯片被布置在所述裸片焊盘上时所述突起用作定位的基准。
4.根据权利要求1所述的引线框架,其中所述多个突起以相等的距离布置在所述边缘中的每一个中。
5.根据权利要求1所述的引线框架,其中所述引线中的每一条具有能够确保所述引线和所述边缘之间以及所述引线和所述突起之间的预定间隙的形状。
6.一种电子部件,所述电子部件包括安装在引线框架上的至少一个IC芯片,所述引线框架包括:
裸片焊盘,在所述裸片焊盘上安装所述IC芯片;
多条引线,所述多条引线电气地连接所述IC芯片和至少一个外部元件;以及
多个突起,所述多个突起形成在所述裸片焊盘的至少一个边缘中,
其中所述IC芯片或者所述外部元件的至少一个自由端子电气地连接至所述突起。
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JPH0373560A (ja) * | 1989-08-14 | 1991-03-28 | Nec Corp | 半導体装置 |
JPH045656U (zh) * | 1990-04-28 | 1992-01-20 | ||
JPH0745778A (ja) * | 1993-07-29 | 1995-02-14 | Sumitomo Electric Ind Ltd | リードフレーム及び半導体装置 |
JP2005243902A (ja) * | 2004-02-26 | 2005-09-08 | Matsushita Electric Ind Co Ltd | 半導体装置および半導体装置の製造方法 |
US20080079124A1 (en) * | 2006-10-03 | 2008-04-03 | Chris Edward Haga | Interdigitated leadfingers |
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JPS5762548A (en) * | 1980-10-01 | 1982-04-15 | Nec Corp | Semiconductor device |
JPH0263553U (zh) * | 1988-11-02 | 1990-05-11 | ||
JPH06318667A (ja) * | 1993-05-10 | 1994-11-15 | Nec Kansai Ltd | 半導体装置 |
KR0149798B1 (ko) * | 1994-04-15 | 1998-10-01 | 모리시다 요이치 | 반도체 장치 및 그 제조방법과 리드프레임 |
JPH1140721A (ja) * | 1997-07-15 | 1999-02-12 | Matsushita Electron Corp | リードフレーム、半導体装置およびそれらの製造方法 |
JP2000236060A (ja) * | 1999-02-16 | 2000-08-29 | Matsushita Electronics Industry Corp | 半導体装置 |
JP2002093987A (ja) * | 2000-09-13 | 2002-03-29 | Sharp Takaya Denshi Kogyo Kk | 認識パターン付リードフレーム |
JP2002110889A (ja) * | 2000-09-28 | 2002-04-12 | Hitachi Ltd | 半導体装置及びその製造方法 |
-
2009
- 2009-07-03 JP JP2009158460A patent/JP2011014758A/ja active Pending
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2010
- 2010-05-20 US US12/783,857 patent/US20110001226A1/en not_active Abandoned
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0373560A (ja) * | 1989-08-14 | 1991-03-28 | Nec Corp | 半導体装置 |
JPH045656U (zh) * | 1990-04-28 | 1992-01-20 | ||
JPH0745778A (ja) * | 1993-07-29 | 1995-02-14 | Sumitomo Electric Ind Ltd | リードフレーム及び半導体装置 |
JP2005243902A (ja) * | 2004-02-26 | 2005-09-08 | Matsushita Electric Ind Co Ltd | 半導体装置および半導体装置の製造方法 |
US20080079124A1 (en) * | 2006-10-03 | 2008-04-03 | Chris Edward Haga | Interdigitated leadfingers |
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