JP2010141230A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】半導体基板上に形成された第1配線層150、及び半導体素子200を備える。第1配線層150は、絶縁層156と、絶縁層156の表面に埋め込まれた第1配線154とを備える。半導体素子200は、半導体層220、ゲート絶縁膜160、及びゲート電極210を備える。半導体層220は、第1配線層150上に位置する。ゲート絶縁膜160は、半導体層220の上又は下に位置する。ゲート電極210は、ゲート絶縁膜160を介して半導体層220の反対側に位置する。
【選択図】図1
Description
"Control of p- and n-type conductivity in sputter deposition of undoped ZnO"、 Gang Xiong他5名、App.Phys.Lett., Vol.80, No.7, 18 February 2002 "High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper"、Minlyu kim他8名、App.Phys.Lett., Vol.90, 212114(2007) "High mobility thin-film transistors with InGaZnO channel fabricated by room temperature rf-magnetron sputtering"、Hisato Yabuta他8名、App.Phys.Lett., Vol.89, 112123(2006) "Highly Stable Ga2O3-In2O3-ZnO TFT for Active-Matrix Organic Light-Emitting Diode Display Application"、Chang Jung Kim他9名、IEEE Electron Devices Meeting, IEDM '06, Technical Digest, session 11.6, 2006 "Integrated circuits based on amorphous indium-gallium-zinc-oxide-channel thin-film transistors"、M.Ofuji他8名、ECS Transactions, 3(8)293-300(2006) "Wide-bandgap high-mobility ZnO thin-film transistors produced at room temperature"、Elvira M.C.Fortunato他6名、App.Phys.Lett., Vol.85, No.13, 27 September 2004
前記半導体基板上に形成された絶縁層と、前記絶縁層の表面に埋め込まれた第1配線とを有する第1配線層と、
前記第1配線層上に位置する半導体層と、
前記半導体層の上又は下に位置するゲート絶縁膜と、
前記ゲート絶縁膜を介して前記半導体層の反対側に位置するゲート電極と
を備える半導体装置が提供される。
前記第1配線層上に、前記第1配線上に位置するゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上に半導体層を形成する工程と、
前記半導体層にソース及びドレインを形成する工程と、
を備える半導体装置の製造方法が提供される。
前記第1配線層上に半導体層を形成する工程と、
前記半導体層上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記半導体層にソース及びドレインを形成する工程と、
を備える半導体装置の製造方法が提供される。
52 マスクパターン
54 マスクパターン
100 半導体基板
102 素子分離膜
110 半導体素子
112 ゲート絶縁膜
114 ゲート電極
116 不純物領域
120 コンタクト層
122 コンタクト
124 絶縁層
130 配線層
132 配線
134 絶縁層
140 拡散防止膜
150 第1配線層
152 ビア
154 第1配線
156 絶縁層
160 ゲート絶縁膜
162 拡散防止膜
170 絶縁層
184 ビア
186 配線
188 配線
189 ビア
200 半導体素子
210 ゲート電極
220 半導体層
222 ソース及びドレイン
224 チャネル領域
230 トラップ膜
232 ゲート絶縁膜
240 バックゲート電極
242 ゲート電極
Claims (20)
- 半導体基板と、
前記半導体基板上に形成された絶縁層と、前記絶縁層の表面に埋め込まれた第1配線とを有する第1配線層と、
前記第1配線層上に位置する半導体層と、
前記半導体層の上又は下に位置するゲート絶縁膜と、
前記ゲート絶縁膜を介して前記半導体層の反対側に位置するゲート電極と
を備える半導体装置。 - 請求項1に記載の半導体装置において、
前記第1配線層上に位置し、前記半導体層に接続する第2配線を備える第2配線層をさらに備える半導体装置。 - 請求項1または2に記載の半導体装置において、
前記ゲート絶縁膜は、前記第1配線層の上、かつ前記半導体層と前記第1配線層の間に位置しており、
前記ゲート電極は、前記第1配線と同一層に形成されている半導体装置。 - 請求項3に記載の半導体装置において、
前記第1配線は銅配線であり、
前記第1配線層上に設けられた拡散防止膜をさらに備え、
前記ゲート絶縁膜は、前記拡散防止膜であり、
前記半導体層は、前記拡散防止膜上に形成されている半導体装置。 - 請求項3又は4に記載の半導体装置において、
前記半導体層にはチャネル領域が形成されており、
前記半導体層上に位置するトラップ膜と、
前記トラップ膜上に位置し、平面視において前記チャネル領域と重なるバックゲート電極と、
を備える半導体装置。 - 請求項5に記載の半導体装置において、
前記半導体層、前記ゲート絶縁膜、前記ゲート電極、前記トラップ膜、及び前記バックゲート電極は、メモリ素子を構成する半導体装置。 - 請求項1または2に記載の半導体装置において、
前記ゲート絶縁膜及び前記ゲート電極は前記半導体層上に位置している半導体装置。 - 請求項1〜7のいずれか一つに記載の半導体装置において、
前記半導体層は酸化物半導体層を有している半導体装置。 - 請求項8に記載の半導体装置において、
前記酸化物半導体層はInGaZnO層又はZnO層である半導体装置。 - 請求項1〜9のいずれか一つに記載の半導体装置において、
前記絶縁層は、酸化シリコンより誘電率が低い低誘電率絶縁層である半導体装置。 - 請求項1〜10のいずれか一つに記載の半導体装置において、
前記半導体基板に形成されたMOSトランジスタ型の素子を備える半導体装置。 - 請求項11に記載の半導体装置において、
前記MOSトランジスタ型の素子は、平面視において少なくとも一部が前記半導体層と重なっている半導体装置。 - 半導体基板上に、絶縁層及び前記絶縁層の表面に埋め込まれた第1配線を有する第1配線層を形成する工程と、
前記第1配線層上に、前記第1配線上に位置するゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上に半導体層を形成する工程と、
前記半導体層にソース及びドレインを形成する工程と、
を備える半導体装置の製造方法。 - 請求項13に記載の半導体装置の製造方法において、
前記半導体層を形成する工程の後に、
前記半導体層上にトラップ膜を形成する工程と、
前記トラップ膜上に、平面視において前記第1配線と重なるバックゲート電極を形成する工程と、
を備える半導体装置の製造方法。 - 請求項14に記載の半導体装置の製造方法において、
前記トラップ膜を形成する工程及び前記バックゲート電極を形成する工程は、前記ソース及びドレインを形成する工程の前に行われ、
前記ソース及びドレインを形成する工程は、前記バックゲート電極をマスクとして前記半導体層を処理する工程である半導体装置の製造方法。 - 半導体基板上に、絶縁層及び前記絶縁層の表面に埋め込まれた第1配線を有する第1配線層を形成する工程と、
前記第1配線層上に半導体層を形成する工程と、
前記半導体層上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記半導体層にソース及びドレインを形成する工程と、
を備える半導体装置の製造方法。 - 請求項13〜16のいずれか一項に記載の半導体装置の製造方法において、
前記絶縁層は酸化シリコンより誘電率が低い低誘電率絶縁層である半導体装置の製造方法。 - 請求項13〜17のいずれか一項に記載の半導体装置の製造方法において、
前記半導体層は酸化物半導体層であり、
前記半導体層を形成する工程において、前記半導体基板を400℃以下の温度に加熱する半導体装置の製造方法。 - 請求項18に記載の半導体装置の製造方法において、
前記ソース及びドレインを形成する工程は、還元性プラズマを用いて前記半導体層を処理する工程である半導体装置の製造方法。 - 請求項18に記載の半導体装置の製造方法において、
前記ソース及びドレインを形成する工程は、前記半導体層に選択的に不純物を導入する工程である半導体装置の製造方法。
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