JP5946683B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5946683B2 JP5946683B2 JP2012094359A JP2012094359A JP5946683B2 JP 5946683 B2 JP5946683 B2 JP 5946683B2 JP 2012094359 A JP2012094359 A JP 2012094359A JP 2012094359 A JP2012094359 A JP 2012094359A JP 5946683 B2 JP5946683 B2 JP 5946683B2
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- Prior art keywords
- transistor
- drain
- source
- electrically connected
- oxide semiconductor
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0063—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H—ELECTRICITY
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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Description
まず、本発明の一態様である不揮発性メモリの一構成例について説明する。
酸化物半導体に限らず、実際に測定される絶縁ゲート型トランジスタの電界効果移動度は、さまざまな理由によって本来の移動度よりも低くなる。
本実施の形態の内容の一部又は全部は、他の全ての実施の形態又は実施例と組み合わせて実施することができる。
組成比としてIn:Sn:Zn=1:1:1のターゲットを用いて、ガス流量比をAr/O2=6/9sccm、成膜圧力を0.4Pa、成膜電力100Wとして、15nmの厚さとなるように基板上に酸化物半導体層を成膜した。
サンプルAは酸化物半導体層の成膜中に基板に意図的な加熱を施さなかった。
サンプルBは基板を200℃になるように加熱した状態で酸化物半導体層の成膜を行った。
サンプルCは基板を200℃になるように加熱した状態で酸化物半導体層の成膜を行った。
図17(A)にサンプルAのトランジスタの初期特性を示す。
サンプルB(成膜後加熱処理なし)及びサンプルC(成膜後加熱処理あり)とに対してゲートBTストレス試験を行った。
102 第2のトランジスタ
103 第3のトランジスタ
104 第4のトランジスタ
105 第5のトランジスタ
106 第6のトランジスタ
107 第7のトランジスタ
108 第8のトランジスタ
110 第1の端子
120 第2の端子
130 第3の端子
200 p型トランジスタ及びn型トランジスタが設けられた半導体基板
201 高濃度不純物領域
202 低濃度不純物領域
203 ゲート絶縁膜
204 ゲート電極
205 層間絶縁膜
210 酸化物半導体層にチャネル形成領域を有するトランジスタ
211 酸化物半導体層
212a ソース電極
212b ドレイン電極
213 ゲート絶縁膜
214 ゲート電極
Claims (4)
- 第1乃至第8のトランジスタを有し、
前記第1のトランジスタのソース及びドレインの一方は高電位側電源電位線に電気的に接続され、前記第1のトランジスタのソース及びドレインの他方は前記第2のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第2のトランジスタのソース及びドレインの他方は前記第3のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第3のトランジスタのソース及びドレインの他方は前記第4のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第4のトランジスタのソース及びドレインの他方は低電位側電源電位線に電気的に接続され、
前記第5のトランジスタのソース及びドレインの一方は高電位側電源電位線に電気的に接続され、前記第5のトランジスタのソース及びドレインの他方は前記第6のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第6のトランジスタのソース及びドレインの他方は前記第7のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第7のトランジスタのソース及びドレインの他方は前記第8のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第8のトランジスタのソース及びドレインの他方は低電位側電源電位線に電気的に接続され、
前記第1のトランジスタのゲートと前記第4のトランジスタのゲートは、第3の端子に電気的に接続され、
前記第3の端子は、前記第6のトランジスタのソース及びドレインの他方に電気的に接続され、
前記第5のトランジスタのゲートと前記第8のトランジスタのゲートは、第2の端子に電気的に接続され、
前記第2の端子は、前記第2のトランジスタのソース及びドレインの他方に電気的に接続され、
前記第2のトランジスタのゲートと前記第3のトランジスタのゲートと前記第6のトランジスタのゲートと前記第7のトランジスタのゲートは、第1の端子に電気的に接続されており、
前記第1のトランジスタはp型トランジスタであり、
前記第2のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第3のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第4のトランジスタはn型トランジスタであり、
前記第5のトランジスタはp型トランジスタであり、
前記第6のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第7のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第8のトランジスタはn型トランジスタである半導体装置。 - 第1乃至第8のトランジスタを有し、
前記第1のトランジスタのソース及びドレインの一方は高電位側電源電位線に電気的に接続され、前記第1のトランジスタのソース及びドレインの他方は前記第2のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第2のトランジスタのソース及びドレインの他方は前記第3のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第3のトランジスタのソース及びドレインの他方は前記第4のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第4のトランジスタのソース及びドレインの他方は低電位側電源電位線に電気的に接続され、
前記第5のトランジスタのソース及びドレインの一方は高電位側電源電位線に電気的に接続され、前記第5のトランジスタのソース及びドレインの他方は前記第6のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第6のトランジスタのソース及びドレインの他方は前記第7のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第7のトランジスタのソース及びドレインの他方は前記第8のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第8のトランジスタのソース及びドレインの他方は低電位側電源電位線に電気的に接続され、
前記第2のトランジスタのゲートと前記第3のトランジスタのゲートは、第3の端子に電気的に接続され、
前記第3の端子は、前記第6のトランジスタのソース及びドレインの他方に電気的に接続され、
前記第6のトランジスタのゲートと前記第7のトランジスタのゲートは、第2の端子に電気的に接続され、
前記第2の端子は、前記第2のトランジスタのソース及びドレインの他方に電気的に接続され、
前記第1のトランジスタのゲートと前記第4のトランジスタのゲートと前記第5のトランジスタのゲートと前記第8のトランジスタのゲートは、第1の端子に電気的に接続されており、
前記第1のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第2のトランジスタはp型トランジスタであり、
前記第3のトランジスタはn型トランジスタであり、
前記第4のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第5のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第6のトランジスタはp型トランジスタであり、
前記第7のトランジスタはn型トランジスタであり、
前記第8のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタである半導体装置。 - 第1乃至第6のトランジスタを有し、
前記第1乃至第3のトランジスタは順に直列に電気的に接続され、
前記第4乃至第6のトランジスタは順に直列に電気的に接続され、
前記第1のトランジスタのソース及びドレインの一方は高電位側電源電位線に電気的に接続され、前記第1のトランジスタのソース及びドレインの他方は前記第2のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第2のトランジスタのソース及びドレインの他方は前記第3のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第3のトランジスタのソース及びドレインの他方は低電位側電源電位線に電気的に接続され、
前記第4のトランジスタのソース及びドレインの一方は高電位側電源電位線に電気的に接続され、前記第4のトランジスタのソース及びドレインの他方は前記第5のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第5のトランジスタのソース及びドレインの他方は前記第6のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第6のトランジスタのソース及びドレインの他方は低電位側電源電位線に電気的に接続され、
前記第1のトランジスタのゲートと前記第3のトランジスタのゲートは、第3の端子に電気的に接続され、
前記第3の端子は、前記第5のトランジスタのソース及びドレインの他方に電気的に接続され、
前記第4のトランジスタのゲートと前記第6のトランジスタのゲートは、第2の端子に電気的に接続され、
前記第2の端子は、前記第2のトランジスタのソース及びドレインの他方に電気的に接続され、
前記第2のトランジスタのゲートと前記第5のトランジスタのゲートは、第1の端子に電気的に接続されており、
前記第1のトランジスタはp型トランジスタであり、
前記第2のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第3のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第4のトランジスタはp型トランジスタであり、
前記第5のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第6のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第1の端子には、書き込み動作時において、前記第2のトランジスタ及び前記第5のトランジスタをオンにする電位が供給される半導体装置。 - 第1乃至第6のトランジスタを有し、
前記第1乃至第3のトランジスタは順に直列に電気的に接続され、
前記第4乃至第6のトランジスタは順に直列に電気的に接続され、
前記第1のトランジスタのソース及びドレインの一方は高電位側電源電位線に電気的に接続され、前記第1のトランジスタのソース及びドレインの他方は前記第2のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第2のトランジスタのソース及びドレインの他方は前記第3のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第3のトランジスタのソース及びドレインの他方は低電位側電源電位線に電気的に接続され、
前記第4のトランジスタのソース及びドレインの一方は高電位側電源電位線に電気的に接続され、前記第4のトランジスタのソース及びドレインの他方は前記第5のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第5のトランジスタのソース及びドレインの他方は前記第6のトランジスタのソース及びドレインの一方に電気的に接続され、
前記第6のトランジスタのソース及びドレインの他方は低電位側電源電位線に電気的に接続され、
前記第2のトランジスタのゲートと前記第3のトランジスタのゲートは、第3の端子に電気的に接続され、
前記第3の端子は、前記第5のトランジスタのソース及びドレインの他方に電気的に接続され、
前記第5のトランジスタのゲートと前記第6のトランジスタのゲートは、第2の端子に電気的に接続され、
前記第2の端子は、前記第2のトランジスタのソース及びドレインの他方に電気的に接続され、
前記第1のトランジスタのゲートと前記第4のトランジスタのゲートは、第1の端子に電気的に接続されており、
前記第1のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第2のトランジスタはp型トランジスタであり、
前記第3のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第4のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第5のトランジスタはp型トランジスタであり、
前記第6のトランジスタは酸化物半導体層にチャネル形成領域を有するトランジスタであり、
前記第1の端子には、書き込み動作時において、前記第1のトランジスタ及び前記第4のトランジスタをオンにする電位が供給される半導体装置。
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US20120268979A1 (en) | 2012-10-25 |
US8797788B2 (en) | 2014-08-05 |
US9548308B2 (en) | 2017-01-17 |
US9287266B2 (en) | 2016-03-15 |
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US20160163710A1 (en) | 2016-06-09 |
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