JP2007235150A - 二方向伝導フリップチップ半導体デバイス及び半導体デバイス - Google Patents
二方向伝導フリップチップ半導体デバイス及び半導体デバイス Download PDFInfo
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- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
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- 238000000034 method Methods 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 210000004027 cell Anatomy 0.000 description 2
- 238000013461 design Methods 0.000 description 2
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- CJRQAPHWCGEATR-UHFFFAOYSA-N n-methyl-n-prop-2-ynylbutan-2-amine Chemical compound CCC(C)N(C)CC#C CJRQAPHWCGEATR-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
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- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】第1の主面において間隔を置いて形成された第1の伝導型である第1及び第2のソース領域53A,53Bと、第1及び第2のソース領域を収容する、第2の伝導型である第1及び第2のチャネル領域52A,52Bと、第1及び第2のチャネル領域を収容し、第2の主面まで延びる共通のドレイン領域51と、第1の主面上に配置され、第1及び第2のチャネル領域のそれぞれの部分を反転させて第1及び第2のソース領域からドレイン領域までの伝導をそれぞれ可能にするような、第1及び第2のゲート構造75A,75Bを備える第1及び第2のMOSゲートデバイス140,141と、第1及び第2のソース領域に接続された第1及び第2のソースメタライズド層31A,31Bと、第1及び第2のゲート構造に接続された第1及び第2のゲートメタライズド層とを有する。
【選択図】図12
Description
図1乃至図6は、本発明の半導体デバイスの第1の実施形態を示す図である。この第1の実施形態は、フリップチップパワーMOSFETの形態であって、全ての電極を1つの平面内に有し、コンタクトバンプを有することで、支持体構造、たとえばプリント回路基板のトレースまたはその他の導体へのコンタクトが可能である。記載すべきデバイスは、他のどんなタイプのデバイスでも良く、たとえばP/Nまたはショットキーダイオード、IGBT、サイリスタ、複数の部品を有する集積回路ダイなどである。また、図1乃至図6のデバイスは、Pチャネルデバイスを示している。伝導型を反対にしてNチャネルデバイスを作製することができる。また、図1乃至図6のデバイスは、トレンチ型のデバイスとして示しているが、後述するようにプレーナセルラまたはストライプ構造であっても良い。
31 上部ソース電極メタライジング(ソース電極)
32 ドレイン電極メタライジング(ドレインコンタクトメタライジング)
33 ゲート電極金属パッド(ゲートパッドメタライジング)
34 ゲートバス
40 ソースコンタクトボール
41,42 ドレインコンタクトボール
43 ゲートコンタクトボール
50 P+シリコン基板
51 接合収容層
52 チャネル拡散層(N拡散層)
53 P+ソース拡散層
60,61 トレンチ
70,71 ゲート絶縁層
75 導電性ポリシリコンゲート
76,77 絶縁キャップ
80 TEOS層
81,82 コンタクト開口部
90 P+「シンカ」拡散層
91 トレンチ
92 導電性ポリシリコン
100 ダイ
101 ソース電極
102,103 ドレイン電極
104 ゲートパッド
105,106 バス
110 N+基板
111 N型エピタキシャル(エピ)層
112,113,114 Pチャネル拡散層
115,116,117 N+ソース拡散層
118,119,120 P+コンタクト拡散層
121 ポリシリコンゲート格子
122 絶縁層
130 二方向ダイ
131 基板メタライゼーション(底部導体)
140,141 MOSFET
142,143 バス
Claims (16)
- シリコンウェハを備えた二方向伝導フリップチップ半導体デバイスにおいて、
前記シリコンウェハは、平行な第1及び第2の主面と、前記シリコンウェハ内に形成され、横方向に分離された第1及び第2のMOSゲートデバイスであって、
前記第1の主面の、間隔を置いて配置された第1及び第2の横方向領域内にそれぞれ形成される、第1の伝導型である第1及び第2のソース領域と、
前記第1及び第2のソース領域を収容する、第2の伝導型である第1及び第2のチャネル領域と、
前記第1及び第2のチャネル領域を収容し、前記第2の主面まで延びる共通のドレイン領域と、前記第1の主面上に配置され、前記第1及び第2のチャネル領域のそれぞれの部分を反転させて前記第1及び第2のソース領域から前記ドレイン領域までの伝導をそれぞれ可能にするような、独立動作が可能な第1及び第2のゲート構造とをそれぞれ備える第1及び第2のMOSゲートデバイスと、
前記第1の主面上に配置され、前記第1及び第2のソース領域にそれぞれ接続された、横方向に間隔を置いて配置される第1及び第2のソースメタライズド層と、
前記第1の主面上にあり、前記第1及び第2のゲート構造にそれぞれ接続された、横方向に間隔を置いて配置される第1及び第2のゲートメタライズド層と
を有することを特徴とする二方向伝導フリップチップ半導体デバイス。 - 前記ソース及びゲートメタライズド層のそれぞれに接続される少なくとも1つのコンタクトバンプを備えることを特徴とする請求項1に記載の二方向伝導フリップチップ半導体デバイス。
- 前記ソースメタライズド層のそれぞれに接続される個別の複数のコンタクトバンプを備え、前記複数のコンタクトバンプのそれぞれは、間隔を置いて配置される互いに平行な個別の列に並べられていることを特徴とする請求項2に記載の二方向伝導フリップチップ半導体デバイス。
- 前記第1及び第2のソース領域は、互いに対して横方向のインターデジタル構造の関係で配置されることを特徴とする請求項1に記載の二方向伝導フリップチップ半導体デバイス。
- 前記第1及び第2のソース領域は、互いに対して横方向のインターデジタル構造の関係で配置されることを特徴とする請求項3に記載の二方向伝導フリップチップ半導体デバイス。
- 前記第2の主面上の金属層を備えることを特徴とする請求項1に記載の二方向伝導フリップチップ半導体デバイス。
- シリコンダイを備える半導体デバイスであって、前記シリコンダイは、
平行な第1及び第2の表面と、
一方の伝導性の基板及び該基板上に設けられた前記一方の伝導性のエピタキシャル形成層と、
前記第1の表面から前記エピタキシャル形成層の内部まで延びる他方の伝導型の領域と、
該他方の伝導型の領域内部に横方向に間隔を置いて配置された複数の前記一方の伝導型の拡散層によって形成される、前記デバイス中に形成される接合パターンと、
前記第1の表面上に形成され、前記一方の伝導型の複数の拡散層とコンタクトしているフリップマウント可能な第1の導電性電極と、
前記第1の表面上に形成され、前記第1の導電性電極に対して、同一平面であり、横方向に間隔を置いて配置され、絶縁されており、かつ前記エピタキシャル形成層に延びている伝導体を介して前記基板及び前記エピタキシャル形成層と電気的に接続され、前記伝導体が前記エピタキシャル形成層と異なる低いあるいは高い伝導材料であるフリップマウント可能な第2の導電性電極と、
前記第1及び第2のそれぞれの導電性電極上にそれぞれ形成される少なくとも1つのハンダボールコネクタと、
前記第1の表面に垂直な垂直要素を有する、前記第1の導電性電極から前記第2の導電性電極までの電流経路と
を有することを特徴とする半導体デバイス。 - 前記半導体デバイスは、パワーMOSゲートデバイスを含み、前記第1及び第2の電極は前記デバイスのメインパワー電極を含むことを特徴とする請求項7に記載の半導体デバイス。
- 前記半導体デバイスは、前記複数の拡散層に隣接して形成され前記デバイスをオン/オフするように動作可能なポリシリコンゲート構造と、前記第1の表面上に形成され、前記第1及び第2の導電性電極に対して、同一平面であり、横方向に間隔を置いて配置され、絶縁されており、かつ前記ポリシリコンゲート構造と接続される第3の導電性電極と、前記第3の導電性電極と接続されるハンダボールコネクタとを備え、前記ハンダボールコネクタは全て、互いと同一平面上にあることを特徴とする請求項8に記載の半導体デバイス。
- 前記半導体デバイスは、フリップチップパワーMOSFETであることを特徴とする請求項9に記載の半導体デバイス。
- 前記一方の伝導型はP型であることを特徴とする請求項7に記載の半導体デバイス。
- 前記一方の伝導型はP型であることを特徴とする請求項9に記載の半導体デバイス。
- 前記半導体デバイスは、前記複数の拡散層に隣接して形成され前記デバイスをオン/オフするように動作可能なポリシリコンゲート構造と、前記第1の表面上に形成され、前記第1及び第2の導電性電極に対して、同一平面であり、横方向に間隔を置いて配置され、絶縁されており、かつ前記ポリシリコンゲート構造と接続される第3の導電性電極と、前記第3の導電性電極と接続されるハンダボールコネクタとを備え、前記ハンダボールコネクタは全て、互いと同一平面上にあることを特徴とする請求項7に記載の半導体デバイス。
- 前記第2の主面は、前記デバイスの冷却を改善するための拡張された面積を設けるために粗くされていることを特徴とする請求項9に記載の半導体デバイス。
- 前記第2の表面に固定されてこの表面に広がる金属層を含むことを特徴とする請求項9に記載の半導体デバイス。
- 前記半導体デバイスは、MOSFET、ショットキーダイオード、バイポーラトランジスタ、及びP/Nダイオードからなる群から選択されることを特徴とする請求項7に記載の半導体デバイス。
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JP2018061009A (ja) * | 2016-09-30 | 2018-04-12 | ローム株式会社 | 半導体装置および半導体パッケージ |
US11557587B2 (en) | 2016-09-30 | 2023-01-17 | Rohm Co., Ltd. | Semiconductor device and semiconductor package |
Also Published As
Publication number | Publication date |
---|---|
WO2001059842A1 (en) | 2001-08-16 |
KR20070010188A (ko) | 2007-01-22 |
US6653740B2 (en) | 2003-11-25 |
KR20020073547A (ko) | 2002-09-26 |
US20010045635A1 (en) | 2001-11-29 |
KR100721139B1 (ko) | 2007-05-25 |
CN1401141A (zh) | 2003-03-05 |
CN1315195C (zh) | 2007-05-09 |
AU2001238081A1 (en) | 2001-08-20 |
US20040021233A1 (en) | 2004-02-05 |
KR100699552B1 (ko) | 2007-03-26 |
EP1258040A1 (en) | 2002-11-20 |
EP1258040A4 (en) | 2009-07-01 |
TW493262B (en) | 2002-07-01 |
JP4646284B2 (ja) | 2011-03-09 |
JP2004502293A (ja) | 2004-01-22 |
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