CN1315195C - 在单面上带块形连接的垂直导电倒装芯片式器件 - Google Patents
在单面上带块形连接的垂直导电倒装芯片式器件 Download PDFInfo
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Abstract
一种倒装芯片式MOSFET结构具有垂直导电半导体管芯(30),其中,管芯的下层同管芯顶部上的漏极(32)通过扩散散热片或导通电极连接。源极(31)和栅极(33,34)也在管芯的上表面上形成,并且具有连接电路板的共面焊球(41,43,43)。结构具有芯片级封装尺寸。当安装管芯时转换的管芯背面可粗糙化或可以金属化以改进从管芯去除热量。可并排地将几个分离的MOSFET结合进管芯,以形成同具有焊球连接体的顶面上的源极和漏极分别连接的一系列MOSFET连接点。多个焊球连接体可为顶部电极提供并被设计在相应的平行行中。管芯可具有拉长矩形的形状,焊球绕着矩形的对角线呈对称地分布。
Description
发明背景
本发明涉及半导体器件封装和制作这种封装的方法,更特别地涉及到芯片级的封装及其生产方法。
已知半导体器件封装用于装套和保护半导体管芯以及提供至管芯电极输出连接。通常,半导体管芯从很大的母片切割而成,其中,管芯扩散和金属化处理在传统的晶片处理设备中进行。这样的管芯可以是二级管、场效应管、可控硅整流器之类。管芯易碎,必须保护管芯表面不受外界环境的损害。此外,合宜的导线必须连接到管芯电极上用于电路中管芯的连接。
通常,这样的管芯通过切片从晶片分割而得,管芯的底部安装于具有接收对应管芯的套片部分的电路板的一部分并与之连接。管芯的顶部电极随后通常用导线与电路板的其它部分连接,电路板随后用于外部连接。这样的导线连接是精密的且减慢了安装进程。它们还提供了相当高的电阻和电感。
希望在许多场合中,封装的半导体器件可从封装的一边安装,使完成电路板上迅速而可靠的安装,同时提供低电阻连接。
发明内容
本方面提供了新颖的半导体管芯封装,包含安装在电路板或其它使用芯片一个表面的电子接口上的“倒装芯片式”。特别地,封装有连接,举例来说,与封装同边的栅极连接、源极连接和漏极连接(对于MOSFET(金属氧化物半导体场效应晶体管)),并且可通过在分别与电路板上的外部栅极、源极和漏极连接相连的芯片表面形成焊球来安装。
与芯片的源极连接通过芯片源极上的焊球来完成,焊球被固定,这样依赖它们将与电路板上适当的源极电子连接相连。封装被这样构造,使得漏极在同一表面上。
在一实施例中,有源结在载流子浓度(例如,P-)相对较低的层中,该层在源极之下但却在具有相对较高的相同类型载流子(比如,P+)浓度的基片之上。在与源电极分离的区域的相同表面上固定着至少一个漏极。扩散区或“散热片”穿过相对基片载流子浓度较低的层,从顶部漏极延伸并在顶部漏极之下。扩散区与基片具有相同的载流子浓度和载流子类型(比如,P+)。由此,建立了一条电子通道,从源极开始,穿过有源元件到达基片,再穿过扩散区到达顶部漏极。
正如所提到的,漏极与源极和栅极在同一表面,并由此可使用对应适当的外部漏极连接的位置的焊球安装至电路板。
在另一实施例中,代替在漏极连接之下使用扩散区,载流子浓度相对较低的层可被蚀刻至基片并用漏极填充。这可在——比如,垂直导电沟道型器件的——沟道蚀刻步骤的同时完成。
在本方面的还有一个实施例中,在公用芯片中形成了两个垂直导电MOSFET器件,它们的源极区横向叉指排列而公用一个漏极基片。这种结构形成了固有双向开关。所有的连接提供在顶面,连接球可沿着绕矩形芯片对角线呈对称的直行分布,以简化对电路板支持的连接。芯片的底部可具有在具有共有漏极的邻近器件之间提供低电阻电流通路的厚金属层。在芯片用其相对印刷电路板的顶面安装时,它还能够提高导热性。
本发明提供一种倒装芯片式半导体器件,其特征在于,包含具有平行的第一和第二主面的硅晶片;在所述晶片内的至少一个P区和至少一个N区,这两个区在所述硅晶片内的PN结处相交;在所述第一主面上形成并彼此绝缘且分别同所述的P区和所述的N区连接的、共面的水平隔开和金属化的第一金属化层和第二金属化层;在所述第一主面之上的第三金属化层,该第三金属化层与所述第一和第二金属化层共面并与该第一和第二金属化层水平隔开;所述第一、第二和第三金属化层分别包括MOS门控器件的源极、漏极和栅极;所述的第二主面被粗糙化以形成用于所述半导体器件的散热的增加的表面积,其中,在所述源极和所述漏极之间有一电流通路,且所述电流通路包括一垂直分量。
本发明提供一种倒装芯片式半导体器件,其特征在于,包含具有平行的第一和第二主面的硅晶片;在所述晶片内的至少一个P区和至少一个N区,这两个区在所述硅晶片内的PN结处相交;在所述第一主面上形成并与另一个主面绝缘且分别同所述的P区和所述的N区连接的、共面的水平隔开和金属化的第一金属化层和第二金属化层;在所述第一主面之上的第三金属化层,该第三金属化层与所述第一和第二金属化层共面并与该第一和第二金属化层水平隔开;所述第一、第二和第三金属化层分别包括MOS门控器件的源极、漏极和栅极;以及延展在所述第二主面上的金属化底层,其中,在所述源极和所述漏极之间有一电流通路,所述电流通路包括一垂直分量。
本发明提供一种倒装芯片式半导体器件,其特征在于,包含具有平行的第一和第二主面的硅晶片;在所述晶片内的至少一个P区和至少一个N区,这两个区在所述硅晶片内的PN结相交;在所述第一主面上形成并彼此绝缘且分别同所述的P区和所述的N区连接的、共面的水平隔开和金属化的第一金属化层和第二金属化层;多个连接于每一个所述第一和第二金属化层的连接球,与所述第一金属化层连接的多个连接球沿第一直行排列,与所述第二金属化层连接的多个连接球沿第二直行排列;以及在所述第一主面之上的第三金属化层,该第三金属化层与所述第一和第二金属化层共面并与该第一和第二金属化层水平隔开;所述第一、第二和第三金属化层分别包括MOS门控器件的源极、漏极和栅极,其中,在所述源极和所述漏极之间有一电流通路,所述电流通路包括一垂直分量。
本发明提供一种半导体器件,其特征在于,包含具有第一和第二平行表面的硅管芯;从所述第一表面延伸至所述管芯体内的一种导电类型的区域;在所述的由多个扩散至所述的一种导电类型区域内的另一种导电类型的扩散组成的器件内确定的连接模式;在与所述的多个扩散相接触的所述第一表面之上形成的第一导通电极;在所述第一表面之上形成的第二导通电极,该第二导通电极与所述第一导通电极共面、水平隔开且绝缘,并且还与所述管芯体相接触;至少一个分别在每个所述的第一和第二导通电极上形成的焊球连接体;从所述第一导通电极至所述第二导通电极的电流通路,其具有基本垂直于所述第一表面的垂直元件。
本方面的其它特征和优点将从以下参考附图的本发明描述中变得更为明显。
附图说明
图1是本发明第一实施例的透视图。
图2是连接块形成前图1器件的金属化图案的俯视图。
图3显示了在焊块形成后图2的晶片。
图4是通过对应图2中线4-4截面区域的小区域展示的图2的横截面,并在图中显示了源极和漏极顶部的金属化。
图5是显示图1和图3接触球的尺寸和间距的布置图。
图6是图2沿横截线6-6和栅极总线的横截面。
图7显示了使用P+散热片扩散使得将漏极金属的顶部连接与P+基片连接。
图8显示了制造图4顶面的漏极至P+基片的连接的修改的连接结构。
图9是本发明另一个实施例金属化顶面的俯视图。
图10显示了图9在适当位置带成行的接触球。
图11是图9取代图4沟道结构的平面连接图案的横截面。
图12是本发明的还有一个实施例的横截面,与图4的相同但在共有的芯片上使用了两个MOSFET,产生了双向导电器件,并且还是图14沿着图中的截面线12-12的横截面。
图13是图12器件的电路的图解。
图14是诸如图12和图13之类器件的俯视图。
图15是图14器件的正视图。
图16至图19显示了图14器件的进一步变化。
具体实施方式的详细描述
图1至图6显示了本发明的第一实施例,它以倒装芯片式功率MOSFET为形式,该功率MOSFET在平面内具有所有的电极并具有连接块使能够连接至线迹或其它诸如印刷电路板之类的支持结构的导电体。描述的器件可以是任何类型的器件,诸如P/N或肖特基二极管、IGBT(绝缘栅极双极型晶体管)、可控硅整流器、具有多个元件的集成电路之类。此外,显示了图1至图6作为P沟道器件的器件。可改变导电类型制成N沟道器件。另外,显示了图1至图6作为沟道型器件的器件,但它可以是平面网格或带形结构以及以后将描述的。
准备安装的完整的器件在图1中显示,并由具有上层源极金属化层31(通常为2μm到8μm厚的铝)、漏极金属化层32和栅极金属焊盘33(图2)和栅极母线34组成。
管芯如图2和图3所示的,以晶片的形式加工。连接球在图1、3和4所示的晶片上形成,源极连接球40在源极金属层31上形成,漏极连接球41和42在漏极连接金属化层32上形成,栅极连接球43在栅极焊盘金属化33上形成。晶片内的管芯随后被切成单个,在电路板或类似装置上制成组件。
图4和图6显示了图1和图3器件的沟道型功率MOSFET的几何机构。从而,对于P沟道器件,使用了P+硅基片50,而对于低浓度P型,在P+硅基片50的顶上外延地形成了结接纳层51。随后形成了N型基极或沟道扩散层52(图4和图5)。
此后,使用传统的技术,在分离的台式区域形成了多个平行沟道60和61(图4)或一列交叉的沟道。随后,在沟道60到64中的每一个沟道的壁上形成了诸如二氧化硅之类的绝缘薄层,分别如栅极绝缘层70到74所示。随后将导电多晶硅栅极75淀积入每一个沟道以及栅极氧化层的上方,接着再将其蚀刻去,只在沟道和栅极母线还有焊盘区域内留下多晶硅。在那以后,TEOS层80沉淀并形成了图案,在沟道60和61内多晶硅75顶部的上方留下了绝缘盖76和77(可能为TEOS(原硅酸四乙酯))(图4)。
在N扩散层52的顶部中形成P+源极扩散层53,并且该层被蚀刻穿过层52和53。接着,连接口81和82(图4)穿过P+源极层53被蚀刻入沟道层52,而在开口81和82底部内形成了N+连接扩散层。随后,水平地蚀刻电介质材料,以暴露管芯表面上源极区域的部分,便于连接。接下来,用铝连接P+源极区53和N型沟道区52,在器件表面的顶部沉淀连续的铝层。该铝层通过蚀刻分离成源极连接31、漏极连接32和栅极垫片33。
图5显示了连接球40和41新颖的构造。这些焊球通过已知的加工方法形成,该方法应用了镍-金电镀,随后使用了焊料的模板印刷以及流动焊料以形成球体。由此,焊球或焊块中心距离为0.8mm,为宽于传统使用的间距。通过使用0.8mm或更大的间距,本发明的倒装芯片式结构可模仿传统的芯片级封装对使用传统的表面安装技术的带传统线迹的电路板的应用和附加装置。焊球40和41用传统上的声热方法焊接至表面上,但具有的直径大于那些先前使用的,比如,同标准的150μ相比的200μ或更大的直径。通过使用较大的直径,提高了导热性并改进了热失效电阻。
在图4中,显示了作为连接P+基片50向上延伸的部分的漏极金属32。这是略图,在实际应用中,从表面漏极32到P+基片50的连接如图7和图8所制造。因而,在图7中应用了P+“散热片”扩散层90以制造连接。在图8中,在制作有效面积的沟道蚀刻过程中,形成了沟道91,并且该沟道用金属或导电多晶硅92填充。
图1至图8器件的操作对于那些普通的技术人员将是明显的。于是,打开器件电源,随着施加于源极31和漏极32之上合适的电压,栅极电压对栅极75的施加将引起邻近于栅极氧化层70至74的N型硅转化为P型,从而完成了从源极31穿过源极区53和转化区到达P区域51和P+基片50,随后水平穿过P+基片50向上(穿过区域90或92)到达漏极31的电路。
图1至图8的新颖的器件带来了为安装至最小作准备的器件的尺寸;即,管芯的尺寸。使用垂直构造的单元沟道工艺管芯本身具有极低的RDSON(器件工作时(例如导通时)的电阻)。例如,设计能够应用每英寸超过110×106个单元。然而,不像标准的沟道FET设计,漏极连接被安装于管芯的前方或顶部。不需要后磨管芯底面或在管芯底面上沉淀金属。通过不后磨,较厚的P+基片允许较低的水平电阻至漏极电流的流动。较佳地,管芯底面可以粗糙且未磨光的以提高其表面积从而有助于除去芯片上的热量。
在金属化后,沉淀氮化硅(或其它电解质)钝化层。氮化硅钝化层形成图案,每个管芯上留下4个(间距,比如为0.8mm)开口。管芯尺寸通常可约为0.060英寸×0.060英寸。较大尺寸0.123英寸×0.023英寸的器件也是典型的。硅被如此设计以提供以4.5伏Vgs带46.8ohm-mm2的R*A的20伏P沟道器件。
当在基片50的底面上不需要金属层时,使用诸如电流导电体的金属层或制作对散热片的热连接是有用的。
也可使用其它具有较高电流容量的较大量焊球的表面几何结构。因此,如图9和图10所示的,可设计较大的管芯100,使得顶面提供一个源极101、两个与管芯100的相对边缘邻接的加宽的漏极102和103以及一个带流道或母线105和106的栅极焊盘104。如图10所示的,每个漏极102和103接纳5个以相应行排列的焊球,而源极101接纳8个同样以平行行排列的焊球。单一的焊球同栅极焊盘104相连。通过对准各自平行行排列焊球,接收器件的印刷电路板上相应的导电线迹可被设计成简单的直线。
图11显示了图9器件是怎样用平面技术并作为N沟道器件来执行的。因此,在图11中,管芯100用N+基片110、N型外延(epi)层111和隔开的多边形P沟道扩散层112、113和114形成。112、113和114中的每一个扩散层分别接纳N+源极扩散层115、116和117以及P+连接扩散层118、119和120。合适的包括多晶硅栅极乳胶121的栅极结构覆盖在传统的栅极氧化物之上并且被绝缘层122覆盖,从而同以平常方式连接源极区和沟道区的覆盖的源极101的栅极乳胶绝缘。N+散热片提供从N+基片到漏极103的导电通道。
同样可能的是,利用两系列连接的MOSFET可集合成单一的芯片这样的双向导电特性来制作管芯。因此,如图12所示,管芯能以图1至图8P沟道的沟道实施方式形成。从而,使用在图1至图8中使用的数字,图12的双向管芯130在单一的管芯上合成了两个这样的器件。这两个器件以图4的数字来识别,分别后跟“A”和“B”但具有共有的基片50。还将提供每一个都具有图5和图6结构的两个相应的栅极结构。还显示了基片的金属化层131。
在图13中显示了双向器件的电路图,该电路图由分别具有源极端子S1和S2、分别具有栅极端子G1和G2以及共有的漏极50和131的两个MOSFET140和141组成,从而形成双向的导通电路。MOSFET140和141是分别带体二极管(图13中未显示)的垂直导电的器件,当另一个MOSFET合上电源时,该体二极管导通。
图14和图15显示了图12的芯片或管芯130的俯视图。芯片130可具有底部导电的漏极131(图15),而且还将具有相应的可分别具有相应的栅极滑道或母线142和143的栅球极G1和G2。漏极131可以是低电阻的厚金属层(同传统的源极厚度相比)。如果P+基片50具有足够高的导电性,可除去底部导电体131,但若作为散热片它仍然有用。
如图14所示,每个FET 140和141的源极具有两个或更多的电极块S1和S2。S1块和G1块之间的距离同S2块和G2块之间的距离是相等的。
根据本发明的进一步特征,芯片或管芯130的高度大于其宽度。因此,它是一个非方形的、拉长的矩形。此外,管芯块S1、S2、G1和G2绕着管芯130的对角线,如图14中点线对角线150所示,对称分布。因此,源极和漏极将在同一位置跟芯片上/下的方向无关。由于管芯具有旋转的对称,不需要引线标志,且简单的模式识别设备能够在附加到表面的过程中检测到管芯的方向或方位。
如前面所指出的,并根据本发明,源极球S1处于同源极球S2相隔或平行的线或行之中。
图16、图17、图18和图19显示了图13、图14和图15中FET1(FET140)和FET2(FET141)的可供选择的布局,其中,相同的数字识别相同的部分。图16至图19的硅管芯可具有大约0.120英寸×0.120英寸的面积。注意的是,在每种情况下,源极球S1和S2均在相应的垂直和平行的行中,使容易通过印刷电路板上的直金属带或直金属线使用用于平行连接的直导体。此外,要注意的是,FET140和141的源极在图17、图18和图19中叉指排列,增加了它们连接的面积。图19的布局特别有优势,因为它将电流必须在基片中通过的距离最小化,同时保持两个源极金属块被放置在一起。通过这种方法,基片和金属的电阻都非常低,同时板级连接非常得容易。
虽然本发明已在其相关的特别实施例中进行了描述,对于那些技术熟练的工人来说,仍然有许多其它的变化、修改和其它用途将会变得明显。因此,较佳地,本发明不受此处特定的揭示内容限制,而只受附加的权利要求的限制。
Claims (35)
1.一种倒装芯片式半导体器件,其特征在于,包含具有平行的第一和第二主面的硅晶片(30);在所述晶片内的至少一个P区(51)和至少一个N区(52),这两个区在所述硅晶片内的PN结处相交;在所述第一主面上形成并彼此绝缘且分别同所述的P区和所述的N区连接的、共面的水平隔开和金属化的第一金属化层(31)和第二金属化层(32);在所述第一主面之上的第三金属化层(34),该第三金属化层与所述第一和第二金属化层共面并与该第一和第二金属化层水平隔开;所述第一、第二和第三金属化层分别包括MOS门控器件的源极、漏极和栅极;所述的第二主面被粗糙化以形成用于所述半导体器件的散热的增加的表面积,其中,在所述源极和所述漏极之间有一电流通路,且所述电流通路包括一垂直分量。
2.一种倒装芯片式半导体器件,其特征在于,包含具有平行的第一和第二主面的硅晶片(30);在所述晶片内的至少一个P区(51)和至少一个N区(52),这两个区在所述硅晶片内的PN结处相交;在所述第一主面上形成并与另一个主面绝缘且分别同所述的P区和所述的N区连接的、共面的水平隔开和金属化的第一金属化层(31)和第二金属化层(32);在所述第一主面之上的第三金属化层(34),该第三金属化层与所述第一和第二金属化层共面并与该第一和第二金属化层水平隔开;所述第一、第二和第三金属化层分别包括MOS门控器件的源极、漏极和栅极;以及延展在所述第二主面上的金属化底层,其中,在所述源极和所述漏极之间有一电流通路,所述电流通路包括一垂直分量。
3.权利要求1的器件,其特征在于,还包括与每个所述的金属化层连接的至少一个连接球(40,41,43)。
4.权利要求2的器件,其特征在于,还包括与每个所述的金属化层连接的至少一个连接球(40,41,43)。
5.权利要求3的器件,其特征在于,多个连接球与每个所述的第一和第二金属化层连接;与所述第一金属化层连接的多个连接球沿第一直行排列;与所述第二金属化层连接的多个连接球沿第二直行排列。
6.权利要求5的器件,其特征在于,所述的第一直行和第二直行彼此互相平行。
7.权利要求4的器件,其特征在于,多个连接球同每一个所述的第一和第二金属化层连接;与所示第一金属化层连接的多个连接球沿第一直行排列;与所述第二金属化层连接的多个连接球沿第二直行排列。
8.权利要求7的器件,其特征在于,所述的第一直和第二直行彼此互相平行。
9.一种倒装芯片式半导体器件,其特征在于,包含具有平行的第一和第二主面的硅晶片(30);在所述晶片内的至少一个P区(51)和至少一个N区(52),这两个区在所述硅晶片内的PN结相交;在所述第一主面上形成并彼此绝缘且分别同所述的P区和所述的N区连接的、共面的水平隔开和金属化的第一金属化层(31)和第二金属化层(32);多个连接于每一个所述第一和第二金属化层的连接球,与所述第一金属化层连接的多个连接球沿第一直行排列,与所述第二金属化层连接的多个连接球沿第二直行排列;以及在所述第一主面之上的第三金属化层,该第三金属化层与所述第一和第二金属化层共面并与该第一和第二金属化层水平隔开;所述第一、第二和第三金属化层分别包括MOS门控器件的源极、漏极和栅极,其中,在所述源极和所述漏极之间有一电流通路,所述电流通路包括一垂直分量。
10.权利要求9的器件,其特征在于,金属化底层延展在所述的第二主面上。
11.权利要求9的器件,其特征在于,所述的第一和第二直行彼此互相平行。
12.权利要求9的器件,其特征在于,所述的硅晶片为具有由给定高度和给定宽度确定的面积的矩形晶片,所述高度大于所述宽度;所述的第一和第二直行的连接球彼此互相平行且绕着穿过所述晶片的对角线对称分布。
13.权利要求10的器件,其特征在于,所述的硅晶片为具有由给定高度和给定宽度确定的面积的矩形晶片,所述高度大于所述宽度;所述的第一和第二直行的连接球彼此互相平行且绕着穿过所述晶片的对角线对称分布。
14.权利要求9的器件,其特征在于,还包括延伸越过所述的第二主面的金属化底层。
15.一种半导体器件,其特征在于,包含具有第一和第二平行表面的硅管芯(30,100);从所述第一表面延伸至所述管芯体内的一种导电类型的区域(52,112);在所述的由多个扩散至所述的一种导电类型区域内的另一种导电类型的扩散(53,115)组成的器件内确定的连接模式;在与所述的多个扩散相接触的所述第一表面之上形成的第一导通电极(31,101);在所述第一表面之上形成的第二导通电极(32,103),该第二导通电极与所述第一导通电极共面、水平隔开且绝缘,并且还与所述管芯体相接触;至少一个分别在每个所述的第一和第二导通电极上形成的焊球连接体;从所述第一导通电极至所述第二导通电极的电流通路,其具有基本垂直于所述第一表面的垂直元件。
16.权利要求15的器件,其特征在于,所述的器件包含功率MOS门控型器件;所述的第一和第二导通电极包含所述器件的主功率电极。
17.权利要求16的器件,其特征在于,所述器件包括在毗邻于所述多个扩散的位置形成且可操作接通和关断所述器件电源的多晶硅栅极(75,121)结构,在所述第一表面之上形成且与所述第一和第二导通电极共面、水平隔开和绝缘并同所述多晶硅栅极结构连接的第三导通电极(34,104);连接于所述第三导通电极的焊球连接体;所有彼此共面的所述的焊球连接体(G)。
18.权利要求17的器件,其特征在于,所述的器件为倒装芯片式功率MOSFET。
19.权利要求15的器件,其特征在于,所述的一种导电类型为P型。
20.权利要求17的器件,其特征在于,所述的一种导电类型为P型。
21.权利要求15的器件,其特征在于,所述硅管芯包括外延形成的硅浓度相对较低的上层以及非外延形成的硅浓度较高的下层。
22.权利要求16的器件,其特征在于,所述硅管芯包括外延形成的硅浓度相对较低的上层以及非外延形成的硅浓度较高的下层。
23.权利要求21的器件,其特征在于,还包括从所述第二导通电极向所述区域的所述下层延伸且连接于所述第二导通电极的浓度相对较高的散热片扩散(90)。
24.权利要求22的器件,其特征在于,还包括从所述第二导通电极向所述区域的所述下层延伸且连接于所述第二导通电极的浓度相对较高的散热片扩散。
25.权利要求21的器件,其特征在于,还包括从所述上层中延伸穿过的沟道以及至少在所述沟道的侧壁上加衬的导电材料。
26.权利要求25的器件,其特征在于,所述器件包括在毗邻于所述多个扩散的位置形成且可操作接通和关断所述器件电源的多晶硅栅极结构,在所述第一表面之上形成且与所述第一和第二导通电极共面、水平隔开和绝缘并同所述多晶硅栅极结构连接的第三导通电极;连接于所述第三导通电极的焊球连接体;所有彼此共面的所述的焊球连接体。
27.权利要求24的器件,其特征在于,所述的器件为倒装芯片式功率MOSFET。
28.权利要求26的器件,其特征在于,所述的器件为倒装芯片式功率MOSFET。
29.权利要求27的器件,其特征在于,所述的一种导电类型为P型。
30.权利要求28的器件,其特征在于,所述的一种导电类型为P型。
31.权利要求17的器件,其特征在于,所述的第二表面被粗糙化以确定用于改进所述器件的冷却的延伸面积。
32.权利要求17的器件,其特征在于,还包括固定于并延伸穿过所述第二表面的金属层。
33.权利要求15的器件,其特征在于,所述的器件从由MOSFET、肖特基二级管、双极晶体管和P/N二级管组成的组中挑选。
34.权利要求15的器件,其特征在于,所述的焊球被安排在大于0.8mm的间距上并具有大于200μ的直径。
35.权利要求33的器件,其特征在于,所述的焊球被安排在大于0.8mm的间距上并具有大于200μ的直径。
Applications Claiming Priority (5)
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US60/224,062 | 2000-08-09 | ||
PCT/US2001/004164 WO2001059842A1 (en) | 2000-02-10 | 2001-02-09 | Vertical conduction flip-chip device with bump contacts on single surface |
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CN (1) | CN1315195C (zh) |
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Families Citing this family (116)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6392290B1 (en) * | 2000-04-07 | 2002-05-21 | Siliconix Incorporated | Vertical structure for semiconductor wafer-level chip scale packages |
US6756273B2 (en) * | 2001-03-12 | 2004-06-29 | Semiconductor Components Industries, L.L.C. | Semiconductor component and method of manufacturing |
US6894397B2 (en) * | 2001-10-03 | 2005-05-17 | International Rectifier Corporation | Plural semiconductor devices in monolithic flip chip |
US6657255B2 (en) * | 2001-10-30 | 2003-12-02 | General Semiconductor, Inc. | Trench DMOS device with improved drain contact |
US6649961B2 (en) * | 2002-04-08 | 2003-11-18 | Fairchild Semiconductor Corporation | Supporting gate contacts over source region on MOSFET devices |
US7071537B2 (en) * | 2002-05-17 | 2006-07-04 | Ixys Corporation | Power device having electrodes on a top surface thereof |
JP2004055812A (ja) * | 2002-07-19 | 2004-02-19 | Renesas Technology Corp | 半導体装置 |
US8884361B2 (en) | 2002-07-19 | 2014-11-11 | Renesas Electronics Corporation | Semiconductor device |
US7129558B2 (en) * | 2002-11-06 | 2006-10-31 | International Rectifier Corporation | Chip-scale schottky device |
US6969909B2 (en) | 2002-12-20 | 2005-11-29 | Vlt, Inc. | Flip chip FET device |
US7038917B2 (en) * | 2002-12-27 | 2006-05-02 | Vlt, Inc. | Low loss, high density array interconnection |
US7034344B2 (en) * | 2003-07-08 | 2006-04-25 | International Rectifier Corporation | Integrated semiconductor power device for multiple battery systems |
JP3917144B2 (ja) * | 2004-04-09 | 2007-05-23 | 株式会社東芝 | 半導体装置 |
JP2005302953A (ja) | 2004-04-09 | 2005-10-27 | Toshiba Corp | 半導体装置 |
US20050275037A1 (en) * | 2004-06-12 | 2005-12-15 | Chung Shine C | Semiconductor devices with high voltage tolerance |
US7352036B2 (en) | 2004-08-03 | 2008-04-01 | Fairchild Semiconductor Corporation | Semiconductor power device having a top-side drain using a sinker trench |
WO2006031886A2 (en) | 2004-09-13 | 2006-03-23 | International Rectifier Corporation | Power semiconductor package |
EP1643558B1 (en) | 2004-09-30 | 2012-05-02 | STMicroelectronics Srl | Vertical power semiconductor device and method of making the same |
JP2006147700A (ja) * | 2004-11-17 | 2006-06-08 | Sanyo Electric Co Ltd | 半導体装置 |
AT504290A2 (de) | 2005-06-10 | 2008-04-15 | Fairchild Semiconductor | Feldeffekttransistor mit ladungsgleichgewicht |
US7589378B2 (en) * | 2005-07-13 | 2009-09-15 | Texas Instruments Lehigh Valley Incorporated | Power LDMOS transistor |
US7282765B2 (en) * | 2005-07-13 | 2007-10-16 | Ciclon Semiconductor Device Corp. | Power LDMOS transistor |
US8692324B2 (en) * | 2005-07-13 | 2014-04-08 | Ciclon Semiconductor Device Corp. | Semiconductor devices having charge balanced structure |
US7504733B2 (en) * | 2005-08-17 | 2009-03-17 | Ciclon Semiconductor Device Corp. | Semiconductor die package |
US7560808B2 (en) * | 2005-10-19 | 2009-07-14 | Texas Instruments Incorporated | Chip scale power LDMOS device |
US7821133B2 (en) * | 2005-10-28 | 2010-10-26 | International Rectifier Corporation | Contact pad structure for flip chip semiconductor die |
US20070148875A1 (en) * | 2005-12-22 | 2007-06-28 | Ming Sun | Common drain dual semiconductor chip scale package and method of fabricating same |
US7446375B2 (en) * | 2006-03-14 | 2008-11-04 | Ciclon Semiconductor Device Corp. | Quasi-vertical LDMOS device having closed cell layout |
US7768075B2 (en) | 2006-04-06 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die packages using thin dies and metal substrates |
US20080036078A1 (en) * | 2006-08-14 | 2008-02-14 | Ciclon Semiconductor Device Corp. | Wirebond-less semiconductor package |
US7589377B2 (en) * | 2006-10-06 | 2009-09-15 | The Boeing Company | Gate structure with low resistance for high power semiconductor devices |
US20080166837A1 (en) * | 2007-01-10 | 2008-07-10 | Tao Feng | Power MOSFET wafer level chip-scale package |
US7880172B2 (en) * | 2007-01-31 | 2011-02-01 | Cree, Inc. | Transistors having implanted channels and implanted P-type regions beneath the source region |
US7952145B2 (en) * | 2007-02-20 | 2011-05-31 | Texas Instruments Lehigh Valley Incorporated | MOS transistor device in common source configuration |
US7482645B2 (en) * | 2007-03-30 | 2009-01-27 | Fairchild Semiconductor Corporation | Method and structure for making a top-side contact to a substrate |
JP5132977B2 (ja) * | 2007-04-26 | 2013-01-30 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US8053346B2 (en) | 2007-04-30 | 2011-11-08 | Hynix Semiconductor Inc. | Semiconductor device and method of forming gate and metal line thereof with dummy pattern and auxiliary pattern |
KR100826987B1 (ko) * | 2007-04-30 | 2008-05-02 | 주식회사 하이닉스반도체 | Mos 트랜지스터를 포함하는 반도체 장치의 레이아웃방법 |
JP2009069255A (ja) | 2007-09-11 | 2009-04-02 | Sony Corp | 撮像装置および合焦制御方法 |
US8928077B2 (en) | 2007-09-21 | 2015-01-06 | Fairchild Semiconductor Corporation | Superjunction structures for power devices |
US8148748B2 (en) | 2007-09-26 | 2012-04-03 | Stmicroelectronics N.V. | Adjustable field effect rectifier |
EP2232559B1 (en) | 2007-09-26 | 2019-05-15 | STMicroelectronics N.V. | Adjustable field effect rectifier |
US8633521B2 (en) | 2007-09-26 | 2014-01-21 | Stmicroelectronics N.V. | Self-bootstrapping field effect diode structures and methods |
US7884390B2 (en) * | 2007-10-02 | 2011-02-08 | Fairchild Semiconductor Corporation | Structure and method of forming a topside contact to a backside terminal of a semiconductor device |
US8097945B2 (en) * | 2007-11-21 | 2012-01-17 | Lynda Harnden, legal representative | Bi-directional, reverse blocking battery switch |
JP2009164288A (ja) * | 2007-12-28 | 2009-07-23 | Sanken Electric Co Ltd | 半導体素子及び半導体装置 |
US7745846B2 (en) * | 2008-01-15 | 2010-06-29 | Ciclon Semiconductor Device Corp. | LDMOS integrated Schottky diode |
DE102008005547B4 (de) * | 2008-01-23 | 2013-08-29 | Infineon Technologies Ag | Leistungshalbleitermodul und Schaltungsanordnung mit einem Leistungshalbleitermodul |
US7955893B2 (en) | 2008-01-31 | 2011-06-07 | Alpha & Omega Semiconductor, Ltd | Wafer level chip scale package and process of manufacture |
US20090267145A1 (en) * | 2008-04-23 | 2009-10-29 | Ciclon Semiconductor Device Corp. | Mosfet device having dual interlevel dielectric thickness and method of making same |
JP4600576B2 (ja) * | 2008-05-08 | 2010-12-15 | 株式会社デンソー | 半導体装置およびその製造方法 |
US8913527B2 (en) * | 2008-06-12 | 2014-12-16 | Nokia Corporation | Multiple die communication system |
US8053891B2 (en) * | 2008-06-30 | 2011-11-08 | Alpha And Omega Semiconductor Incorporated | Standing chip scale package |
US7910992B2 (en) * | 2008-07-15 | 2011-03-22 | Maxim Integrated Products, Inc. | Vertical MOSFET with through-body via for gate |
US8373257B2 (en) * | 2008-09-25 | 2013-02-12 | Alpha & Omega Semiconductor Incorporated | Top exposed clip with window array |
US8058732B2 (en) * | 2008-11-20 | 2011-11-15 | Fairchild Semiconductor Corporation | Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same |
US8174067B2 (en) | 2008-12-08 | 2012-05-08 | Fairchild Semiconductor Corporation | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
US8304829B2 (en) | 2008-12-08 | 2012-11-06 | Fairchild Semiconductor Corporation | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
US7960800B2 (en) * | 2008-12-12 | 2011-06-14 | Fairchild Semiconductor Corporation | Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same |
US7851856B2 (en) * | 2008-12-29 | 2010-12-14 | Alpha & Omega Semiconductor, Ltd | True CSP power MOSFET based on bottom-source LDMOS |
US8049312B2 (en) * | 2009-01-12 | 2011-11-01 | Texas Instruments Incorporated | Semiconductor device package and method of assembly thereof |
US9070670B2 (en) * | 2009-01-29 | 2015-06-30 | International Rectifier Corporation | Electrical connectivity of die to a host substrate |
US8227855B2 (en) | 2009-02-09 | 2012-07-24 | Fairchild Semiconductor Corporation | Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same |
US8148749B2 (en) | 2009-02-19 | 2012-04-03 | Fairchild Semiconductor Corporation | Trench-shielded semiconductor device |
JP5487645B2 (ja) * | 2009-03-02 | 2014-05-07 | 日産自動車株式会社 | 半導体装置及び電力変換装置 |
JP2010205997A (ja) * | 2009-03-04 | 2010-09-16 | Nissan Motor Co Ltd | 半導体装置 |
JP5152526B2 (ja) * | 2009-04-24 | 2013-02-27 | 株式会社デンソー | 車載電力変換装置 |
WO2010127370A2 (en) | 2009-05-01 | 2010-11-04 | Lakota Technologies, Inc. | Series current limiting device |
US8049276B2 (en) | 2009-06-12 | 2011-11-01 | Fairchild Semiconductor Corporation | Reduced process sensitivity of electrode-semiconductor rectifiers |
US8222078B2 (en) * | 2009-07-22 | 2012-07-17 | Alpha And Omega Semiconductor Incorporated | Chip scale surface mounted semiconductor device package and process of manufacture |
US9818857B2 (en) | 2009-08-04 | 2017-11-14 | Gan Systems Inc. | Fault tolerant design for large area nitride semiconductor devices |
US9029866B2 (en) * | 2009-08-04 | 2015-05-12 | Gan Systems Inc. | Gallium nitride power devices using island topography |
US9064947B2 (en) | 2009-08-04 | 2015-06-23 | Gan Systems Inc. | Island matrixed gallium nitride microwave and power switching transistors |
US20110075392A1 (en) * | 2009-09-29 | 2011-03-31 | Astec International Limited | Assemblies and Methods for Directly Connecting Integrated Circuits to Electrically Conductive Sheets |
US9306056B2 (en) * | 2009-10-30 | 2016-04-05 | Vishay-Siliconix | Semiconductor device with trench-like feed-throughs |
JP2011100932A (ja) * | 2009-11-09 | 2011-05-19 | Toshiba Corp | 半導体パッケージ及びdc−dcコンバータ |
US8547162B2 (en) * | 2009-12-23 | 2013-10-01 | Texas Instruments Incorporated | Integration of MOSFETs in a source-down configuration |
US20110148376A1 (en) * | 2009-12-23 | 2011-06-23 | Texas Instruments Incorporated | Mosfet with gate pull-down |
US8791508B2 (en) | 2010-04-13 | 2014-07-29 | Gan Systems Inc. | High density gallium nitride devices using island topology |
JP5401409B2 (ja) * | 2010-07-22 | 2014-01-29 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8362606B2 (en) | 2010-07-29 | 2013-01-29 | Alpha & Omega Semiconductor, Inc. | Wafer level chip scale package |
US8487371B2 (en) | 2011-03-29 | 2013-07-16 | Fairchild Semiconductor Corporation | Vertical MOSFET transistor having source/drain contacts disposed on the same side and method for manufacturing the same |
CN102931238A (zh) * | 2011-08-10 | 2013-02-13 | 美丽微半导体股份有限公司 | 具备肖特基能障的定电流半导体元件 |
JP2013201286A (ja) * | 2012-03-26 | 2013-10-03 | Toshiba Corp | 半導体素子 |
JP5990401B2 (ja) * | 2012-05-29 | 2016-09-14 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
US9202811B2 (en) | 2012-12-18 | 2015-12-01 | Infineon Technologies Americas Corp. | Cascode circuit integration of group III-N and group IV devices |
JP6131114B2 (ja) | 2013-06-13 | 2017-05-17 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP6348703B2 (ja) * | 2013-11-12 | 2018-06-27 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP5715281B2 (ja) * | 2014-04-18 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10164447B2 (en) | 2015-02-26 | 2018-12-25 | Renesas Electronics Corporation | Semiconductor chip, semiconductor device and battery pack |
CN111640742B (zh) | 2015-07-01 | 2021-04-20 | 新唐科技日本株式会社 | 半导体装置 |
JP2018049974A (ja) * | 2016-09-23 | 2018-03-29 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US10692863B2 (en) | 2016-09-30 | 2020-06-23 | Rohm Co., Ltd. | Semiconductor device and semiconductor package |
JP6941502B2 (ja) * | 2016-09-30 | 2021-09-29 | ローム株式会社 | 半導体装置および半導体パッケージ |
IT201600130185A1 (it) * | 2016-12-22 | 2018-06-22 | St Microelectronics Srl | Procedimento di fabbricazione di un dispositivo a semiconduttore integrante un transistore a conduzione verticale, e dispositivo a semiconduttore |
JP6555247B2 (ja) | 2016-12-28 | 2019-08-07 | 日亜化学工業株式会社 | 発光装置及びその製造方法 |
JP2019046991A (ja) * | 2017-09-04 | 2019-03-22 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2019057534A (ja) * | 2017-09-19 | 2019-04-11 | 株式会社東芝 | 半導体装置及び制御システム |
US10600911B2 (en) | 2017-09-26 | 2020-03-24 | Nxp Usa, Inc. | Field-effect transistor and method therefor |
US10424646B2 (en) | 2017-09-26 | 2019-09-24 | Nxp Usa, Inc. | Field-effect transistor and method therefor |
US10522677B2 (en) | 2017-09-26 | 2019-12-31 | Nxp Usa, Inc. | Field-effect transistor and method therefor |
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US10833174B2 (en) | 2018-10-26 | 2020-11-10 | Nxp Usa, Inc. | Transistor devices with extended drain regions located in trench sidewalls |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5077229A (en) * | 1988-10-10 | 1991-12-31 | Eniricerche S.P.A. | Monolithic chemical sensor of the chemfet type incorporating an ion-selective membrane and method of making the same |
US5578841A (en) * | 1995-12-18 | 1996-11-26 | Motorola, Inc. | Vertical MOSFET device having frontside and backside contacts |
JPH1126658A (ja) * | 1997-07-09 | 1999-01-29 | Rohm Co Ltd | Bga型半導体装置のパッケージ構造 |
JPH11135532A (ja) * | 1997-10-30 | 1999-05-21 | New Japan Radio Co Ltd | 半導体チップ及び半導体装置 |
US5986885A (en) * | 1997-04-08 | 1999-11-16 | Integrated Device Technology, Inc. | Semiconductor package with internal heatsink and assembly method |
Family Cites Families (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3761782A (en) * | 1971-05-19 | 1973-09-25 | Signetics Corp | Semiconductor structure, assembly and method |
US4205099A (en) * | 1978-04-14 | 1980-05-27 | Sprague Electric Company | Method for making terminal bumps on semiconductor wafers |
JPS5691478A (en) * | 1979-12-26 | 1981-07-24 | Hitachi Ltd | Manufacture of punch-through type diode |
US4416054A (en) * | 1980-07-01 | 1983-11-22 | Westinghouse Electric Corp. | Method of batch-fabricating flip-chip bonded dual integrated circuit arrays |
JPS5773956A (en) * | 1980-10-27 | 1982-05-08 | Hitachi Ltd | Glass coated semiconductor device |
US4574208A (en) * | 1982-06-21 | 1986-03-04 | Eaton Corporation | Raised split gate EFET and circuitry |
US4541001A (en) * | 1982-09-23 | 1985-09-10 | Eaton Corporation | Bidirectional power FET with substrate-referenced shield |
US4626879A (en) * | 1982-12-21 | 1986-12-02 | North American Philips Corporation | Lateral double-diffused MOS transistor devices suitable for source-follower applications |
US5105243A (en) * | 1987-02-26 | 1992-04-14 | Kabushiki Kaisha Toshiba | Conductivity-modulation metal oxide field effect transistor with single gate structure |
US4866495A (en) * | 1987-05-27 | 1989-09-12 | International Rectifier Corporation | High power MOSFET and integrated control circuit therefor for high-side switch application |
GB8713388D0 (en) * | 1987-06-08 | 1987-07-15 | Philips Electronic Associated | Semiconductor device |
JP2708495B2 (ja) * | 1988-09-19 | 1998-02-04 | 株式会社日立製作所 | 半導体冷却装置 |
US4980740A (en) * | 1989-03-27 | 1990-12-25 | General Electric Company | MOS-pilot structure for an insulated gate transistor |
JPH07118514B2 (ja) * | 1989-04-24 | 1995-12-18 | 株式会社東芝 | 半田バンプ型半導体装置 |
US5994739A (en) * | 1990-07-02 | 1999-11-30 | Kabushiki Kaisha Toshiba | Integrated circuit device |
US5216278A (en) | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
US5241133A (en) | 1990-12-21 | 1993-08-31 | Motorola, Inc. | Leadless pad array chip carrier |
US5416351A (en) * | 1991-10-30 | 1995-05-16 | Harris Corporation | Electrostatic discharge protection |
US5856695A (en) * | 1991-10-30 | 1999-01-05 | Harris Corporation | BiCMOS devices |
US5592025A (en) | 1992-08-06 | 1997-01-07 | Motorola, Inc. | Pad array semiconductor device |
JP3167457B2 (ja) * | 1992-10-22 | 2001-05-21 | 株式会社東芝 | 半導体装置 |
JPH06151863A (ja) * | 1992-11-05 | 1994-05-31 | Oki Electric Ind Co Ltd | 半導体装置 |
US5352926A (en) | 1993-01-04 | 1994-10-04 | Motorola, Inc. | Flip chip package and method of making |
US5355283A (en) | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
US5734201A (en) | 1993-11-09 | 1998-03-31 | Motorola, Inc. | Low profile semiconductor device with like-sized chip and mounting substrate |
US5467253A (en) | 1994-06-30 | 1995-11-14 | Motorola, Inc. | Semiconductor chip package and method of forming |
JPH0832060A (ja) * | 1994-07-13 | 1996-02-02 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
EP0702411B1 (en) * | 1994-09-16 | 2002-11-27 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device with a buried MOS-gate structure |
EP0706208B1 (en) | 1994-10-03 | 2002-06-12 | Kabushiki Kaisha Toshiba | Method of manufacturing of a semiconductor package integral with semiconductor chip. |
US5841197A (en) * | 1994-11-18 | 1998-11-24 | Adamic, Jr.; Fred W. | Inverted dielectric isolation process |
JPH08181307A (ja) * | 1994-12-26 | 1996-07-12 | Nippondenso Co Ltd | 電界効果型パワ−素子集積回路 |
US5688725A (en) * | 1994-12-30 | 1997-11-18 | Siliconix Incorporated | Method of making a trench mosfet with heavily doped delta layer to provide low on-resistance |
US5583376A (en) | 1995-01-03 | 1996-12-10 | Motorola, Inc. | High performance semiconductor device with resin substrate and method for making the same |
JP3412332B2 (ja) * | 1995-04-26 | 2003-06-03 | 株式会社デンソー | 半導体装置 |
JP2679681B2 (ja) | 1995-04-28 | 1997-11-19 | 日本電気株式会社 | 半導体装置、半導体装置用パッケージ及びその製造方法 |
JP3303601B2 (ja) * | 1995-05-19 | 2002-07-22 | 日産自動車株式会社 | 溝型半導体装置 |
US6049108A (en) * | 1995-06-02 | 2000-04-11 | Siliconix Incorporated | Trench-gated MOSFET with bidirectional voltage clamping |
JPH0945692A (ja) | 1995-07-27 | 1997-02-14 | Sharp Corp | 縦型構造トランジスタ及びその製造方法、並びに半導体装置 |
US5844168A (en) | 1995-08-01 | 1998-12-01 | Minnesota Mining And Manufacturing Company | Multi-layer interconnect sutructure for ball grid arrays |
KR0157899B1 (ko) | 1995-09-22 | 1998-12-01 | 문정환 | 기판에 반도체 장치를 부착시키기 위한 연결구조 |
US6831331B2 (en) * | 1995-11-15 | 2004-12-14 | Denso Corporation | Power MOS transistor for absorbing surge current |
US5674785A (en) | 1995-11-27 | 1997-10-07 | Micron Technology, Inc. | Method of producing a single piece package for semiconductor die |
JPH09213753A (ja) | 1995-11-30 | 1997-08-15 | Ricoh Co Ltd | 半導体装置とプリント基板との接続構造体 |
US5866939A (en) | 1996-01-21 | 1999-02-02 | Anam Semiconductor Inc. | Lead end grid array semiconductor package |
US5731709A (en) | 1996-01-26 | 1998-03-24 | Motorola, Inc. | Method for testing a ball grid array semiconductor device and a device for such testing |
US5729052A (en) * | 1996-06-20 | 1998-03-17 | International Business Machines Corporation | Integrated ULSI heatsink |
KR100231276B1 (ko) | 1996-06-21 | 1999-11-15 | 황인길 | 반도체패키지의 구조 및 제조방법 |
US5807783A (en) * | 1996-10-07 | 1998-09-15 | Harris Corporation | Surface mount die by handle replacement |
US5866949A (en) | 1996-12-02 | 1999-02-02 | Minnesota Mining And Manufacturing Company | Chip scale ball grid array for integrated circuit packaging |
WO1998034285A1 (fr) * | 1997-01-31 | 1998-08-06 | Matsushita Electronics Corporation | Element electroluminescent, dispositif electroluminescent a semiconducteur, et leur procede de production |
US5889332A (en) | 1997-02-21 | 1999-03-30 | Hewlett-Packard Company | Area matched package |
US6117299A (en) * | 1997-05-09 | 2000-09-12 | Mcnc | Methods of electroplating solder bumps of uniform height on integrated circuit substrates |
JP3593847B2 (ja) * | 1997-05-14 | 2004-11-24 | 株式会社デンソー | 電力用半導体装置 |
JPH10335567A (ja) | 1997-05-30 | 1998-12-18 | Mitsubishi Electric Corp | 半導体集積回路装置 |
US5831832A (en) | 1997-08-11 | 1998-11-03 | Motorola, Inc. | Molded plastic ball grid array package |
JP3663036B2 (ja) * | 1997-08-25 | 2005-06-22 | 三洋電機株式会社 | 半導体装置及びその製造方法 |
JP3395603B2 (ja) * | 1997-09-26 | 2003-04-14 | 株式会社豊田中央研究所 | 横型mos素子を含む半導体装置 |
JP3329707B2 (ja) * | 1997-09-30 | 2002-09-30 | 株式会社東芝 | 半導体装置 |
JP3045122B2 (ja) * | 1997-10-20 | 2000-05-29 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6373100B1 (en) * | 1998-03-04 | 2002-04-16 | Semiconductor Components Industries Llc | Semiconductor device and method for fabricating the same |
CN1166002C (zh) * | 1998-04-23 | 2004-09-08 | 国际整流器有限公司 | P沟道槽型金属氧化物半导体场效应晶体管结构 |
JP2000022140A (ja) * | 1998-06-26 | 2000-01-21 | Nissan Motor Co Ltd | 半導体装置及びその製造方法 |
US6133634A (en) * | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
US6392290B1 (en) * | 2000-04-07 | 2002-05-21 | Siliconix Incorporated | Vertical structure for semiconductor wafer-level chip scale packages |
US6713814B1 (en) * | 2002-08-05 | 2004-03-30 | National Semiconductor Corporation | DMOS transistor structure with gate electrode trench for high density integration and method of fabricating the structure |
-
2001
- 2001-02-09 TW TW090102979A patent/TW493262B/zh not_active IP Right Cessation
- 2001-02-09 US US09/780,080 patent/US6653740B2/en not_active Expired - Lifetime
- 2001-02-09 JP JP2001559065A patent/JP4646284B2/ja not_active Expired - Fee Related
- 2001-02-09 KR KR1020067025067A patent/KR100721139B1/ko not_active IP Right Cessation
- 2001-02-09 AU AU2001238081A patent/AU2001238081A1/en not_active Abandoned
- 2001-02-09 KR KR1020027010402A patent/KR100699552B1/ko not_active IP Right Cessation
- 2001-02-09 EP EP01910483A patent/EP1258040A4/en not_active Ceased
- 2001-02-09 WO PCT/US2001/004164 patent/WO2001059842A1/en active Application Filing
- 2001-02-09 CN CNB018049087A patent/CN1315195C/zh not_active Expired - Fee Related
-
2003
- 2003-07-03 US US10/613,326 patent/US20040021233A1/en not_active Abandoned
-
2007
- 2007-04-02 JP JP2007096790A patent/JP2007235150A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5077229A (en) * | 1988-10-10 | 1991-12-31 | Eniricerche S.P.A. | Monolithic chemical sensor of the chemfet type incorporating an ion-selective membrane and method of making the same |
US5578841A (en) * | 1995-12-18 | 1996-11-26 | Motorola, Inc. | Vertical MOSFET device having frontside and backside contacts |
US5986885A (en) * | 1997-04-08 | 1999-11-16 | Integrated Device Technology, Inc. | Semiconductor package with internal heatsink and assembly method |
JPH1126658A (ja) * | 1997-07-09 | 1999-01-29 | Rohm Co Ltd | Bga型半導体装置のパッケージ構造 |
JPH11135532A (ja) * | 1997-10-30 | 1999-05-21 | New Japan Radio Co Ltd | 半導体チップ及び半導体装置 |
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US20040021233A1 (en) | 2004-02-05 |
WO2001059842A1 (en) | 2001-08-16 |
EP1258040A4 (en) | 2009-07-01 |
JP2004502293A (ja) | 2004-01-22 |
US20010045635A1 (en) | 2001-11-29 |
KR100721139B1 (ko) | 2007-05-25 |
EP1258040A1 (en) | 2002-11-20 |
KR20070010188A (ko) | 2007-01-22 |
TW493262B (en) | 2002-07-01 |
KR100699552B1 (ko) | 2007-03-26 |
US6653740B2 (en) | 2003-11-25 |
AU2001238081A1 (en) | 2001-08-20 |
JP2007235150A (ja) | 2007-09-13 |
KR20020073547A (ko) | 2002-09-26 |
JP4646284B2 (ja) | 2011-03-09 |
CN1401141A (zh) | 2003-03-05 |
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