CN111696943A - 具有带有堤状构造的管芯焊盘的半导体器件 - Google Patents

具有带有堤状构造的管芯焊盘的半导体器件 Download PDF

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Publication number
CN111696943A
CN111696943A CN202010165084.XA CN202010165084A CN111696943A CN 111696943 A CN111696943 A CN 111696943A CN 202010165084 A CN202010165084 A CN 202010165084A CN 111696943 A CN111696943 A CN 111696943A
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metal pad
region
power transistor
layer
metal
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CN202010165084.XA
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Inventor
R·佩尔泽
F·洛佩兹
A·马格兰吉特
S·A·F·什克扎卡里亚
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

公开了一种半导体器件，包括：半导体衬底；形成在该半导体衬底中的功率晶体管，该功率晶体管包括其中形成有一个或多个功率晶体管单元的有源区；形成在半导体衬底上方并且基本上覆盖功率晶体管的所有有源区的第一金属焊盘，第一金属焊盘电连接到功率晶体管的有源区中的源极或发射极区域，第一金属焊盘包括内部区域，该内部区域由***区域横向包围，该***区域比内部区域厚；以及通过管芯附接材料附接到第一金属焊盘的内部区域的第一互连板或半导体管芯。还描述了对应的制造方法。

Description

具有带有堤状构造的管芯焊盘的半导体器件
背景技术
许多半导体器件技术使用金属夹来进行源极/发射极焊盘互连。相邻接合焊盘之间的交叉污染与利用焊膏材料的夹接合有关。焊膏材料的不期望的分布或散布通常被称为“溢流”，并可能导致严重的管芯焊盘腐蚀。基于Cu的逻辑管芯焊盘对焊膏材料溢流特别敏感。例如，典型的Cu-到-Cu钉头接合工艺不允许在Cu管芯焊盘表面上有任何有机异物或腐蚀性副产物。
因此，需要改进的半导体器件互连技术。
发明内容
根据半导体器件的实施例，半导体器件包括：半导体衬底；形成在半导体衬底中的功率晶体管，该功率晶体管包括有源区，在有源区中形成一个或多个功率晶体管单元；第一金属焊盘，其形成在半导体衬底上方并基本上覆盖功率晶体管的所有的有源区，第一金属焊盘电连接至功率晶体管的有源区中的源极或发射极区域，第一金属焊盘包括由***区域横向包围的内部区域，该***区域比内部区域厚；以及第一互连板或半导体管芯，其通过管芯附接材料附接到第一金属焊盘的内部区域。
在一个实施例中，第一金属焊盘的内部区域具有在5μm至10μm的范围内的厚度，并且第一金属焊盘的***区域具有约20μm或更大的厚度。
单独地或组合地，半导体衬底可以具有250μm或更小的厚度，例如，具有60μm或更小的厚度。
单独地或组合地，第一金属焊盘的***区域可以比管芯附接材料厚。
单独地或组合地，管芯附接材料可以比第一金属焊盘的***区域厚，使得第一互连板或半导体管芯的底表面设置在第一金属焊盘的***区域的顶表面上方。
单独地或组合地，第一互连板的底表面可以具有一个或多个结构，该一个或多个结构从第一金属焊盘的***区域向内横向设置并且朝向第一金属焊盘的内部区域垂直延伸。
单独地或组合地，第一金属焊盘的***区域可以被分成多个段，并且所述段中的相邻段可以通过间隙横向分开。
单独地或组合地，功率晶体管可以包括多个输出沟道，每个输出沟道被配置为向负载输送电流，功率晶体管可以包括针对每个输出沟道的个体有源区，并且第一金属焊盘可以基本上覆盖功率晶体管的有源区中的第一个。
单独地或组合地，半导体器件还可以包括：多个附加的金属焊盘，其形成在半导体衬底上方，每个附加的金属焊盘基本上覆盖功率晶体管的有源区中的对应一个，每个附加的金属焊盘电连接到基本上被金属焊盘覆盖的有源区中的源极或发射极区域，每个金属焊盘包括由***区域横向包围的内部区域，***区域比内部区域厚；以及多个附加的互连板，每个附加的互连板通过管芯连接材料附接到附加的金属焊盘中的对应一个的内部区域。
单独地或组合地，半导体器件还可以包括作为功率晶体管而集成在半导体衬底的不同区域中的一个或多个逻辑器件。
单独地或组合地，第一金属焊盘可以是Cu焊盘，并且第一互连板可以是Cu夹。
根据制造半导体器件的方法的实施例，该方法包括：在半导体衬底中形成功率晶体管，该功率晶体管包括有源区，在有源区中形成一个或多个功率晶体管单元；在半导体衬底上方形成第一金属焊盘，并且该第一金属焊盘基本上覆盖功率晶体管的所有的有源区，第一金属焊盘电连接至功率晶体管的有源区中的源极或发射极区域，第一金属焊盘包括由***区域横向包围的内部区域，该***区域比内部区域厚；以及通过管芯附接材料将第一互连板或半导体管芯附接到第一金属焊盘的内部区域。
在一个实施例中，形成第一金属焊盘包括：在半导体衬底上方沉积第一Cu层，并且该第一Cu层基本上覆盖功率晶体管的所有的有源区；在第一Cu层的与第一金属焊盘的内部区域相对应的部分上形成掩模，该掩模被配置为防止Cu沉积；以及在第一Cu层的未被掩模保护的部分上沉积第二Cu层，以形成第一金属焊盘的***区域，第一金属焊盘的内部区域由第一Cu层中的在第二Cu层的沉积期间被掩模保护的部分形成。第一Cu层可以具有在5μm至10μm的范围内的厚度，并且第二Cu层可以具有在10μm至20μm的范围内的厚度。
在另一实施例中，形成第一金属焊盘可以包括：在半导体衬底上方沉积Cu层，并且该Cu层基本上覆盖功率晶体管的所有的有源区；在Cu层的与第一金属焊盘的***区域相对应的部分上形成掩模，该掩模被配置为防止Cu蚀刻；以及蚀刻Cu层的未被掩模保护的部分以形成第一金属焊盘的内部区域，第一金属焊盘的***区域由所述Cu层的在所述Cu层的蚀刻期间被掩模保护的部分形成。所沉积的Cu层的厚度可以为约20μm或更大，并且Cu层的蚀刻部分的厚度可以在5μm至10μm的范围内。
单独地或组合地，第一金属焊盘的***区域可以比管芯附接材料厚，并且其中，将第一互连板或半导体管芯附接到第一金属焊盘的内部区域可以包括：将管芯附接材料沉积在第一金属焊盘的内部区域上；以及在使用第一金属焊盘的***区域将第一互连板与第一金属焊盘对准的同时，将第一互连板与管芯附接材料接触放置。
单独地或组合地，管芯附接材料可以比第一金属焊盘的***区域厚，并且其中，将第一互连板或半导体管芯附接到第一金属焊盘的内部区域可以包括：将管芯附接材料沉积在第一金属焊盘的内部区域上；以及在使用管芯附接材料的表面张力使第一互连板与第一金属焊盘对准的同时，将第一互连板与管芯附接材料接触放置。
单独地或组合地，第一互连板的底表面可以具有从第一金属焊盘的***区域向内横向设置的一个或多个结构，并且将第一互连板或半导体管芯附接至第一金属焊盘的内部区域可以包括：在第一金属焊盘的内部区域上沉积管芯附接材料；以及将第一互连板与管芯附接材料接触放置，以使得在第一互连板的底表面处的一个或多个特征朝向第一金属焊盘的内部区域垂直延伸，并且从第一金属焊盘的***区域向内横向设置，以使第一互连板与第一金属焊盘对准。
单独地或组合地，功率晶体管可以包括多个输出沟道，每个输出沟道被配置为向负载输送电流，功率晶体管可以包括针对每个输出沟道的个体有源区，第一金属焊盘可以基本上覆盖功率晶体管的有源区中的第一个，并且该方法还可以包括：在半导体衬底上方形成多个附加的金属焊盘，每个附加的金属焊盘基本上覆盖功率晶体管的有源区中的对应一个，每个附加的金属焊盘电连接到基本上被金属焊盘覆盖的有源区中的源极或发射极区域，每个金属焊盘包括由***区域横向包围的内部区域，该***区域比内部区域厚；以及通过管芯附接材料将多个附加的互连板中的每个附接到附加的金属焊盘中的对应一个的内部区域。
本领域技术人员在阅读以下具体实施方式并在查看附图时将认识到附加的特征和优点。
附图说明
附图的要素不必相对于彼此成比例。相同的附图标记表示对应的相似部分。可以组合各种所示实施例的特征，除非它们相互排斥。在附图中描绘了实施例，并且在下面的描述中详细描述了实施例。
图1示出了具有带有堤状构造的金属焊盘的半导体器件的实施例的侧视透视图。
图2A示出了具有带有堤状构造的金属焊盘的半导体器件的另一实施例的俯视图。
图2B示出了沿图2A中标记为A-A'的线的半导体器件的截面图。
图2C示出了与图2A-图2B所示的器件相似的半导体器件，但是半导体管芯附接到具有堤状构造的金属焊盘的内部区域。
图3A至图3C示出了形成如图2A至图2B所示的具有堤状构造的金属焊盘102的实施例的相应的俯视图。
图4示出了附接到图3A至图3C所示的第一金属焊盘的较薄内部区域的互连板的实施例的侧视透视图。
图5至图7示出了具有带有堤状构造的金属焊盘的半导体器件的其他实施例的相应截面图，每个器件具有不同的芯片焊盘-到-互连接口。
图8示出了半导体器件的实施例的俯视图，该半导体器件具有4个单独的有源区、4个输出沟道、以及针对每个有源区/输出沟道的具有堤状构造的单独的金属焊盘。
图9A至图9E示出了在制造具有带有堤状构造的一个或多个金属焊盘的半导体器件的不同阶段期间的相应截面图。
图10A至图10C示出了根据另一实施例的在制造具有带有堤状构造的一个或多个金属焊盘的半导体器件的不同阶段期间的相应截面图。
具体实施方式
本文所述的实施例提供了用于半导体管芯的金属焊盘结构以及对应的制造方法。金属焊盘具有由***区域横向包围的内部区域。***区域比内部区域厚。金属焊盘的内部区域被配置用于附接到诸如金属夹或金属块的互连板，或者用于附接到另一半导体管芯。金属焊盘的较厚的***区域形成堤状结构，以用于保持用于将互连板或另一半导体管芯附接到金属焊盘的材料。同样有益的是，由于使金属焊盘的内部区域较薄，因此在器件的加热和冷却期间，金属焊盘在半导体衬底上施加较小的机械应力。
图1示出了具有带有堤状构造的金属焊盘102的半导体器件100的实施例的侧视透视图。根据该实施例，半导体器件100包括半导体衬底104和形成在半导体衬底104中的功率晶体管，例如功率MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极晶体管)、HEMT(高电子迁移率晶体管)等。一个或多个逻辑器件可以集成在半导体衬底104的与功率晶体管不同的区域中，例如，以用于控制功率晶体管。例如，驱动器电路和/或控制器可以集成在半导体衬底104中，以用于控制功率晶体管。
半导体衬底104可以相对较厚，例如大于250μm厚，或相对较薄，例如小于250μm厚。半导体衬底104可以由适合于制造功率晶体管的任何半导体材料制成。这种材料的示例包括但不限于诸如硅(Si)或锗(Ge)的元素半导体材料、诸如碳化硅(SiC)或硅锗(SiGe)的IV族化合物半导体材料、诸如氮化镓(GaN)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、磷化铟镓(InGaPa)、氮化铝镓(AlGaN)、氮化铝铟(AlInN)、氮化铟镓(InGaN)、氮化铝镓铟(AlGaInN)或磷化铟镓砷(InGaAsP)的二元、三元或四元III-V半导体材料，等待。
形成在半导体衬底104中的功率晶体管包括有源区，在有源区中形成一个或多个功率晶体管单元。有源区被具有堤状构造的金属焊盘102覆盖，并且因此在图1中看不到。具有堤状构造的金属焊盘102形成在半导体衬底104上方，并且基本上覆盖功率晶体管的所有的有源区。金属焊盘102电连接到功率晶体管的有源区中的源极或发射极区域。金属焊盘102具有由***区域108横向包围的内部区域106。***区域108比内部区域106厚。金属焊盘102的较厚的***区域108形成堤状结构，以用于保持用于将互连板或另一半导体管芯附接到金属焊盘102的材料。图1并未示出附接到具有堤状构造的金属焊盘102的互连板或另一半导体管芯，以便提供整个金属焊盘102的无障碍视图。
在一个实施例中，具有堤状构造的金属焊盘102的内部区域106具有在约5μm至约20μm的范围内的厚度t1，并且金属焊盘102的***区域108具有约20μm或更大的厚度t2。可以预期金属焊盘102的内部和***区域106、108的其他厚度范围。通常，具有堤状构造的金属焊盘102的内部和***区域106、108可以具有任何期望的厚度，只要***区域108比内部区域106厚即可。例如在半导体衬底104具有60μm或更小的厚度的情况下，具有较薄的内部区域106和较厚的***区域108的这种金属焊盘102对于较薄的半导体管芯特别有利，因为在器件100的加热和冷却期间，金属焊盘102在半导体衬底104上施加较小的机械应力。
具有带有堤状构造的金属焊盘102的半导体器件100的侧面可以包括附加的金属结构，例如形成在与具有堤状构造的金属焊盘102相同的金属层中的其他金属焊盘110和/或金属迹线112。例如，具有带有堤状构造的金属焊盘102的半导体器件的侧面还可以包括栅极焊盘110，该栅极焊盘110电连接到功率晶体管的有源区中的栅电极。栅极焊盘110可以或可以不具有与具有堤状构造的金属焊盘102的***区域108相同的厚度。一个或多个金属迹线112可以形成在半导体器件100的具有带有堤状构造的金属焊盘102的侧面。金属迹线112为功率晶体管提供信号布线，并且可以或可以不具有与具有堤状构造的金属焊盘102的内部区域106相同的厚度。
图2A示出了具有带有堤状构造的金属焊盘102的半导体器件200的另一实施例的俯视图，并且图2B示出了沿图2A中标记为A-A'的线的半导体器件200的截面图。图2A和图2B所示的实施例类似于图1所示的实施例。然而，不同的是，半导体器件200在半导体器件200的具有带有较薄的内部区域106和较厚的***区域108的金属焊盘102的侧面包括附加的焊盘202、204。附加的焊盘202、204可以用于电接触形成在半导体衬底104中的功率晶体管的不同或附加区域，和/或可以用于从半导体器件200的背面到正面进行电接触。
图2B还示出了在将诸如金属夹或金属块的互连板206附接到具有堤状构造的金属焊盘102的内部区域106之后的半导体器件200。互连板206通过诸如焊料、导电胶、导电带等的管芯附接材料208附接到金属焊盘102的内部区域106。互连板206和金属焊盘102的附接互连板206的内部区域106均可以具有一个或多个附加层210、212，例如粘合促进层。
图2B还示出了形成在半导体衬底104中的功率晶体管的有源区214。有源区214包括一个或多个功率晶体管单元。每个功率晶体管单元包括通过电介质218与半导体衬底216绝缘的栅电极216、第一导电类型的源极或发射极区域220和第二导电类型的主体区域222，其提供由施加到栅电极216的电压控制的沟道。为了简化图示，在图2B中示出了一个功率晶体管单元。每个栅电极216可以设置在形成在半导体衬底104中的栅极沟槽224中，并且其可以或可以不包括处于栅电极216下方并与其绝缘的场电极226。根据图2B所示的实施例，功率晶体管是垂直器件，其在主体区域222与半导体衬底104的背面之间具有漂移区228，该背面形成功率晶体管的漏极或集电极区域。诸如引线框架的管芯垫、金属块、衬底的金属化表面的金属主体230通过管芯附接材料232附接到半导体衬底104的背面，以形成半导体器件200的漏极/集电极端子。源极/发射极端子在器件200的相对侧，并且部分地由具有较薄的内部区域106和较厚的***区域108的金属焊盘102、以及附接到金属焊盘102的较薄的区域106的互连板206形成。在一个实施例中，具有堤状构造的金属焊盘102是Cu焊盘，并且互连板207是Cu夹。功率晶体管可以替代地具有与半导体衬底104的正面绝缘的平面栅电极和/或可以是横向器件而不是垂直器件。
图2C示出了类似于图2A-2B所示的器件200的半导体器件300，但是半导体管芯302附接到具有堤状构造的金属焊盘102的内部区域106而不是互连板。半导体管芯302可以具有通过管芯附接材料208附接到金属焊盘102的内部区域106的金属化表面304、以及在半导体管芯302的相对侧的一个或多个管芯焊盘306。钝化层308可以被施加到半导体管芯302的该侧，并且电导体310可以附接到管芯焊盘306以提供与管芯302的不同端子的电连接。在一个实施例中，下部管芯104和上部管芯302是经由具有堤状构造的金属焊盘102以半桥构造电连接的功率晶体管管芯。
图3A至图3C示出了形成如图2A至图2B所示的具有堤状构造的金属焊盘102的实施例。
图3A示出了形成在半导体衬底104之上的第一图案化金属层400。在一个实施例中，第一图案化金属层400是通过电化学沉积(ECD)形成的Cu层。第一图案化金属层400形成金属迹线402和金属焊盘基座404、406、408、410。
图3B示出了形成在第一图案化金属层400上的第二图案化金属层412。在一个实施例中，第二图案化金属层412是由ECD形成的Cu层。在需要较厚金属的地方形成第二图案化金属层412。这包括第一金属焊盘414/102，其中堆叠在第一图案化金属层400上的第二图案化金属层412形成第一金属焊盘414/102的较厚的***区域416。第一金属焊盘414/102还具有仅由第一图案化金属层400形成的较薄的内部区域418。第二图案化金属层412也可以用于形成其他厚金属焊盘420、422、424。第二图案化金属层400、412可以是如上所述的Cu层，或者可以是诸如Al、AlCu、Au等其他类型的金属层。第一和第二图案化金属层400、412可以包括诸如防氧化层、粘合促进层等的附加金属层。在一个实施例中，第二图案化金属层412的外横向边缘426与第一图案化金属层400的外横向边缘428沿第一金属焊盘414/102的一侧或多侧向内间隔开距离d1，例如间隔开约5μm。第二图案化金属层412的外横向边缘426可以替代地沿第一金属焊盘414/102的一侧或多侧与第一图案化金属层400的外横向边缘428垂直对准。
图3C示出了附接到第一金属焊盘414/102的较薄内部区域418的互连板430。互连板430可以通过诸如焊料、导电胶、导电带等的管芯附接材料(视线之外)附接到第一金属焊盘414/102的内部区域418。第二图案化金属层412的内横向边缘432可以沿第一金属焊盘414/102的一侧或多侧与互连板430的横向边缘434间隔开距离d2，例如，间隔开约100μm。
如本文先前所述，第一金属焊盘414/102的***区域416具有堤状形状。如图3B所示，在第一金属焊盘414/102的整个***之上，堤状形状可以是连续且不间断的。替代地，第二图案化金属层412可以被构造为使得第一金属焊盘414/102的***区域416被划分为多个段，其中所述段中的相邻段横向分开一定间隙。这种间隙由图3B中的虚线框指示。因此，第一金属焊盘414/102的***区域416的堤状形状可以沿第一金属焊盘414/102的所有侧、沿第一金属焊盘414/102的一些侧但并非全部侧是连续且不间断的，在壁段之间可以具有断裂，或具有任何其他类型的所需形状或构造。
图4示出了附接到图3A至图3C中所示的第一金属焊盘414/102的较薄内部区域416的互连板430的实施例的侧视透视图。根据该实施例，互连板430是金属夹，例如Cu夹。金属夹具有沿第一层级L1延伸的第一区域436、沿第一层级L1上方的第二层级L2延伸的第二区域438、以及连接第一和第二区域436、438并在第一和第二层级L1、L2之间提供过渡的中间区域440。金属夹430的第一区域436附接到第一金属焊盘414/102的较薄的内部区域418，并且金属夹430的中间区域440提供高度过渡，使得金属夹430不接触第一金属焊盘414/102的***区域416。
图5至图7示出了半导体器件的其他实施例的相应截面图，每个半导体器件具有不同的芯片焊盘-到-互连接口。
在图5中，具有堤状构造的金属焊盘102的***区域108比用于将互连板206(或另一半导体管芯)附接到金属焊盘102的较薄的内部区域106的管芯附接材料208厚。根据实施例，当放置第一互连板206(或另一半导体管芯)时，金属焊盘102的***区域108可以用作引导件，以确保互连板206(或另一半导体管芯)适当地着落在金属焊盘102的较薄的内部区域106上。例如，在将管芯附接材料208沉积在金属焊盘102的内部区域106上之后，可以在使用金属焊盘102的***区域108使互连板206(或另一半导体管芯)与金属焊盘102对准的同时，将互连板206(或另一半导体管芯)与管芯附接材料208接触放置。
在图6中，管芯附接材料208比具有堤状构造的金属焊盘102的***区域108厚，使得第一互连板206的底表面500(或替代地，另一半导体管芯的底表面)设置在金属焊盘102的***区域108的顶表面502上方。根据该实施例，管芯附接材料208的属性允许互连板206(或另一半导体管芯)在具有堤状构造的金属焊盘102的较薄的内部区域106上自动居中。例如，在将管芯附接材料208沉积在金属焊盘102的内部区域206上之后，可以在使用管芯附接材料208的表面张力使互连板206(或另一半导体管芯)与金属焊盘102对准的同时，将互连板206(或另一半导体管芯)与管芯附接材料208接触放置。互连板206(或另一半导体管芯)被软着落在金属焊盘102的较薄的内部区域106上，这意味着互连板206(或另一半导体管芯)没有被压入管芯附接材料208中，而是被轻轻地放置在管芯附接材料208上。在将胶作为管芯附接材料208的情况下，胶的表面张力使互连板206(或另一半导体管芯)居中。该方法产生了互连板206(或另一半导体管芯)相对于具有堤状构造的金属焊盘102的粗略对准。
在图7中，互连板206的底表面500具有一个或多个结构504，该结构504从具有堤状构造的金属焊盘102的***区域108向内横向设置，并且朝向金属焊盘102的内部区域106垂直延伸。一个或多个结构504可以例如通过压印形成并且在着落工艺期间辅助互连板206与金属焊盘102的内部区域106的对准。例如，在将管芯附接材料208沉积在金属焊盘102的内部区域106上之后，可以将互连板206与管芯附接材料208接触放置，以使得在互连板206的底表面500处的一个或多个特征504朝向金属焊盘102的内部区域106垂直延伸，并且从金属焊盘102的***区域108向内横向设置，以使互连板206与金属焊盘102对准。
图1、图2A-2B、图3A-3C和图5-7所示的半导体器件实施例示出了具有较薄的内部区域和较厚的***区域的一个金属焊盘、以及附接到金属焊盘的较薄的内部区域的一个互连板(或另一半导体管芯)。这样做只是为了便于说明。通常，本文所述的半导体器件中包括的功率晶体管可以具有用于将电流输送到负载的一个或多个输出沟道或相。在单个输出沟道的情况下，半导体器件是单相器件。在多个(多于一个)输出沟道的情况下，半导体器件是诸如多相电压调节器的多相器件。
包括在本文所述的每个半导体器件中的功率晶体管具有用于每个输出沟道的个体有源区以及用于每个输出沟道的本文所述种类的单独的堤状金属焊盘。通常，对于具有N个输出沟道(其中N为大于或等于1的整数)的功率晶体管，对应的半导体器件具有N个单独的有源区和N个本文所述种类的堤状金属焊盘——器件的每个输出沟道/有源区一个。一个或多个互连板可以附接到N个堤状金属焊盘中的每一个。也就是说，每个沟道的有源区取决于该沟道的Ron(导通电阻)要求。这样，取决于每个沟道的有源区尺寸，可以使用不同尺寸的互连板。例如，功率晶体管可以具有1个较大的有源区和3个较小的有源区。较小的互连板可以用于3个较小的有源区，并且1个较大的互连板或多个较小的互连板可以用于较大的有源区。
图8示出了具有4个单独的有源区并因此具有4个输出沟道的半导体器件600的实施例的俯视图。每个有源区基本上被本文所述种类的单独的堤状金属焊盘102覆盖。每个堤状金属焊盘102电连接到下面的有源区中的源极或发射极区域，并且具有由较厚的***区域108横向包围的较薄的内部区域106。一个或多个互连板或另一半导体管芯通过管芯附接材料附接至每个堤状金属焊盘102的内部区域106。互连板/附加的半导体管芯未在图8中示出，以使堤状金属焊盘102的细节是清楚的。
图9A至图9E示出了在制造具有本文所述种类的一个或多个堤状金属焊盘的半导体器件的不同阶段期间的相应截面图。
图9A示出了形成在半导体衬底702之上的诸如TiW的阻挡层700、以及形成在阻挡层700上的Cu种晶层704。可以例如通过物理气相沉积(PVD)来沉积阻挡层700和Cu种晶层704。阻挡层700和Cu种晶层704可以相对薄，例如均为约300nm厚。
图9B示出了形成在Cu种晶层704上的第一Cu层706。第一Cu层706可以使用光刻胶掩模708通过ECD形成，以将沉积的Cu图案化为金属焊盘的基座708和用于信号布线的金属迹线710。在一个实施例中，第一Cu层706具有约5μm至约20μm的范围内的厚度，例如，约5μm至约10μm的范围内的厚度。
图9C示出了第一Cu层706的对应于图案化到由掩模712(例如，抗蚀剂)保护的第一Cu层706中的堤状金属焊盘的内部区域/基座708、以及金属迹线710的部分。掩模712防止Cu随后沉积在掩蔽区域中的第一Cu层706上。然后第二Cu层714沉积在第一Cu层706的未被掩模712保护的部分上，以形成堤状金属焊盘102的***区域108，并且加厚其他焊盘(如果需要)。堤状金属焊盘102的内部区域106由第一Cu层706的在沉积第二Cu层714期间由掩模712保护的部分形成。相同的掩模可以用于形成两个Cu层706、714，其中，在沉积第一Cu层706之后去除掩模的部分以在所需区域中形成第二Cu层714。在一个实施例中，第二Cu层714具有约10μm至约20μm的范围内的厚度，例如，约10μm至约15μm的范围内的厚度。
图9D示出了在去除用于Cu沉积的掩模708/712之后、在形成覆盖金属迹线710和金属焊盘708/106的***的部分的新掩模716(例如，酰亚胺掩模)之后、并且在诸如钝化的保护层718形成在第二Cu层714的暴露部分上之后的结构。在采用Ag蚀刻的情况下，第二Cu层714的暴露部分由保护层718保护。
图9E示出了在诸如金属夹或金属块或另一半导体管芯的互连板206附接到堤状金属焊盘102的较薄的内部区域708/106之后、在诸如导线凸块、柱、垂直(切割)接合线等导体720附接到接合焊盘708中的不具有堤状构造的其他接合焊盘之后、并且在诸如引线框架的管芯垫、金属块、衬底的金属化表面等金属主体230附接到半导体衬底104的背面之后的结构。可以使用诸如焊料、导电胶、导电带等的管芯附接材料208、232来促进一些或所有附接操作。诸如粘合促进层的附加层212、304、722可以与管芯附接材料208、232结合使用。
图10A至图10C示出了根据另一实施例的在制造具有本文所述种类的一个或多个堤状金属焊盘的半导体器件的不同阶段期间的相应截面图。
图10A示出了形成在半导体衬底802之上的诸如TiW的阻挡层800、形成在阻挡层800上的Cu层804和形成在Cu层804上的可选的银或铝层806。在一个实施例中，阻挡层800相对薄，例如约300nm厚，并且Cu层804相对厚，例如至少10μm或至少20μm厚。在银或铝层806沉积在Cu层804上的情况下，可选的层806比Cu层804薄，例如，在Ag的情况下约200nm，或者在Al的情况下约50nm。
图10B示出了Cu层804，其例如通过光刻和蚀刻而被图案化以在Cu层804中形成金属焊盘和金属迹线结构808、810、812。图案化工艺可以包括例如使用稀氢氟酸的Ag或Al蚀刻，然后是例如使用H3PO4或H2O2的Cu蚀刻，然后是例如使用H2O2的TiW蚀刻。在Cu层图案化工艺之后，形成诸如酰亚胺掩模的掩模814，其覆盖金属迹线结构812、将具有均匀厚度的金属焊盘结构810以及堤状金属焊盘结构808的***。然后，例如使用H3PO4或H2O2来蚀刻例如未被掩模814保护的Cu层804的暴露部分以形成具有堤状构造的金属焊盘102，其具有较薄的内部区域106和较厚的***区域108。Cu层804的蚀刻部分的厚度t_ec可以在5μm至10μm的范围内。堤状金属焊盘102的***区域108由在蚀刻Cu层804期间由掩模814保护的Cu层804的部分形成。如本文先前所描述，诸如金属夹或金属块、或另一半导体管芯的互连板接着可以附接到堤状金属焊盘102的较薄的内部区域106。
诸如“第一”、“第二”等的术语用于描述各种元件、区域、部分等，并且也不旨在进行限制。在整个说明书中，相似的术语指代相似的元件。
如本文中所使用的，术语“具有”、“包含”、“包括”等是开放式术语，其指示所陈述的元件或特征的存在，但不排除附加的元件或特征。除非上下文另外明确指出，否则冠词“一”和“所述”旨在包括复数和单数。
应当理解，除非另外特别指出，否则本文所述的各种实施例的特征可以彼此组合。
尽管本文已经示出并描述了特定实施例，但是本领域普通技术人员将理解，在不脱离本发明的范围的情况下，各种替代和/或等效实施方式可以代替所示出和描述的特定实施例。本申请旨在覆盖本文讨论的特定实施例的任何改编或变型。因此，旨在使本发明仅由权利要求及其等同物限制。

Claims (20)

1.一种半导体器件，包括：
半导体衬底；
形成在所述半导体衬底中的功率晶体管，所述功率晶体管包括有源区，在所述有源区中形成一个或多个功率晶体管单元；
第一金属焊盘，其形成在所述半导体衬底上方并基本上覆盖所述功率晶体管的所有所述有源区，所述第一金属焊盘电连接至所述功率晶体管的所述有源区中的源极或发射极区域，所述第一金属焊盘包括由***区域横向包围的内部区域，所述***区域比所述内部区域厚；以及
第一互连板或半导体管芯，其通过管芯附接材料附接至所述第一金属焊盘的所述内部区域。
2.根据权利要求1所述的半导体器件，其中，所述第一金属焊盘的所述内部区域具有5μm至10μm的范围内的厚度，其中，所述第一金属焊盘的所述***区域具有约20μm或更大的厚度。
3.根据权利要求2所述的半导体器件，其中，所述半导体衬底具有60μm或更小的厚度。
4.根据权利要求1所述的半导体器件，其中，所述第一金属焊盘的所述***区域比所述管芯附接材料厚。
5.根据权利要求1所述的半导体器件，其中，所述管芯附接材料比所述第一金属焊盘的所述***区域厚，使得所述第一互连板或所述半导体管芯的底表面设置在所述第一金属焊盘的所述***区域的顶表面上方。
6.根据权利要求1所述的半导体器件，其中，所述第一互连板的底表面具有一个或多个结构，所述一个或多个结构从所述第一金属焊盘的所述***区域向内横向设置并且朝向所述第一金属焊盘的所述内部区域垂直延伸。
7.根据权利要求1所述的半导体器件，其中，所述第一金属焊盘的所述***区域被划分为多个段，并且其中，所述段中的相邻段通过间隙横向分开。
8.根据权利要求1所述的半导体器件，其中，所述功率晶体管包括多个输出沟道，每个输出沟道被配置为向负载输送电流，其中，所述功率晶体管包括用于每个输出沟道的个体有源区，并且其中，所述第一金属焊盘基本上覆盖所述功率晶体管的所述有源区中的第一个。
9.根据权利要求8所述的半导体器件，还包括：
形成在所述半导体衬底上方的多个附加金属焊盘，每个附加金属焊盘基本上覆盖所述功率晶体管的所述有源区中的对应一个，每个附加金属焊盘电连接到基本上被所述金属焊盘覆盖的所述有源区中的源极或发射极区域，每个金属焊盘包括由***区域横向包围的内部区域，所述***区域比所述内部区域厚；以及
多个附加互连板，每个附加互连板通过管芯附接材料附接到所述附加金属焊盘中的对应一个的所述内部区域。
10.根据权利要求1所述的半导体器件，还包括集成在所述半导体衬底的与所述功率晶体管不同的区域中的一个或多个逻辑器件。
11.根据权利要求1所述的半导体器件，其中，所述第一金属焊盘是Cu焊盘，并且其中，所述第一互连板是Cu夹。
12.一种制造半导体器件的方法，所述方法包括：
在半导体衬底中形成功率晶体管，所述功率晶体管包括有源区，在所述有源区中形成一个或多个功率晶体管单元；
在所述半导体衬底上方形成第一金属焊盘，并且所述第一金属焊盘基本上覆盖所述功率晶体管的全部所述有源区，所述第一金属焊盘电连接至所述功率晶体管的所述有源区中的源极或发射极区域，所述第一金属焊盘包括由***区域横向包围的内部区域，所述***区域比所述内部区域厚；以及
通过管芯附接材料将第一互连板或半导体管芯附接至所述第一金属焊盘的所述内部区域。
13.根据权利要求12所述的方法，其中，形成所述第一金属焊盘包括：
在所述半导体衬底上方沉积第一Cu层，并且所述第一Cu层基本上覆盖所述功率晶体管的所有所述有源区；
在所述第一Cu层的与所述第一金属焊盘的所述内部区域相对应的部分上形成掩模，所述掩模被配置为防止Cu沉积；以及
在所述第一Cu层的未被所述掩模保护的部分上沉积第二Cu层以形成所述第一金属焊盘的所述***区域，所述第一金属焊盘的所述内部区域由所述第一Cu层的在所述第二Cu层的沉积期间被所述掩模保护的所述部分形成。
14.根据权利要求13所述的方法，其中，所述第一Cu层具有在5μm至10μm的范围内的厚度，并且其中，所述第二Cu层具有在10μm至20μm的范围内的厚度。
15.根据权利要求12所述的方法，其中，形成所述第一金属焊盘包括：
在所述半导体衬底上方沉积Cu层，所述Cu层基本上覆盖所述功率晶体管的所有所述有源区；
在所述Cu层的与所述第一金属焊盘的所述***区域相对应的部分上形成掩模，所述掩模被配置为防止Cu蚀刻；以及
蚀刻所述Cu层的未被所述掩模保护的部分以形成所述第一金属焊盘的所述内部区域，所述第一金属焊盘的所述***区域由所述Cu层的在所述Cu层的蚀刻期间被所述掩模保护的所述部分形成。
16.根据权利要求15所述的方法，其中，所沉积的所述Cu层的厚度为约20μm或更大，并且其中，所述Cu层的被蚀刻部分的厚度在5μm至10μm的范围内。
17.根据权利要求12所述的方法，其中，所述第一金属焊盘的所述***区域比所述管芯附接材料厚，并且其中，将所述第一互连板或所述半导体管芯附接到所述第一金属焊盘的所述内部区域包括：
在所述第一金属焊盘的所述内部区域上沉积所述管芯附接材料；以及
在使用所述第一金属焊盘的所述***区域将所述第一互连板与所述第一金属焊盘对准的同时，将所述第一互连板与所述管芯附接材料接触放置。
18.根据权利要求12所述的方法，其中，所述管芯附接材料比所述第一金属焊盘的所述***区域厚，并且其中，将所述第一互连板或所述半导体管芯附接到所述第一金属焊盘的所述内部区域包括：
在所述第一金属焊盘的所述内部区域上沉积所述管芯附接材料；以及
在使用所述管芯附接材料的表面张力将所述第一互连板与所述第一金属焊盘对准的同时，将所述第一互连板与所述管芯附接材料接触放置。
19.根据权利要求12所述的方法，其中，所述第一互连板的底表面具有一个或多个结构，所述一个或多个结构从所述第一金属焊盘的所述***区域向内横向设置，并且其中，将所述第一互连板或所述半导体管芯附接到所述第一金属焊盘的所述内部区域包括：
在所述第一金属焊盘的所述内部区域上沉积所述管芯附接材料；以及
将所述第一互连板与所述管芯附接材料接触放置，以使所述第一互连板的所述底表面处的所述一个或多个特征朝向所述第一金属焊盘的所述内部区域垂直延伸，并且从所述第一金属焊盘的所述***区域向内横向设置，以使所述第一互连板与所述第一金属焊盘对准。
20.根据权利要求12所述的方法，其中，所述功率晶体管包括多个输出沟道，每个输出沟道被配置为将电流输送到负载，其中，所述功率晶体管包括用于每个输出沟道的个体有源区，并且其中，所述第一金属焊盘基本上覆盖所述功率晶体管的所述有源区中的第一个，所述方法还包括：
在所述半导体衬底上方形成多个附加金属焊盘，每个附加金属焊盘基本上覆盖所述功率晶体管的所述有源区中的对应一个，每个附加金属焊盘电连接到基本上被所述金属焊盘覆盖的所述有源区中的源极或发射极区域，每个金属焊盘包括由***区域横向包围的内部区域，所述***区域比所述内部区域厚；以及
通过管芯附接材料将多个附加互连板中的每个附接到所述附加金属焊盘中的对应一个的所述内部区域。
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