EP2015624B1 - Mehrschichtdruckleiterplatte - Google Patents

Mehrschichtdruckleiterplatte Download PDF

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Publication number
EP2015624B1
EP2015624B1 EP08018753A EP08018753A EP2015624B1 EP 2015624 B1 EP2015624 B1 EP 2015624B1 EP 08018753 A EP08018753 A EP 08018753A EP 08018753 A EP08018753 A EP 08018753A EP 2015624 B1 EP2015624 B1 EP 2015624B1
Authority
EP
European Patent Office
Prior art keywords
layer
substrate
hole
resin
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP08018753A
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English (en)
French (fr)
Other versions
EP2015624A3 (de
EP2015624A2 (de
Inventor
Motoo Asai
Kenichi Shimada
Kouta Noda
Takashi Ibiden Co. Ltd. Kariya
Hiroshi Ibiden Co. Ltd. Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
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Filing date
Publication date
Priority claimed from JP34018297A external-priority patent/JP3564981B2/ja
Priority claimed from JP6706598A external-priority patent/JP3408417B2/ja
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of EP2015624A2 publication Critical patent/EP2015624A2/de
Publication of EP2015624A3 publication Critical patent/EP2015624A3/de
Application granted granted Critical
Publication of EP2015624B1 publication Critical patent/EP2015624B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B3/00—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0212—Resin particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0215—Metallic fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0242—Shape of an individual particle
    • H05K2201/0257—Nanoparticles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/383—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by microetching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/384—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/385—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by conversion of the surface of the metal, e.g. by oxidation, whether or not followed by reaction or removal of the converted layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Definitions

  • This invention relates to a multilayer printed wiring board used as a package board for mounting an IC chip or the like, and more particularly to a multilayer printed wiring board capable of providing a high density wiring easily and of preventing the formation of cracks or the like in through-holes or in the neighborhood thereof when heat cycle occurs, for example.
  • through-holes are formed for electrically connecting the front surface to the back surface of a core substrate (hereinafter simply referred to as "substrate") of a both-sided multilayer printed wiring board.
  • substrate a core substrate
  • through-holes are, however, considered as dead spaces in designing of a circuit, and hence become one of the factors which prevent wiring from densifying.
  • the present invention has been accomplished to solve the aforementioned problems inherent to the conventional techniques, and it is a main object of the invention to provide a multilayer printed wiring board which can easily ensure high density wiring and a production process thereof.
  • a further object of the invention is to provide high density through-hole intervals and wiring in a build-up multilayer printed wiring board without reducing an electric connection reliability between through-holes and viaholes at high temperature and high humidity conditions.
  • a yet further object of the invention is to provide a construction of a resin composition used for filling through-hole of the aforementioned multilayer printed wiring boards.
  • the present invention provides a multilayer printed wiring board as defined in claim 1.
  • the multilayer printed wiring board according to the invention is characterized, as a first aspect, by forming a roughened layer on an internal surface conductor of the through-hole filled with a filler.
  • a second aspect of the printed wiring board according to the present invention is that a through-hole-covering conductor layer is formed for covering an exposed surface of the filler filling the through-hole.
  • the multilayer printed wiring board according to the invention is characterized, as a third aspect, by forming a viahole just above the through-hole-covering conductor layer which is formed just above the through-hole and by connecting the viahole to the conductor layer.
  • the present invention is characterized, as a fourth feature, by proposing a resin composition for filling through-hole of the aforementioned multilayer printed wiring board.
  • a roughened layer is formed on the internal surface of the through-hole in order to bring the filler into intimate contact with the through-hole via the roughened layer and to avoid the formation of voids. If a void is formed between the filler and the through-hole, a conductor layer formed just thereabove by electroplating becomes bumpy or air in the void expands by heat and causes cracks or delamination, whereas moisture accumulated in the void causes migration or cracks. The formation of a roughened layer can avoid such defects.
  • wiring can be installed just above the through-hole and a viahole can be connected directly thereto, as described below.
  • the through-hole-covering conductor layer plays a role of protecting a resin ingredient in the filler from erosion.
  • the viahole which is directly connected via the through-hole-covering conductor layer formed just above the through-hole according to the third aspect of the invention precludes the formation of a land (internal layer pad) for wiring around the through-hole as in conventional equivalents.
  • the shape of the land of through-hole can remain a perfect circle. Accordingly, intervals between through-holes formed in a substrate can be reduced so as to decrease dead spaces and increase the number of through-holes. In other words, this construction ensures intervals of adjacent through-holes to be as narrow as 700 ⁇ m or less.
  • Such a construction ensures lines of a back build-up wiring layer of the substrate to connect to a front build-up wiring layer through a multitude of through-holes.
  • wiring of the conductor circuit to the periphery of the substrate can be installed in both the front and back build-up layers.
  • a plurality of wiring from plural bumps on the back surface are integrated and connected to bumps on the front surface in a multilayer printed wiring board.
  • through-holes are formed in high density, wiring can be integrated in front and back build-up wiring layers in the same condition so that the numbers of build-up wiring layers can be the same between the front and back surfaces and, in addition, can be reduced.
  • the pitch between through-holes may be set to equal to or less than 700 ⁇ m in order to obtain the aforementioned operations and advantages.
  • the pitch of equal to or less than 700 ⁇ m increases the number of through-holes and ensures connection from the front to the back build-up layers.
  • a roughened layer is formed on the internal surfaces of the through-holes and/or on the surface of the through-hole-covering conductor layer which covers the filler exposed from the through-hole.
  • the latter roughened layer ensures a direct connection of a viahole to the through-hole-covering layer with a high reliability. Consequently, even when used at high temperature and high humidity conditions, high density wiring and through-holes in a build-up multilayer printed wiring board can easily be achieved without reducing electric connection reliability between the through-hole and viahole.
  • the thickness of the roughened layer formed on the internal surface of through-holes or on the surface of the conductor layer should preferably fall in the range from 0.1 to 10 ⁇ m. This is because a thicker roughened layer causes a short circuit between layers, whereas a thinner roughened layer decreases adhesion of the roughened layer with respect to an adherend.
  • These roughened layers may preferably be obtained by subjecting the conductor on the internal surface of through-holes or the surface of the through-hole-covering conductor layer to an oxidation (graphitization)-reduction treatment or a treatment with an aqueous mixture of an organic acid and a copper(II) complex, or a plating treatment with needle-formed alloy of a copper-nickel-phosphorus.
  • the solution acts as follows in the coexistence of oxygen such as in spraying or bubbling and dissolves a metal foil such as copper as a conductor circuit: Cu + Cu(II)A n ⁇ 2Cu(I)A n/2 2Cu(I)A n/2 + (n/4)O 2 + nAH (aeration) ⁇ 2Cu(II)A n + (n/2)H 2 O wherein A is a complexing agent (acting as a chelating agent) and n is a coordination number.
  • the copper(II) complex used in this treatment is preferably a copper(II) complex of an azole.
  • the copper(II) complex of an azole acts as an oxidizing agent for oxidizing a metallic copper or the like.
  • the preferred azole includes diazoles, triazoles and tetrazoles. Among them, imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole and 2-undecylimidazole are preferred.
  • the content of the copper (II) complex of an azole should preferably fall in the range from 1 to 15% by weight. Within this range, satisfactory solubility and stability can be obtained.
  • the organic acid is incorporated for dissolving a copper oxide.
  • At least one organic acid selected from formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, malic acid and sulfamic acid is desirable.
  • the content of the organic acid may preferably fall in the range from 0.1 to 30% by weight. Within this range, solubility and dissolution stability of an oxidized copper can be maintained.
  • the produced copper(I) complex is dissolved by a function of an acid and bonded with oxygen to form a copper(II) complex and thereby to contribute oxidation of copper again.
  • Halogen ions such as fluorine ions, chlorine ions, bromine ions or the like may be added to the etchant comprising the organic acid-copper(II) complex for supplementing dissolution of copper or oxidation of an azole.
  • the halogen ion can be supplied by adding hydrochloric acid, sodium chloride or the like to the solution.
  • the content of the halogen ion may preferably fall in the range from 0.01 to 20% by weight. Within this range, the formed roughened layer has a satisfactory adherence with respect to the interlaminar insulating resin layer.
  • the etchant comprising an organic acid-copper(II) complex may be prepared by dissolving a copper(II) complex of an azole and an organic acid (if necessary with halogen ion) in water.
  • the plating treatment with a needle-formed alloy of copper-nickel-phosphorus may preferably be conducted using a plating bath containing 1 to 40 g/l of copper sulfate, 0.1 to 6.0 g/l of nickel sulfate, 10 to 20 g/l of citric acid, 10 to 100 g/l of a phosphinate, 10 to 40 g/l of boric acid, and 0.01 to 10 g/l of a surfactant.
  • the first filler (A) used in the invention should preferably be composed of metal particles, a thermosetting resin and a curing agent, or of metal particles and a thermoplastic resin, whereas a solvent can be added as necessary.
  • a solvent can be added as necessary.
  • the metal particles there may be mentioned particles of copper, gold, silver, aluminium, nickel, titanium, chromium, tin/lead, palladium, platinum or others.
  • the particle size of the metal particles may preferably fall in the range from 0.1 to 50 ⁇ m. When the particle size is less than 0.1 ⁇ m, surfaces of the metal particles are oxidized so as to reduce wettability of the filler with respect to the resin, whereas when it exceeds 50 ⁇ m, the print quality is deteriorated.
  • the metal particles may preferably be incorporated in a ratio ranging from 30 to 90% by weight with respect to the total weight. When the ratio is less than 30% by weight, the adherence of the conductor layer covering an exposed filler from through-hole is deteriorated, whereas when it exceeds 90% by weight, the print quality is worsened.
  • the resin examples include epoxy resins, phenolic resins, polyimide resins, polytetrafluoroethylene (PTFE) and other fluororesins, bismaleimide-triazine (BT) resins, FEP, PFA, PPS, PEN, PES, nylon, aramid resins, PEEK, PEKK, PET and others.
  • the metal particles can be treated with a complexing agent or a modifier on their surfaces for improving their adherence with respect to the resin.
  • a complexing agent or a modifier on their surfaces for improving their adherence with respect to the resin.
  • any of imidazole-series, phenol-series or amine-series curing agents can be employed, and any of NMP (N-methylpyrrolidone), DMDG (diethylene glycol dimethyl ether), glycerin, water, 1-, 2- or 3-cyclohexanol, cyclohexanone, methyl cellosolve, methyl cellosolve acetate, methanol, ethanol, butanol, propanol, bisphenol A type epoxy and other solvents may be used.
  • the filler preferably has, as an optimum composition, a combination of a mixture of Cu powder and bisphenol F type solvent-free epoxy (manufactured by Yuka Shell Co., Ltd., trade name: E-807) in a weight ratio of 6:4 to 9:1 and a curing agent, or a combination of Cu powder, PPS and NMP in a weight ratio of 8:2:3.
  • such a filler (B) should be distinguished from the aforementioned filler (B), and it is essentially characterized by comprising a particulate substance, a resin and an ultrafine inorganic powder.
  • the aforementioned resin composition for filling through-hole comprises an inorganic ultrafine powder having an average particle size preferably ranging from 1 to 1, 000 nm (more preferably from 2 to 100 nm), and when it is charged in the through-hole, a meshwork formed as a function of an intermolecular force of the ultrafine inorganic powder traps the particulate substance so as to prevent isolation and precipitation of the particulate substance.
  • the particulate substance can be engaged into the through-hole-covering conductor layer above the filler as an anchor, and in addition, crevices for anchoring can be formed by dissolving and removing the particulate substance to contribute to integration of the filler and the through-hole-covering conductor layer effectively.
  • the particulate substance is a metal particle
  • the metal particle is protruded from the surface of the filler so that the protruded metal particle and the through-hole-covering conductor layer covering the same are integrated to enhance the adherence therebetween.
  • delamination between the filler and the through-hole conductor layer can be prevented, and hence delamination between the filler and the conductor layer covering the filler can be prevented even at high temperature and high humidity conditions.
  • the particulate substance at least one member selected from metal particles, inorganic particles and resin particles is preferred.
  • metal particles those used in the filler (A) may be employed.
  • the inorganic particles include particles of silica, alumina, mullite, silicon carbide and the like.
  • a surface-modifier such as a silane coupling agent can be added.
  • resin particles at least one member selected from epoxy resins, benzoguanamine resins and amino resins is advantageously employed. These resins have satisfactory adherence with respect to the constitutive resin of the filler.
  • the particulate substance preferably has an average particle size ranging from 0.1 to 30 ⁇ m. Such an average particle size enhances adherence with respect to the through-hole-covering conductor layer covering the filler.
  • the content of the particle substance may preferably fall in the range from 30 to 90% by weight based upon the total solid contents of the resin composition. Within this range, satisfactory adherence and print quality can be obtained simultaneously.
  • the constitutive resin (which should be distinguished from the aforementioned resin particle) of the resin composition for filling through-hole includes thermosetting resins and thermoplastic resins.
  • thermosetting resin includes at least one member selected from epoxy resins, polyimide resins and phenolic resins.
  • thermoplastic resin use may preferably made of at least one member selected from polytetrafluoroethylene (PTFE), tetrafluoroethylene-hexafluoropropylene copolymers (FEP), tetrafluoroethylene-perfluoroalcoxy copolymers (PFA) and other fluororesins, polyethylene terephthalates (PET), polysulfones (PSF), polyphenylene sulfides (PPS), thermoplastic polyphenylene ethers (PPE), polyether sulfones (PES), polyether imides (PEI), polyphenylene sulfones (PPES), polyethylene naphthalates (PEN), polyether ether ketones (PEEK), and polyolefin resins.
  • PTFE polytetrafluoroethylene
  • FEP tetrafluoroethylene-hexafluoropropylene copolymers
  • PFA tetrafluoroethylene-perfluoroalc
  • At least one member selected from bisphenol type epoxy resins and novolac type epoxy resins can advantageously be used as the resin for filling through-hole.
  • the viscosity of a bisphenol type epoxy resin can be regulated by selecting from A-type resins, F-type resins or others suitably without the use of a diluent solvent.
  • a novolac type epoxy resin has a high strength, excellent heat resistance and chemical resistance and is not disintegrated even in a strongly basic solution such as a plating solution and not degraded by heat.
  • bisphenol type epoxy resin use is preferably made of at least one member selected from bisphenol A type epoxy resins and bisphenol F type epoxy resins.
  • bisphenol F type epoxy resins can advantageously be employed as they can be used at a low viscosity without any solvent.
  • At least one member selected from phenol novolac type epoxy resins and cresol novolac type epoxy resins may preferably be employed as the novolac type epoxy resin.
  • the composition ratio thereof should preferably fall in the range from 1/1 to 1/100 by weight. Within this range, excessive increase of the viscosity can be prevented.
  • the preferred curing agent used in the resin composition includes imidazole-series curing agents, acid anhydride-series curing agents and amine-series curing agents, since these curing agents exhibit a small shrinkage in curing. By preventing such shrinkage in curing, integration between the filler and the conductor layer covering the same can be enhanced and the adherence can be improved.
  • the resin composition may be diluted with a solvent as necessary.
  • a solvent there may be mentioned NMP (N-methylpyrrolidone), DMDG (diethylene glycol dimethyl ether), glycerin, water, 1-, 2- or 3-cyclohexanol, cyclohexanone, methyl cellosolve, methyl cellosolve acetate, methanol, ethanol, butanol, propanol and the like.
  • Preferable ultrafine inorganic particle (which should be distinguished from the aforementioned inorganic particle) constituting the resin composition for filling through-hole includes silica, alumina, silicon carbide and mullite, among which silica is most desirable.
  • the ultrafine inorganic particle should have an average particle size ranging from 1 to 1,000 nm and more preferably from 2 to 100 nm. Within this range, the particle size is fine and thus repletion of through-holes is not deteriorated, and meshwork bonds, which are estimated as hydrogen bonds, can be formed so as to trap the particulate substance.
  • the content of the ultrafine inorganic particle should preferably fall in the range from 0.1 to 5% by weight relative to the total solid contents in the resin composition. This is because precipitation of the metal particle can be prevented without deteriorating repletion within this range.
  • the filler being composed of the resin composition as mentioned above should be a nonconducting filler having a specific resistance of equal to or more than 10 6 ⁇ cm and more preferably equal to or more than 10 8 ⁇ cm.
  • the filler is electroconductive, cuttings of the filler is formed in polishing of the resin composition after curing, and they adhere between the conductor circuit so as to cause a short circuit.
  • the composition should be cured and shrunk. If such a shrinkage by curing is excessive, delamination between the filler and the through-hole-covering conductor layer covering the filler occurs.
  • Re Interlaminar insulating resin layer
  • the interlaminar insulating resin layer according to the invention can be composed of an lower layer comprising a resin having excellent insulation properties and an upper layer comprising a resin having a satisfactory adherence, using any of thermosetting resins, thermoplastic resins or complexes of a thermosetting resin and a thermoplastic resin.
  • thermosetting resin epoxy resins, polyimide resins, phenolic resins, thermosettable polyphenylene ethers (PPE) may be employed.
  • thermoplastic resin examples include polytetrafluoroethylene (PTFE) and other fluororesins, polyethylene terephthalates (PET), polysulfones (PSF), polyphenylene sulfides (PPS), thermoplastic polyphenylene ethers (PPE), polyether sulfones (PES), polyether imides (PEI), polyphenylene sulfones (PPES), tetrafluoroethylene-hexafluoropropylene copolymers (FEP), tetrafluoroethylene-perfluoroalkoxy copolymers (PFA), polyethylene naphthalates (PEN), polyether ether ketones (PEEK) and polyolefin resins.
  • the complex of a thermosetting resin and a thermoplastic resin includes an epoxy resin-PES, an epoxy resin-PSF, an epoxy resin-PPS, an epoxy resin-PPES and the like.
  • a glass cloth-impregnated resin complex can be used as the interlaminar insulating resin layer.
  • the glass cloth-impregnated resin complex includes a glass cloth-impregnated epoxy, a glass cloth-impregnated bismaleimide-triazine, a glass cloth-impregnated PTFE, a glass cloth-impregnated PPE, a glass cloth-impregnated polyimide and the like.
  • An adhesive for electroless plating can also be used as the interlaminar insulating resin layer in the present invention.
  • an adhesive formed by dispersing cured heat-resistant particles soluble in an acid or an oxidizing agent into an uncured heat-resistant resin hardly soluble in an acid or an oxidizing agent through curing treatment is most desirable.
  • the heat-resistant resin particles are dissolved and removed by a treatment with an acid or an oxidizing agent so as to form a roughened layer composed of reverse- ⁇ -formed anchors on its surface.
  • the cured heat-resistant resin particles in the adhesive for electroless plating particularly preferred is at least one member selected from 1 heat-resistant resin particles having an average particle size of equal to or less than 10 ⁇ m, 2 agglomerate particles obtained by aggregating heat-resistant resin powder having an average particle size of equal to or less than 2 ⁇ m, 3 a mixture of heat-resistant resin powder having an average particle size ranging from 2 to 10 ⁇ m and heat-resistant resin powder having an average particle size of equal to or less than 2 ⁇ m, 4 quasi-particles obtained by adhering at least one of heat-resistant resin powder or inorganic powder each having an average particle size of equal to or less than 2 ⁇ m to surfaces of heat-resistant resin powder having an average particle size ranging from 2 to 10 ⁇ m, 5 a mixture of heat-resistant resin powder having an average particle size ranging from 0.1 to 0.8 ⁇ m and heat-resistant resin powder having an average particle size more than 0.8 ⁇ m and less than 2 ⁇ m, and 6 heat-resistant resin powder having an average particle
  • thermosetting resins thermoplastic resins and complexes of a thermosetting resin and a thermoplastic resin may be employed.
  • the conductor circuit (inclusive of the through-hole-covering conductor layer) formed on the substrate and the conductor circuit formed on the interlaminar insulating resin layer can be connected to each other through a viahole.
  • the viahole may be filled with a plated film or a filler.
  • a process of producing the multilayer printed wiring board through a semi-additive process will be described below, whereas a full-additive process, a multilamination process and a pin lamination process can also be employed in the production process of the multilayer printed wiring board according to the invention.
  • an oxidation bath containing NaOH (20 g/l) , NaClO 2 (g/l) and Na 3 PO 4 (15.0 g/l) and a reduction bath containing NaOH (2.7 g/l) and NaBH 4 1.0 g/l) are preferably employed.
  • the surface of copper is roughened as a function of oxidizing properties of divalent copper in the solution.
  • a typical example of the solution includes CZ8100 solution manufactured by MEC Co., Ltd.
  • the roughened layer may be covered with a layer of a metal or noble metal having an ionization tendency of more than copper but less than titanium.
  • a metal or noble metal layer covering the roughened layer can prevent the dissolution of the conductor circuit due to a local electrode reaction created in the roughening of the interlaminar insulating resin layer.
  • the thickness of this layer is preferably from 0.01 to 2 ⁇ m.
  • the metal preferred is at least one metal selected from titanium, aluminium, zinc, iron, indium, thallium, cobalt, nickel, tin, lead and bismuth.
  • the noble metal includes, for instance, gold, silver, platinum and palladium.
  • tin is desirable, because it can form a thin layer through electroless substitution plating and can advantageously be followed to the roughened layer.
  • a solution of tin borofluoride-thiourea or tin chloride-thiourea is used. In this case, Sn layer having a thickness ranging from 0.01 to 2 ⁇ m is formed through Cu-Sn substitution reaction.
  • a noble metal sputtering method, vaporization method or the like is employed.
  • the conductors are excellent in adherence with respect to the interlaminar insulating resin layer so that cracks starting from a boundary face between the side face of the conductor circuit and through-hole-covering conductor layer which covers the filler and the insulating resin layer can be prevented.
  • the through-hole-covering conductor layer covering the filler can effectively contribute to improvement of adherence with respect to viaholes which are electrically connected thereto.
  • the roughened layers may be formed according to any of the processes mentioned above, such as a graphitization (oxidation)-reduction treatment, a plating with a needle-formed alloy or an etching process.
  • a resin is applied and charged between the conductor circuits and then cured in order to reduce unevenness due to the conductor layer formed on surface of the substrate.
  • the surface of the resin should preferably be polished and smoothed so that the conductor is exposed.
  • a resin composed of a bisphenol A type epoxy resin, bisphenol F type epoxy resin or other bisphenol type epoxy resin, an imidazole curing agent and inorganic particles is desirable.
  • Such a bisphenol type epoxy resin has a low viscosity and a satisfactory applicability.
  • a bisphenol F type epoxy resin can be applied without solvent, and hence is advantageous as to prevent the formation of cracks or delamination caused by volatilization of a solvent in heating and curing.
  • a roughed layer is formed on surface of each of the conductors after polishing.
  • a plating resist is formed onto the substrate after completion of the steps 1 and 2, and a non-resist-formed portion is subjected to an electroplating so as to form a conductor circuit and a through-hole-covering conductor layer portion.
  • a solder plated film is then formed on these conductors using a solder electroplating solution composed of tin borofluoride, lead borofluoride, hydroborofluoric acid and peptone.
  • the plating resist is then removed, and the electroless plating film and copper foil located beneath the plating resist are removed by etching, and then the solder plating film is dissolved and removed with an aqueous solution of borofluoric acid to form a conductor layer.
  • an aqueous solution of a mixture of sulfuric acid and hydrogen peroxide an aqueous solution of a persulfate such as ammonium persulfate, sodium persulfate and potassium persulfate, an aqueous solution of iron chloride, copper chloride or the like is advantageously used.
  • the viaholes are filled with an electrolytic plated metal to form so-called filled viaholes in order to ensure smoothness of the interlaminar insulating resin layer.
  • Fig. 1 is a cross section view illustrating a multilayer printed wiring board according to an embodiment of the invention, which has a construction composed of a substrate 100, and build-up wiring layers 101A, 101B respectively formed on the front and back surfaces of the substrate 100.
  • Each of the build-up layers 101A, 101B is composed of an interlaminar insulating resin layer 104 provided with a viahole 102 and a conductor circuit 103, and an interlaminar insulating resin layer 204 provided with a viahole 202 and a conductor circuit 203.
  • a solder bump 105 is formed on the front surface for connecting to a bump of an IC chip (not shown), and a solder bump 106 is formed on the back surface for connecting to a bump of a mother board (not shown).
  • a conductor circuit starting from the solder bump 105 connecting to the IC chip is routed in the peripheral direction of the substrate, and connected to the solder bump 106 connecting to the mother board.
  • the front build-up layer 101A and the back build-up layer 101B are connected to each other through through-holes 107 formed on the substrate 100.
  • the through-holes 107 are filled with a filler 108, and a through-hole-covering conductor layer 109 is so formed as to cover an exposed surface of the filler 108 from the through-holes 107.
  • the upper-layer viahole 102 is connected to the conductor layer 109, and, the upper-layer viahole 202 is connected to the conductor circuit 103 connecting to the viahole 102.
  • the solder bumps 105, 106 are formed on the viahole 202, or on the conductor circuit 203 connecting to the viahole 202.
  • the through-hole-covering conductor layer 109 located above the filler 108 in the through-holes 107 is formed round, and the viahole 102 is connected directly to the conductor layer 109.
  • the wiring board does not require addition of an internal layer pad for connecting from the through-holes 107 to the viahole 102 as in conventional equivalents, the land shape of the through-hole 107 can be set to round. As a result, the number of through-holes can be increased by densifying the through-holes 107 formed in the substrate 30.
  • routing for dispersing the conductor circuits to the periphery of the substrate can be conducted on both the front and back build-up layers 101A, 101B.
  • a multilayer printed wiring board a plurality of wiring from plural front bumps are connected to back bumps while being integrated, as described above.
  • wiring can be integrated at the same pace between the front and back build-up wiring layers 101A, 101B.
  • the numbers of the layers of the front and back build-up wiring layers 101A, 101B can be set to the same and can be reduced.
  • a palladium-tin colloid was then applied to substrate, and the substrate was immersed in an electroless plating solution having the following composition to form an electroless plated film of 2 ⁇ m in thickness all over the surface of the substrate.
  • the substrate was subjected to an electrolytic copper plating under the following conditions to form an electrolytic copper plated film having a thickness of 15 ⁇ m (see Fig. 2 (c) ).
  • the multilayer printed wiring board prepared by the above mentioned manner ensures through-holes each provided with a perfectly circular land, and it can provide a land pitch of about 600 ⁇ m and thereby through-holes can be formed in a high density so as to densify through-holes easily.
  • the number of through-holes in the substrate can be increased, an electric connection with respect to conductor circuits in the multilayer core substrate can sufficiently be ensured through the through-holes.
  • a multilayer printed wiring board was manufactured in the same manner as in Example 1, except that when through-holes were filled with a copper paste, a through-hole-covering conductor layer 10 for covering an exposed copper paste from the through-holes was not formed. According to this process, pits might be formed because the surface of the copper paste was frequently removed in the formation of openings on an insulating resin layer by a laser beam irradiation.
  • a multilayer printed wiring board was obtained in a similar manner to Example 1, except that the following composition was employed as the filler.
  • Bisphenol F type epoxy resin manufactured by Yuka Shell Co., Ltd., E-807
  • Imidazole curing agent manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN
  • Copper powder having a particle size of 15 ⁇ m or less manufactured by Fukuda Metal Foil and Powder Co., Ltd., SCR-Cu-15
  • Defoaming agent manufactured by Sannopko, Pernol S4
  • example 1 The procedure of example 1 was repeated to produce a multilayer printed wiring board, except that a bisphenol F type epoxy resin containing no metal particle was used as the filler for filling the through-hole.
  • a multilayer printed wiring board was produced in a similar manner to Example 1, except that through-holes were filled with the epoxy resin and the surfaces of the epoxy resin exposed from the through-holes were roughened with chromic acid and then covered with a conductor layer.
  • a multilayer printed wiring board was obtained in the same manner as in Example 1, except that a roughened layer was not formed on the surface of the internal conductor on the through-holes.
  • a heat cycle test of -55°C x 15 min., ambient temperature x 10 min. and 125°C x 15 min at 1,000 times was conducted with respect to the multilayer printed wiring boards according to the examples and comparative examples.
  • viaholes could be formed just above the through-holes according to the multilayer printed wiring boards of Examples 1 to 4 of the present invention, and thus high density through-holes could easily be obtained.
  • no peeling was observed between the filler and the internal surface conductor of the through-hole, or between the filler and the through-hole-covering conductor, and neither crack nor migration was found in the heat cycle test and PCT.
  • a resin composition (filler) 5 for filling through-hole was prepared by kneading, through three rolls, 3.5 parts by weight of a cresol novolac type epoxy resin (manufactured by Yuka Shell Co., Ltd., Epikote 152), 14.1 parts by weight of a bisphenol F type epoxy resin (manufactured by Yuka Shell Co., Ltd., Epikote 807), 1.0 part by weight of ultrafine silica particles (Aerosil R202) having an average particle size of 14 nm, 1.2 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) and 100 parts by weight of copper powder having an average particle size of 15 ⁇ m, and adjusting the viscosity of the mixture to the range from 200 to 300 Pa ⁇ s at 22 ⁇ 1°C.
  • a cresol novolac type epoxy resin manufactured by Yuka Shell Co., Ltd., Epikote 152
  • An adhesive A for upper-layer electroless plating was prepared by mixing the above mixtures 1 to 3.
  • An adhesive B for lower-layer electroless plating was prepared by admixing the above mixtures 1 to 3.
  • solder tin-silver, tin-indium, tin-zinc, tin-bismuth or other solders can be employed as the solder.
  • a multilayer printed wiring board was produced in a similar manner to Example 1, except that the following composition was used as the resin composition for filling through-hole.
  • a resin composition for filling through-hole was prepared by kneading through three rolls 3.5 parts by weight of a cresol novolac type epoxy resin (manufactured by Yuka Shell Co., Ltd., Epikote 152), 14.1 parts by weight of a bisphenol F type epoxy resin (manufactured by Yuka Shell Co., Ltd., Epikote 807) , 1.2 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei co., Ltd., 2E4MZ-CN) and 100 parts by weight of copper powder having an average particle size of ⁇ m, and adjusting a viscosity to the range from 200 to 300 Pa ⁇ s at 22 ⁇ 1°C.
  • a cresol novolac type epoxy resin manufactured by Yuka Shell Co., Ltd., Epikote 152
  • 14.1 parts by weight of a bisphenol F type epoxy resin manufactured by Yuka Shell Co., Ltd., Epikote 807
  • an imidazole curing agent manufactured
  • Example 1 The procedure of Example 1 was repeated to give a multilayer printed wiring board, except that the following resin composition was employed as the resin composition for filling through-hole.
  • a resin composition for filling through-hole was prepared by mixing 17.6 parts by weight of a bisphenol F type epoxy resin (manufactured by Yuka Shell Co., Ltd., Epikote 807), 1.0 part by weight of ultrafine silica particles (Aerosil R202) having an average particle size of 14 nm, 1.2 parts by weight of an imidazole curing agent (Shikoku Kasei Co., Ltd., 2E4MZ-CN) and 100 parts by weight of copper powder having an average particle size of 15 ⁇ m.
  • a bisphenol F type epoxy resin manufactured by Yuka Shell Co., Ltd., Epikote 807
  • ultrafine silica particles Aerosil R202 having an average particle size of 14 nm
  • an imidazole curing agent Shikoku Kasei Co., Ltd., 2E4MZ-CN
  • a multilayer printed wiring board was prepared in the same manner as in Example 1, except that the following resin composition was used as the resin composition for filling through-hole.
  • a resin composition for filling through-hole was prepared by kneading, through three rolls, 3.5 parts by weight of a cresol novolac type epoxy resin (manufactured by Yuka Shell Co., Ltd., Epikote 152), 1.0 part by weight of ultrafine silica particles (Aerosil R202) having an average particle size of 14 nm, 14.1 parts by weight of a bisphenol F type epoxy resin (manufactured by Yuka Shell Co., Ltd., Epikote 807), 1.2 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) and 100 parts by weight of silica particles having an average particle size of 10 ⁇ m, and adjusting a viscosity to the range from 200 to 300 Pa ⁇ s at 22 ⁇ 1°C.
  • a cresol novolac type epoxy resin manufactured by Yuka Shell Co., Ltd., Epikote 152
  • ultrafine silica particles
  • a multilayer printed wiring board was produced in a similar manner to Example 1, except that the following resin composition for filling through-hole was used and that after polishing the surface of the filler, the epoxy resin exposed from the surface was removed by chromic acid.
  • a resin composition for filling through-hole was prepared by kneading through three rolls 3.5 parts by weight of a cresol novolac type epoxy resin (manufactured by Yuka Shell Co., Ltd., Epikote 152), 14.1 parts by weight of a bisphenol F type epoxy resin (manufactured by Yuka Shell Co., Ltd., Epikote 807), 1.0 part by weight of ultrafine silica particles (Aerosil R202) having an average particle size of 14 nm, 1.2 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) and 100 parts by weight of epoxy resin particles (manufactured by Sanyo Kasei Co., Ltd., Polymerpole) having an average particle size of 1 ⁇ m, and adjusting the viscosity of the mixture to the range from 200 to 300 Pa ⁇ s at 22 ⁇ 1°C.
  • a cresol novolac type epoxy resin manufactured by
  • Example 1 The procedure of Example 1 was repeated to give a multilayer printed wiring board, except that the following resin composition was employed as the resin composition for filling through-hole.
  • a cresol novolac type epoxy resin manufactured by Yuka Shell Co., Ltd., Epikote 152
  • 14.1 parts by weight of a bisphenol F type epoxy resin manufactured by Yuka Shell Co., Ltd., Epikote 807
  • an imidazole curing agent manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN
  • the copper powder precipitated so as to cause the filler to peel from the conductor layer covering the filler, and thereby to invite a break between the through-hole and viahole.
  • the printed wiring board according to the invention is useful for a multilayer wiring board which is used as a packaging substrate for packing IC chips, in particular for a multilayer printed wiring board obtained by a semi-additive process or a full-additive process.
  • the resin composition is applicable as through-holes, as well as an interlaminar insulating resin layer of a printed wiring board.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Claims (10)

  1. Mehrschichtige Leiterplatte, die ein Substrat (1), das mit Durchgangslöchern (3) versehen ist, und eine erste Leiterschaltung (9) umfasst, die aus einer Plattierungsschicht und/oder einer Metallfolie ausgebildet und auf dem Substrat ausgebildet ist, wobei die Durchgangslöcher (3) mit einem Füllstoff (5) gefüllt sind, und
    eine freiliegende Fläche des Füllstoffs (5) in den Durchgangslöchern mit einer Durchgangslochabdeckungs-Leiterschicht (10) abgedeckt ist, die aus der Plattierung besteht, und ein Kontaktloch (17), das unmittelbar über der Durchgangslochabdeckungs-Leiterschicht (10) ausgebildet ist, mit der Durchgangslochabdeckungs-Leiterschicht (10) verbunden ist, und
    eine zweite Leiterschaltung (9, 17, 103) mit dem Kontaktloch verbunden ist,
    dadurch gekennzeichnet, dass
    eine Oberfläche der Durchgangslochabdeckungs-Leiterschicht aufgeraut ist.
  2. Mehrschichtige Leiterplatte nach Anspruch 1, wobei die zweite Leiterschaltung auf einer Zwischenschicht-Isolier-Harzschicht (12) ausgebildet ist, die die erste Leiterschaltung (9) und die Durchgangslochabdeckungs-Leiterschicht (10) abdeckt.
  3. Mehrschichtige Leiterplatte nach einem der Ansprüche 1 oder 2, wobei das Kontaktloch mit einem plattierten Film plattiert ist.
  4. Mehrschichtige Leiterplatte nach einem der Ansprüche 1 bis 3, wobei eine Innenfläche des Durchgangslochs (3) aufgeraut ist.
  5. Mehrschichtige Leiterplatte nach einem der Ansprüche 1 bis 4, wobei eine Seitenfläche der Durchgangslochabdeckungs-Leiterschicht aufgeraut ist.
  6. Mehrschichtige Leiterplatte nach einem der Ansprüche 1 bis 5, wobei die Durchgangslochabdeckungs-Leiterschicht einen stromlos plattierten Film und einen elektroplattierten Film auf dem stromlos plattierten Film umfasst.
  7. Mehrschichtige Leiterplatte nach einem der Ansprüche 1 bis 6, wobei der Füllstoff Metallteilchen umfasst.
  8. Mehrschichtige Leiterplatte nach Anspruch 7, wobei der Füllstoff nicht leitend ist.
  9. Mehrschichtige Leiterplatte nach einem der Ansprüche 1 bis 8, wobei die erste Leiterschaltung auf dem Substrat über eine dazwischen befindliche Zwischenschicht-Isolier-Harzschicht (12) ausgebildet ist.
  10. Mehrschichtige Leiterplatte nach einem der Ansprüche 1 bis 9, wobei die Metallfolie eine Kupferfolie ist.
EP08018753A 1997-10-14 1998-10-12 Mehrschichtdruckleiterplatte Expired - Lifetime EP2015624B1 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP28049997 1997-10-14
JP34018297A JP3564981B2 (ja) 1997-10-14 1997-12-10 多層プリント配線板およびその製造方法
JP34018097A JPH11186728A (ja) 1997-10-14 1997-12-10 多層プリント配線板
JP6706598A JP3408417B2 (ja) 1998-03-17 1998-03-17 スルーホール充填用樹脂組成物および多層プリント配線板
EP98947819A EP1030544B1 (de) 1997-10-14 1998-10-12 Mehrschichtige gedruckte leiterplatte, verfahren zu deren herstellung, und harzzusammensetzung zum füllen von kontaktlöchern

Related Parent Applications (2)

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EP98947819.3 Division 1998-10-12
EP98947819A Division EP1030544B1 (de) 1997-10-14 1998-10-12 Mehrschichtige gedruckte leiterplatte, verfahren zu deren herstellung, und harzzusammensetzung zum füllen von kontaktlöchern

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EP2015624A2 EP2015624A2 (de) 2009-01-14
EP2015624A3 EP2015624A3 (de) 2010-03-03
EP2015624B1 true EP2015624B1 (de) 2011-10-12

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EP08018753A Expired - Lifetime EP2015624B1 (de) 1997-10-14 1998-10-12 Mehrschichtdruckleiterplatte
EP02026472A Expired - Lifetime EP1286578B1 (de) 1997-10-14 1998-10-12 Mehrschichtige gedruckte Leiterplatte
EP98947819A Expired - Lifetime EP1030544B1 (de) 1997-10-14 1998-10-12 Mehrschichtige gedruckte leiterplatte, verfahren zu deren herstellung, und harzzusammensetzung zum füllen von kontaktlöchern

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EP98947819A Expired - Lifetime EP1030544B1 (de) 1997-10-14 1998-10-12 Mehrschichtige gedruckte leiterplatte, verfahren zu deren herstellung, und harzzusammensetzung zum füllen von kontaktlöchern

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US (3) US6376049B1 (de)
EP (3) EP2015624B1 (de)
CN (3) CN100418390C (de)
DE (2) DE69842069D1 (de)
TW (3) TW443084B (de)
WO (1) WO1999020090A1 (de)

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EP2015624A3 (de) 2010-03-03
CN100418390C (zh) 2008-09-10
EP1030544B1 (de) 2009-12-30
TW520629B (en) 2003-02-11
CN1181717C (zh) 2004-12-22
TWI249979B (en) 2006-02-21
CN1592554A (zh) 2005-03-09
EP1030544A1 (de) 2000-08-23
CN1237852C (zh) 2006-01-18
CN1272298A (zh) 2000-11-01
TW443084B (en) 2001-06-23
EP2015624A2 (de) 2009-01-14
EP1286578B1 (de) 2010-12-22
EP1030544A4 (de) 2006-03-08
WO1999020090A1 (fr) 1999-04-22
CN1474642A (zh) 2004-02-11
EP1286578A2 (de) 2003-02-26
USRE40947E1 (en) 2009-10-27
DE69842069D1 (de) 2011-02-03
DE69841424D1 (de) 2010-02-11
US6376049B1 (en) 2002-04-23
EP1286578A3 (de) 2006-03-22
US6376052B1 (en) 2002-04-23

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