CN1173739A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN1173739A
CN1173739A CN97113871A CN97113871A CN1173739A CN 1173739 A CN1173739 A CN 1173739A CN 97113871 A CN97113871 A CN 97113871A CN 97113871 A CN97113871 A CN 97113871A CN 1173739 A CN1173739 A CN 1173739A
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金载甲
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MagnaChip Semiconductor Ltd
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    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
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Abstract

本发明公开一种具有低阈值电压、能够防止由于活性区域杂质缺乏而导致泄漏电流的MOS半导体装置及其制造方法。所述半导体装置包括:所定的导电型的半导体衬底;在衬底上形成的场绝缘膜;通过场绝缘膜在上述衬底内设定的活性区域;包围场绝缘膜的在衬底内形成的与衬底为同一导电型的杂质区域;在衬底上形成的门绝缘膜;在门绝缘膜及场绝缘膜上形成的门极图形。

Description

半导体装置及 其制造方法
本发明涉及半导体装置，尤其是具有低阈值电压(threshold voltage)的MOS晶体管及其制造方法。
为了与半导体装置的高集成化及性能复杂化相适应，对集成电路有了特殊的性能要求。例如，使用具有相对低的阈值电压的MOS晶体管，使源极及漏极间的电压降最小化，MOS晶体管的电气特性提高，半导体装置的功能也得到提高。
一般地，为实现具有低阈值电压的NMOS晶体管，形成NMOS晶体管后，在衬底计数掺杂(count doping)调节阈值电压用的P型杂质离子，以降低阈值电压。然而，由于衬底掺杂的P型杂质的增加，电子的迁移率(mobility)降低。另外，为了实现具有低阈值电压的NMOS晶体管，在P沟未形成时向原始P型半导体衬底注入调节阈值电压用的P型杂质离子，以降低阈值电压。即，与P沟相比原始P型衬底相对P型杂质的浓度低，故在原始衬底上形成的NMOS晶体管具有相对低的阈值电压。
图1是上述的具有低阈值电压的NMOS晶体管的平面图。
如图1所示，具有低阈值电压的NMOS晶体管活性区域(active region)A设定在原始的P型衬底(图中未示出)。设定包围从活性区域A到所定间隔形成P沟2的活性区域A的周围的活性区域A′。在活性区域A、A’的中央，沿纵向在P沟2的规定区域扩展有门5。
图2是沿图1的II-II′线剖开的剖面图。参照图2说明具有低阈值电压的NMOS晶体管的制造方法。
如图2所示，在原始的P型半导体衬底1上形成场氧化膜2，在除去具有低阈值电压的NMOS晶体管区域的衬底1内，形成P沟3并设定活性区域A、A’。向衬底1内注入调节阈值电压用的P型杂质离子10，在活性区域A上形成门绝缘膜4。其次，在衬底1上以预定的形状形成门5，图中未示出，在门5的两侧活性区域A注入N型杂质离子，形成源极及漏极。
然而，上述NMOS晶体管，注入调节阈值电压用P型杂质离子10后，位于门5下部的场氧化膜3下部的活性区域A′会形成P型杂质的缺乏层20。这种缺乏层20在NMOS晶体管工作时，在源极及漏极间产生泄漏电流(leakage current)，从而降低元件的电气特性。
因此，本发明的目的是提供具有低阈值电压的晶体管，能够防止由于活性区域杂质缺乏而导致泄漏电流的MOS晶体管及其制造方法。
为达到上述目的，本发明的具有低阈值电压的半导体装置包括：所定的导电型的半导体衬底；在衬底上形成的场绝缘膜；由场绝缘膜在上述衬底内设定的活性区域；包围场绝缘膜的在衬底内形成的与衬底为同一导电型的杂质区域；在衬底上形成的门绝缘膜；在门绝缘膜及场绝缘膜上形成的门极图形。
另外，为达到上述目的，本发明的具有低阈值电压的半导体装置的制造方法包括：在所定的导电型半导体衬底上形成场绝缘膜设定活性区域工序；在衬底上包围上述绝缘膜下部的与衬底形成同一导电型的杂质区域工序；向衬底注入调节阈值电压的离子的工序；在衬底上形成门绝缘膜工序；在门绝缘膜及场绝缘膜上形成门极图形的工序。
本发明使门下部的场绝缘膜下部的活性区域向杂质区域扩展。因此，能够防止与P型杂质区域比杂质浓度相对较低的衬底活性区域产生杂质缺乏。
图1是以往的具有低阈值电压的NMOS晶体管的平面图。
图2是以往的具有低阈值电压的NMOS晶体管的剖面图。
图3是本发明的具有低阈值电压的NMOS晶体管的平面图。
图4A至图4C是用于说明本发明一实施例的具有低阈值电压的NMOS晶体管制造方法的剖面图。
图5A及图5B是用于说明本发明其它实施例的具有低阈值电压的NMOS晶体管制造方法的剖面图。
下面参照附图说明本发明的实施例。
图3是本发明的具有低阈值电压的NMOS晶体管的平面图。
如图3所示，在原始的P型衬底(图中未示出)设有具有低阈值电压的NMOS晶体管的活性区域AA。这时，活性区域AA在其中央部分的两侧所定部分，设有纵向扩展的突出部位AA′。与活性区域AA突出部位AA′的所定部分重叠，从活性区域AA以所定间隔在上述衬底形成有P沟33。活性区域AA的上述中央上部形成有扩展到突出部位AA′及P沟33的所定部分的纵向门35。即在门35的下部活性区域AA向所定部分P沟33扩展。
图4A至图4C是沿图3的IV-IV′线剖开的剖面图，参照图4A至图4C说明本发明一实施例的NMOS晶体管制造方法。
如图4A所示，在原始的P型半导体衬底31上设定了形成场氧化膜32的具有低阈值电压的NMOS晶体管活性区域AA。这时，场氧化膜32比以往的所定距离更远地形成，活性区域AA如图所示，设定得比以往的活性区域A、A，所定区域向外扩展。其次，在活动区域AA、AA’上形成有屏蔽绝缘膜90。
如图4B所示，在围绕场氧化膜32扩展的活性区域，即包含图3的突出部位AA′的衬底形成有P沟33。其后，在活性区域AA、AA’注入调节阈值电压用的P型杂质离子100，较理想的是注入约10～50KeV能量和5×1011～5×1012ions/cm2浓度的B离子，或是注入30～80KeV能量和5×1011～5×1012ions/cm2浓度的BF2离子。这样调节的阈值电压约达到0.2～0.4V的程度。
如图4C所示，除去屏蔽绝缘膜90，在活动区域AA、AA’上形成门绝缘膜34。其次，在衬底上部形成门35。
上述实施例中，具有低阈值电压的NMOS晶体管门35下部的场氧化膜32下部的活性区域AA，扩展到P沟33。这样，在与P沟33相对的P型杂质浓度低的原始P型衬底1的活性区域AA，能防止P型杂质的缺乏。
图5A及图5B是本发明另外的实施例NMOS晶体管的剖面图。剖面方向表示沿图3的IV-IV′线剖开的方向。另一方面，在此说明在衬底形成P沟状态，具有相对低的阈值电压的NMOS晶体管的制造方法。
如图5A所示，在原始的P型半导体衬底5 1的NMOS晶体管预定区域，注入P型杂质离子，最好是约50～150KeV能量和5×1012～5×1013ions/cm2浓度的B离子之后，通过扩散工序形成P沟52。这样，NMOS晶体管的阈值电压达到0.2～0.4V的程度。其次，在P沟52上设定了形成场氧化膜53的活性区域AA。这时，场氧化膜52比以往的所定距离更远地形成，活性区域AA如图所示，设定得比以往的活性区域A、A’只向图3的突出部位AA′扩展。其次，在活动区域AA、AA’上形成有屏蔽绝缘膜54。
如图5B所示，在围绕场氧化膜53形成有包含活性区域AA和突出部位AA′的P型杂质区域55a、55b。这时，在P型杂质区域55a、55b注入约60～150KeV能量和1×1012～1×1013ions/cm2浓度的B离子。这时，P型杂质区域55a、55b不会在活性区域AA的源极及漏极预定区域(参照图3)形成。即，活性区域AA的突出部位AA′由P型杂质区域55a、55b组成。而且，去除屏蔽绝缘膜54，在活性区域AA、AA’上便形成有门绝缘膜56。然后，在衬底上形成门57。
上述实施例中，在形成P沟状态，具有相对低的阈值电压的NOMS晶体管的门57下部的场氧化膜53下部的活性区域AA，扩展到P型区域。这样，通过P型杂质区域，在P型杂质浓度相对低的P沟活性区域AA，能防止P型杂质的缺乏。
如上所述，本发明能够防止具有低阈值电压的晶体管门下部的活性区域发生杂质的缺乏。这样，在晶体管工作时能够防止在源极及漏极间产生泄漏电流，从而提高具有低阈值电压的晶体管的特性。

Claims (8)

1.一种半导体装置，具有低阈值电压，其特征在于，包括：所定的导电型的半导体衬底；在上述衬底上形成的场绝缘膜；通过上述场绝缘膜在上述衬底内设定的活性区域；包围上述场绝缘膜的在上述衬底内形成的与上述衬底为同一导电型的杂质区域；在上述衬底上形成的门绝缘膜；在上述门绝缘膜及场绝缘膜上形成的门极图形。
2.一种半导体装置的制造方法，所述半导体装置具有低阈值电压，其特征在于该制造方法包括：
在所定的导电型半导体衬底上形成场绝缘膜而设定活性区域的工序；在上述衬底内包围上述场绝缘膜下部的与上述衬底形成同一导电型的杂质区域的工序；向上述衬底内注入调节阈值电压的离子的工序；在上述衬底上形成门绝缘膜的工序；在上述门绝缘膜及场绝缘膜上形成门极图形的工序。
3.如权利要求2所述的半导体装置的制造方法，其特征在于，上述半导体衬底是没掺杂杂质的原始衬底。
4.如权利要求3所述的半导体装置的制造方法，其特征在于，注入上述调节阈值电压离子工序为：以约10～50KeV的能量和5×1011～5×1012ions/cm2浓度注入B离子。
5.如权利要求3所述的半导体装置的制造方法，其特征在于，注入上述阈值电压调节离子工序为：以约30～80KeV的能量和5×1011～5×1012ions/cm2浓度注入BF2离子。
6.如权利要求2所述的半导体装置的制造方法，其特征在于，上述半导体衬底是形成了沟的衬底。
7.如权利要求6所述的半导体装置的制造方法，其特征在于，上述沟通过注入50～150KeV的能量和5×1012～5×1013ions/cm2浓度注入的B离子形成。
8.如权利要求6所述的半导体装置的制造方法，其特征在于，上述杂质区域通过注入60～150KeV的能量和1×1012～1×1013ions/cm2的B离子形成。
CNB971138710A 1996-06-29 1997-06-28 半导体装置及其制造方法 Expired - Fee Related CN1136613C (zh)

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JPH1070272A (ja) 1998-03-10
GB9713545D0 (en) 1997-09-03
GB2314973A (en) 1998-01-14
DE19727491A1 (de) 1998-01-02
KR980006490A (ko) 1998-03-30
TW416113B (en) 2000-12-21
KR100233558B1 (ko) 1999-12-01

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