KR980006490A - 반도체 소자 및 그의 제조방법 - Google Patents
반도체 소자 및 그의 제조방법 Download PDFInfo
- Publication number
- KR980006490A KR980006490A KR1019960026296A KR19960026296A KR980006490A KR 980006490 A KR980006490 A KR 980006490A KR 1019960026296 A KR1019960026296 A KR 1019960026296A KR 19960026296 A KR19960026296 A KR 19960026296A KR 980006490 A KR980006490 A KR 980006490A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- region
- semiconductor substrate
- predetermined
- gate electrode
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 239000004065 semiconductor Substances 0.000 title claims abstract 16
- 239000012535 impurity Substances 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims 8
- 150000002500 ions Chemical class 0.000 claims 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 3
- 238000000034 method Methods 0.000 claims 3
- 238000005468 ion implantation Methods 0.000 claims 2
- 230000000903 blocking effect Effects 0.000 claims 1
- 229910052796 boron Inorganic materials 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 230000002265 prevention Effects 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 반도체 소자 및 그 제조방법을 개시한다. 개시한 본 발명은,필드 절연막 주변에 P형의 불순물 결핍층의 형성을 발생코자, 필드 절연막중 액티브 영역의 케이트 예정 영역의 주변에 웰 영역 및 누설 방지층을 P형의 불순물로 형성하므로써, P형의 불순물 결핍층이 형성되지 않는다.
이로써, 이후의 반도체 소자의 소오스 드레인 영역의 형성시, 누설 전류가 최소화 된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4a도 및 제4b도는 본 발명의 제1 실시예에 따른 N모스 트랜지스터의 제조방법을 설명하기 위한 도면.
Claims (9)
- P형의 반도체 기판; 상기 반도체 기판에 필드 절연막을 형성함에 의하여 구축되며, 반도체 소자가 형성되는 액티브 영역; 상기 필드 절연막 하부및 반도체 기판의 예정 영역에 형성되는 P웰 영역; 반도체 기판의 소정 부분을 지나며, 문턱 전압 이상의 전압이 인가되면, 턴온되는 게이트 전극; 상기 액티브 영역 중 게이트 전극 하부의 액티브 영역은 P웰 영역쪽으로 일정 폭만큼 확장되도록 형성되는 것을 특징으로 하는 반도체 소자.
- 반도체 기판의 소정 부분에 소자와 소자를 분리키 위한 필드 절연막을 형성하여, 액티브 영역을 형성하는 단계; 상기 반도체 기판의 소정 영역에 P웰을 형성하는 단계; 결과물 상부의 소정 영역에 게이트 전극을 형성하는 단계를 포함하며, 상기 엑티브 영역 형성단계에서, 게이트 전극 예정 영역에 해당하는 액티브 영역은 P웰 영역 예정 영역으로 일부분 확장되도록 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제2항에 있어서, 상기 P웰 형성 단계와 게이트 전극 형성 단계사이에, 문턱전압 조절 이온을 주입하는 단계를 부가적으로 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제3항에 있어서, 상기 문턱 전압 조절 이온은 보론(boron)을 5 ×1011~5 ×1012ion/㎤의 농도와 약 10 내지 50KeV에 의하여 이온 주입하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제3항에 있어서, 상기 문턱 전압 조절 이온은 BF3를 5 ×1011~5 ×1012ion/㎤의 농도와 약 30 내지 80KeV에 의하여 이온 주입하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 반도체 기판의 소정 부분에 P웰을 형성하는 단계; 반도체 기판의 소자 분리 예정 영역에 필드 절연막을 형성하는 단계; 상기 필드 절연막을 감싸도록 P웰 영역내의 소정 부분에 누설 전류 방지층을 형성하는 단계; 상기 구조물 상부에 게이트 전극을 형성하는 단계를 포함하며, 상기 누설 전류 방지층은 게이트 전극이 형성되는 영역에 형성된 필드 절연막의 하부를 감싸도록 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제6항에 있어서, 상기 누설 방지층은 P형의 불순물을 이온 주입하여 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제6항에 있어서, 상기 누설 방지층은 보론 원자를 약 60 내지 150KeV의 에너지 범위와 1 ×1012~1 ×1013ion/㎤의 농도로 이온 주입하여 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제6항에 있어서, 상기 P웰은 보론 원자를 약 50 내지 150KeV의 에너지 범위와 5 ×1012~5 ×1013ion/㎤의 농도로 이온 주입 및 확산하여 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960026296A KR100233558B1 (ko) | 1996-06-29 | 1996-06-29 | 반도체 소자의 제조방법 |
TW086108423A TW416113B (en) | 1996-06-29 | 1997-06-17 | Semiconductor device and its fanufacturing method |
JP9183142A JPH1070272A (ja) | 1996-06-29 | 1997-06-24 | 半導体装置及びその製造方法 |
GB9713545A GB2314973B (en) | 1996-06-29 | 1997-06-26 | Semiconductor device and its manufacturing method |
DE19727491A DE19727491A1 (de) | 1996-06-29 | 1997-06-27 | Halbleitervorrichtung und Verfahren zu deren Herstellung |
CNB971138710A CN1136613C (zh) | 1996-06-29 | 1997-06-28 | 半导体装置及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960026296A KR100233558B1 (ko) | 1996-06-29 | 1996-06-29 | 반도체 소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR980006490A true KR980006490A (ko) | 1998-03-30 |
KR100233558B1 KR100233558B1 (ko) | 1999-12-01 |
Family
ID=19465048
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960026296A KR100233558B1 (ko) | 1996-06-29 | 1996-06-29 | 반도체 소자의 제조방법 |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPH1070272A (ko) |
KR (1) | KR100233558B1 (ko) |
CN (1) | CN1136613C (ko) |
DE (1) | DE19727491A1 (ko) |
GB (1) | GB2314973B (ko) |
TW (1) | TW416113B (ko) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7304354B2 (en) | 2004-02-17 | 2007-12-04 | Silicon Space Technology Corp. | Buried guard ring and radiation hardened isolation structures and fabrication methods |
JP5036719B2 (ja) | 2005-10-14 | 2012-09-26 | シリコン・スペース・テクノロジー・コーポレイション | 耐放射線性のあるアイソレーション構造及びその製造方法 |
JP4288355B2 (ja) * | 2006-01-31 | 2009-07-01 | 国立大学法人北陸先端科学技術大学院大学 | 三値論理関数回路 |
WO2007108104A1 (ja) * | 2006-03-20 | 2007-09-27 | Fujitsu Limited | 半導体装置及びその製造方法 |
JP2009267027A (ja) * | 2008-04-24 | 2009-11-12 | Seiko Epson Corp | 半導体装置及びその製造方法 |
US10038058B2 (en) | 2016-05-07 | 2018-07-31 | Silicon Space Technology Corporation | FinFET device structure and method for forming same |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2084794B (en) * | 1980-10-03 | 1984-07-25 | Philips Electronic Associated | Methods of manufacturing insulated gate field effect transistors |
JPH0693494B2 (ja) * | 1984-03-16 | 1994-11-16 | 株式会社日立製作所 | 半導体集積回路装置の製造方法 |
JPS61292358A (ja) * | 1985-06-19 | 1986-12-23 | Fujitsu Ltd | Mis型電界効果トランジスタの製造方法 |
JPS62200767A (ja) * | 1986-02-28 | 1987-09-04 | Toshiba Corp | Mos型半導体装置 |
JPS6425438A (en) * | 1987-07-21 | 1989-01-27 | Sony Corp | Manufacture of semiconductor device |
JPH0235778A (ja) * | 1988-07-26 | 1990-02-06 | Seiko Epson Corp | 半導体装置 |
US5525823A (en) * | 1992-05-08 | 1996-06-11 | Sgs-Thomson Microelectronics, Inc. | Manufacture of CMOS devices |
US5396096A (en) * | 1992-10-07 | 1995-03-07 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and manufacturing method thereof |
US5432107A (en) * | 1992-11-04 | 1995-07-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor fabricating method forming channel stopper with diagonally implanted ions |
JPH07135317A (ja) * | 1993-04-22 | 1995-05-23 | Texas Instr Inc <Ti> | 自己整合型シリサイドゲート |
-
1996
- 1996-06-29 KR KR1019960026296A patent/KR100233558B1/ko not_active IP Right Cessation
-
1997
- 1997-06-17 TW TW086108423A patent/TW416113B/zh not_active IP Right Cessation
- 1997-06-24 JP JP9183142A patent/JPH1070272A/ja active Pending
- 1997-06-26 GB GB9713545A patent/GB2314973B/en not_active Expired - Fee Related
- 1997-06-27 DE DE19727491A patent/DE19727491A1/de not_active Ceased
- 1997-06-28 CN CNB971138710A patent/CN1136613C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1136613C (zh) | 2004-01-28 |
CN1173739A (zh) | 1998-02-18 |
GB2314973B (en) | 2001-09-19 |
JPH1070272A (ja) | 1998-03-10 |
GB9713545D0 (en) | 1997-09-03 |
GB2314973A (en) | 1998-01-14 |
DE19727491A1 (de) | 1998-01-02 |
TW416113B (en) | 2000-12-21 |
KR100233558B1 (ko) | 1999-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6525377B1 (en) | Low threshold voltage MOS transistor and method of manufacture | |
US6249029B1 (en) | Device method for enhanced avalanche SOI CMOS | |
US5527724A (en) | Method to prevent latch-up and improve breakdown volatge in SOI mosfets | |
US5998848A (en) | Depleted poly-silicon edged MOSFET structure and method | |
EP0419128B1 (en) | Silicon MOSFET doped with germanium to increase lifetime of operation | |
EP0471131B1 (en) | Process for obtaining an N-channel single polysilicon level EPROM cell | |
US6803285B2 (en) | Method of fabricating dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation | |
KR970013412A (ko) | 반도체소자의 제조방법 | |
KR960015811A (ko) | 표면 채널 피모스소자의 쇼트채널 성능을 향상시키기 위하여 인을 사용하는 활성영역 주입방법 | |
US4839301A (en) | Blanket CMOS channel stop implant employing a combination of n-channel and p-channel punch-through implants | |
US5557129A (en) | Semiconductor MOSFET device having a shallow nitrogen implanted channel region | |
KR100391959B1 (ko) | 반도체 장치 및 제조 방법 | |
KR980006490A (ko) | 반도체 소자 및 그의 제조방법 | |
US6476430B1 (en) | Integrated circuit | |
US6380036B1 (en) | Semiconductor device and method of manufacturing the same | |
KR980006533A (ko) | 반도체 장치 및 그 제조방법 | |
US6589828B2 (en) | Fabricating a thin film transistor having better punch through resistance and hot carrier effects | |
JPH10214970A (ja) | 半導体装置およびその製造方法 | |
KR100219063B1 (ko) | 반도체 소자 제조방법 | |
KR100717504B1 (ko) | 반도체 장치 제조 방법 | |
KR100192169B1 (ko) | P+소오드/드레인 접합 형성방법 | |
KR970024287A (ko) | 실리콘-온- 절연체 모스 전계효과 트랜지스터 및 그의 제조방법(Silicon-On-Insulator MOS transistor and fabricating method thereof) | |
KR980006502A (ko) | 반도체소자의 제조방법 | |
KR980006485A (ko) | 모스 트랜지스터 및 그 제조방법 | |
KR980006392A (ko) | 반도체 메모리소자 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130821 Year of fee payment: 15 |
|
FPAY | Annual fee payment |
Payment date: 20140820 Year of fee payment: 16 |
|
FPAY | Annual fee payment |
Payment date: 20150818 Year of fee payment: 17 |
|
EXPY | Expiration of term |