JPS6425438A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6425438A
JPS6425438A JP18205487A JP18205487A JPS6425438A JP S6425438 A JPS6425438 A JP S6425438A JP 18205487 A JP18205487 A JP 18205487A JP 18205487 A JP18205487 A JP 18205487A JP S6425438 A JPS6425438 A JP S6425438A
Authority
JP
Japan
Prior art keywords
opening
swelled
semiconductor device
conductive layers
drain region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18205487A
Other languages
Japanese (ja)
Inventor
Hisao Hayashi
Taeko Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP18205487A priority Critical patent/JPS6425438A/en
Publication of JPS6425438A publication Critical patent/JPS6425438A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To swell a lower layer base material and to flatten the front surface of a semiconductor device by implanting ions of constituent element of the material into the material itself disposed near the opening of an insulating layer. CONSTITUTION:With a photoresist layer 8 as a mask for an ion implantation an n-type impurity is selectively ion implanted through an opening 9 to a lower layer base material 11, i.e., a source region 6s and a drain region 6d. Then, the material 11 is swelled in the opening 9 to form a swelled part 12, thereby burying the opening 9. Then, the layer 8 is removed, and electrode or wiring conductive layers 10s and 10d are formed on the swelled part 12 equivalent to the extensions from the source region 6s and the drain region 6d of the material filled in the opening 9. The conductive layers 10s and 10d formed in this manner are formed on substantially flat surface.
JP18205487A 1987-07-21 1987-07-21 Manufacture of semiconductor device Pending JPS6425438A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18205487A JPS6425438A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18205487A JPS6425438A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6425438A true JPS6425438A (en) 1989-01-27

Family

ID=16111534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18205487A Pending JPS6425438A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6425438A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100233558B1 (en) * 1996-06-29 1999-12-01 김영환 Manufacturing method of a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100233558B1 (en) * 1996-06-29 1999-12-01 김영환 Manufacturing method of a semiconductor device

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