WO2021104428A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2021104428A1
WO2021104428A1 PCT/CN2020/132144 CN2020132144W WO2021104428A1 WO 2021104428 A1 WO2021104428 A1 WO 2021104428A1 CN 2020132144 W CN2020132144 W CN 2020132144W WO 2021104428 A1 WO2021104428 A1 WO 2021104428A1
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WIPO (PCT)
Prior art keywords
pixel
sub
electrode
color sub
pixels
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PCT/CN2020/132144
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English (en)
French (fr)
Inventor
牟鑫
刁永富
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to RU2021118422A priority Critical patent/RU2765235C1/ru
Priority to EP20824065.5A priority patent/EP4068380A4/en
Priority to MX2021007830A priority patent/MX2021007830A/es
Priority to US17/256,869 priority patent/US11296171B2/en
Priority to JP2020572772A priority patent/JP2023504942A/ja
Priority to BR112021012271A priority patent/BR112021012271A2/pt
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080003063.6A priority patent/CN113196498B/zh
Priority to AU2020390354A priority patent/AU2020390354B2/en
Priority to KR1020207038006A priority patent/KR102498173B1/ko
Publication of WO2021104428A1 publication Critical patent/WO2021104428A1/zh
Priority to US17/576,277 priority patent/US11653530B2/en
Priority to US18/194,921 priority patent/US11974465B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
    • G06F3/038—Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/10—OLED displays
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/30—Devices specially adapted for multicolour light emission
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    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate and a display device.
  • Organic light-emitting diodes have the advantages of self-luminescence, high efficiency, bright colors, light and thin, power-saving, rollable, and wide operating temperature range, and have been gradually applied to large-area displays, lighting, and vehicle-mounted displays.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate includes: a base substrate and a plurality of first-color sub-pixels, a plurality of second-color sub-pixels, and a plurality of third-color sub-pixels arranged on the base substrate; Data line extending in a second direction, the first direction intersecting the second direction; and a power line, the power line in a third direction perpendicular to the base substrate and the data line overlap.
  • At least one of the sub-pixels includes an organic light-emitting element and a pixel circuit that drives the organic light-emitting element.
  • the organic light-emitting element includes a first electrode, a second electrode, and is disposed between the first electrode and the second electrode
  • the pixel circuit includes a driving transistor and a first emission control transistor, the pixel circuit further includes a connection structure provided in the same layer as the data line, and in at least one of the second color sub-pixels, the first The first electrode of the first light-emitting control transistor of the two-color sub-pixel is electrically connected to the connection structure through a first connection hole, and the connection structure is connected to the second electrode of the second-color sub-pixel through a second connection hole Electrically connected, the orthographic projection of at least part of the first connecting hole on the base substrate is located on one side of the orthographic projection of the light-emitting control signal line on the base substrate, and the second connecting hole is At least part of the orthographic projection on the base substrate is located on the other side of the orthographic projection of the light-emitting control signal line on the base substrate; in at least one of the third color sub-pixels, the third color sub-
  • the second electrode of at least one of the third color sub-pixels is connected to the channel of the driving transistor that controls the organic light-emitting elements of other color sub-pixels in the third direction. None of them overlap.
  • the display substrate includes an active semiconductor layer, the active semiconductor layer includes a channel and a source and drain region of each transistor of each sub-pixel, and the connection structure is located in the The first connection hole in the inorganic layer between the connection structure and the active semiconductor layer is electrically connected to the active semiconductor layer; the connection structure is located between the connection structure and the second electrode The second connection hole in at least one of the organic layer and the inorganic layer is electrically connected to the second electrode, and in the second color sub-pixel, the first connection hole is located directly on the base substrate.
  • the center of the projection and the center of the orthographic projection of the second connecting hole on the base substrate are respectively located on both sides of the orthographic projection of the light-emitting control signal line on the base substrate.
  • the orthographic projection of the first connection hole of the second-color sub-pixel on the base substrate is higher than that of the first connection hole of the second color sub-pixel.
  • the orthographic projection of the second connection hole of the second color sub-pixel on the base substrate is away from the orthographic projection of the second electrode of the second color sub-pixel on the base substrate.
  • the second electrode of the second-color sub-pixel is connected with the driving of the second-color sub-pixel in the third direction.
  • the channels of the driving transistors of the organic light-emitting elements of the pixels overlap.
  • the data line connected to the pixel circuit of at least one of the second color sub-pixels and the second electrode of the second color sub-pixel are in the first Spaced from each other in the direction.
  • the second electrode of at least one of the second color sub-pixel and the data line connected to the pixel circuit of the third color sub-pixel are in the third direction. overlap.
  • the second electrode of at least one of the first color sub-pixel and the second electrode of at least one of the third color sub-pixel extend along the second direction.
  • the orthographic projections on the first straight line overlap with the orthographic projections of the connection structure of at least one second color sub-pixel on the first straight line.
  • the orthographic projection of the second electrode of at least one of the third color sub-pixels on a second straight line extending along the first direction is consistent with at least one of the second color
  • the orthographic projections of the connection structure of the sub-pixels on the second straight line overlap.
  • the second electrode of at least one of the sub-pixels includes a main body electrode and a connecting electrode, the connecting electrode is electrically connected to the first light-emitting control transistor, and at least one of the first The orthographic projection of the main electrode of one color sub-pixel on the first straight line overlaps the orthographic projection of the connecting structure of at least one second color sub-pixel on the first straight line.
  • the orthographic projection of the main electrode of at least one of the third color sub-pixels on the second straight line and the connection structure of at least one of the second color sub-pixels overlap.
  • the display substrate further includes: a scan signal line and a reset power signal line.
  • the pixel circuit further includes a data write transistor and a reset transistor, the gate of the data write transistor is configured to be electrically connected to the scan signal line to receive a scan signal, the The gate of the reset transistor is configured to be electrically connected to the reset power signal line to receive a reset control signal.
  • the pixel circuit further includes a second light-emission control transistor, the gate of the first light-emission control transistor and the second light-emission control transistor The gates of are all electrically connected to the light-emitting control signal line to receive the light-emitting control signal.
  • the second electrode of at least one of the second color sub-pixels overlaps the scan signal line in the third direction.
  • the second electrode of at least one of the second color sub-pixels is in the third direction and is electrically connected to the pixel circuit of the second color sub-pixel.
  • the scanning signal lines overlap.
  • the second electrode of at least one of the first color sub-pixel and the second electrode of at least one of the third color sub-pixel are both aligned with each other in the third direction.
  • the light emission control signal lines overlap.
  • the second electrode of at least one of the first color sub-pixels includes a first electrode sub-portion and a second electrode sub-portion located on both sides of the light emission control signal line, The area of the first electrode sub-portion is greater than the area of the second electrode sub-portion; in at least one of the first color sub-pixels, the center of the orthographic projection of the second connection hole on the base substrate and The orthographic projections of the first electrode sub-portions on the base substrate are respectively located on both sides of the orthographic projections of the light-emitting control signal lines on the base substrate.
  • the pixel circuit further includes a storage capacitor, the second electrode of the storage capacitor is multiplexed as the gate of the driving transistor, and at least one The area of the second pole of the storage capacitor of the first color sub-pixel is different from the area of the second pole of the storage capacitor of at least one of the second color sub-pixels.
  • the area of the second electrode of at least one of the first color sub-pixels is greater than the area of the second electrode of at least one of the second color sub-pixels, and at least one The area of the second pole of the storage capacitor of the first color sub-pixel is larger than the area of the second pole of the storage capacitor of at least one of the second color sub-pixels.
  • the first pole of the storage capacitor overlaps the connection structure in the third direction.
  • the channel of the driving transistor of the sub-pixel includes a plurality of channel sub-portions connected in sequence, and at least of the plurality of channel sub-portions The part extends along the first direction, and the orthographic projections of the two channel sub-parts extending along the first direction on the second straight line do not overlap.
  • the plurality of channel sub-portions includes five channel sub-portions connected in sequence, and three of the five channel sub-portions extend along the first direction,
  • the orthographic projections of two of the three channel sub-portions on the second straight line do not overlap, and the orthographic projections on the first straight line overlap, and among the five channel sub-portions
  • the five channel sub-portions include a first channel sub-portion, a second channel sub-portion, a third channel sub-portion, a fourth channel sub-portion, and a fifth channel sub-portion that are sequentially connected.
  • the first channel sub-portion, the third channel sub-portion, and the fifth channel sub-portion extend along the first direction
  • the first channel sub-portion and the third channel sub-portion are parallel to each other
  • the first channel sub-portion and the fifth channel sub-portion are crossed by a third straight line extending along the first direction and the orthographic projections on the second straight line do not overlap
  • the second channel The channel part and the fourth channel part extend along the second direction and are parallel to each other.
  • the display substrate further includes: a pixel defining layer located on a side of the second electrode of each of the sub-pixels away from the base substrate, wherein the pixel defining layer includes In the openings that define the light-emitting area of each sub-pixel, at least a part of the organic light-emitting layer of each sub-pixel is located in the opening, and the orthographic projection of the opening of the pixel defining layer on the base substrate is located in each The main electrode of the second electrode of the sub-pixel is in an orthographic projection on the base substrate; in the pixel defining layer, the area of the opening of the light-emitting region of each of the third color sub-pixels is defined It is larger than the area of the opening defining the light-emitting area of each of the second color sub-pixels, and smaller than the area of the opening defining the light-emitting area of each of the first color sub-pixels.
  • the second electrode of at least one of the first color sub-pixels overlaps the data line in the third direction, and the overlapped portion is along the second direction
  • the length of is greater than 80% of the maximum length of the second electrode along the second direction.
  • the second electrode of at least one of the first color sub-pixels overlaps the power line in the third direction, and the overlapped portion is along the second direction
  • the length of is greater than 80% of the maximum length of the second electrode along the second direction.
  • the orthographic projection of the first connection hole on the base substrate has a first area
  • the second connection hole has a second area
  • the first area and the second area are different.
  • the first connection hole has a first distance from the light emitting control signal line in the second direction, and the The second connection hole has a second distance to the light emitting control signal line in the second direction, and the first distance and the second distance are different.
  • Another embodiment of the present disclosure provides a display device including the above-mentioned display substrate.
  • FIG. 1A is a schematic plan view of an array substrate provided according to an embodiment of the present disclosure
  • FIG. 1B is a schematic partial cross-sectional view of the array substrate shown in FIG. 1A taken along line AA;
  • FIG. 1C is a schematic plan view of an array substrate provided according to an embodiment of the present disclosure.
  • 1D and 1E are schematic plan views of driving transistors of a first color sub-pixel and a second color sub-pixel, respectively;
  • FIG. 2 is a schematic flowchart of a manufacturing method of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a simulation curve diagram of a data signal input to each color sub-pixel and a saturation current flowing through an organic light-emitting element of each color sub-pixel in a second example of an embodiment of the disclosure
  • FIG. 4 is a graph of gate voltage and saturation current of driving transistors with different channel width-to-length ratios in an embodiment of the present disclosure
  • 5A-5C are diagrams showing the relationship between the channel width-to-length ratio and the charging rate of the driving transistor in each color sub-pixel;
  • FIG. 6 is a schematic block diagram of a display substrate provided according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a repeating unit of a display substrate provided according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • 9A-10A are schematic diagrams of various layers of a pixel circuit provided by some embodiments of the present disclosure.
  • 10B and 10C are respectively schematic cross-sectional views taken along the AA' line and BB' line shown in FIG. 10A;
  • FIG. 11A is a schematic diagram of a partial structure of an array substrate provided by an example of an embodiment of the present disclosure.
  • FIG. 11B is a schematic diagram of the arrangement structure of the pixels shown in FIG. 11A.
  • FIG. 12 is a schematic diagram of a partial structure of an array substrate provided by another example of this embodiment.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate includes: a base substrate and a plurality of first-color sub-pixels, a plurality of second-color sub-pixels, and a plurality of third-color sub-pixels arranged on the base substrate; light-emitting control signal lines extending along the first direction
  • the data line extends in the second direction, the first direction intersects the second direction; and the power line, the power line overlaps the data line in the third direction perpendicular to the base substrate.
  • At least one sub-pixel includes an organic light-emitting element and a pixel circuit that drives the organic light-emitting element.
  • the organic light-emitting element includes a first electrode, a second electrode, and a light-emitting layer disposed between the first electrode and the second electrode, and the pixel circuit includes a driving transistor and a pixel circuit.
  • the first light-emitting control transistor and the pixel circuit further include a connection structure arranged on the same layer as the data line.
  • the first electrode of the first light-emitting control transistor of the second color sub-pixel is connected to the second color sub-pixel through the first connection hole.
  • connection structure is electrically connected, the connection structure is electrically connected to the second electrode of the second color sub-pixel through the second connection hole, and the orthographic projection of at least part of the first connection hole on the base substrate is located on the light-emitting control signal line on the base substrate On one side of the orthographic projection of the second connection hole, the orthographic projection of at least part of the second connecting hole on the base substrate is located on the other side of the orthographic projection of the light-emitting control signal line on the base substrate; in at least one third color sub-pixel, The second electrode of the third color sub-pixel does not overlap with the channel of the driving transistor that controls the organic light-emitting element of the third color sub-pixel in the third direction.
  • the present disclosure provides a pixel arrangement structure.
  • the positional relationship between the two connecting holes and the light-emitting control signal line and the positional relationship between the second electrode of the third color sub-pixel and the channel of the driving transistor are set. It is possible to effectively drive the second color sub-pixels to emit light through the connection structure on the basis of increasing the compactness of the pixel arrangement to increase the pixel resolution.
  • the present disclosure by arranging data lines and power lines of different layers, that is, double-layer signal lines, the close arrangement of pixels and the optimized wiring method can be realized.
  • FIG. 1A is a schematic plan view of an array substrate provided according to an embodiment of the present disclosure
  • FIG. 1B is a schematic partial cross-sectional view of the array substrate shown in FIG. 1A taken along line AA.
  • an embodiment of the present disclosure provides an array substrate including a base substrate 100 and a first color sub-pixel 110 and a second color sub-pixel 120 located on the base substrate 100.
  • the first color sub-pixel 110 includes a first driving transistor 111
  • the second color sub-pixel 120 includes a second driving transistor 121
  • the channel width to length ratio W1/L1 of the first driving transistor 111 is larger than that of the second driving transistor 121
  • the aspect ratio is W2/L2.
  • the channel width of the first driving transistor 111 is W1
  • the channel length is L1
  • the channel width of the second driving transistor 121 is W2
  • the channel length is L2, and W1/L1>W2/L2.
  • FIG. 1A schematically shows that the channel lengths of the first driving transistor and the second driving transistor are the same, but the channel widths are different.
  • the embodiments of the present disclosure are not limited to this, and the channel widths of the first driving transistor and the second driving transistor are the same, but the channel lengths are different, or the channel widths and channel lengths of the first driving transistor and the second driving transistor All are different.
  • the brightness of the display device including the array substrate can be improved.
  • the current efficiency of the first color sub-pixel is less than the current efficiency of the second color sub-pixel.
  • the current efficiency here refers to the luminous intensity of each color sub-pixel under a unit current (unit is candela per ampere, cd/A). Due to the differences in the current efficiency of the sub-pixels of different colors, by setting the channel width to length ratios of the driving transistors of the sub-pixels of different colors to be different, it is possible to prevent the white light displayed by the display device including the array substrate from being at the highest gray level. , The phenomenon of insufficient brightness of the first color appears.
  • the first color sub-pixel 110 is a blue sub-pixel
  • the second color sub-pixel 120 is a red sub-pixel or a green sub-pixel.
  • the display device including the array substrate by setting the channel width-to-length ratio of the driving transistor of the blue sub-pixel to be greater than the channel width-to-length ratio of the driving transistor of the red sub-pixel or the green sub-pixel, it is possible to prevent the display device including the array substrate from displaying When the white light is at the highest gray level, there is a phenomenon of insufficient blue light brightness, which causes the white balance color coordinate of the highest gray level white light to deviate from the design value.
  • the white balance mentioned above refers to the white balance, that is, an indicator of the accuracy of the white light formed by mixing the three primary colors of red, green, and blue displayed by the display device.
  • the first color sub-pixel 110 may also be a blue sub-pixel
  • the second color sub-pixel 120 may also be a yellow sub-pixel.
  • FIG. 1C is a schematic plan view of an array substrate provided according to an embodiment of the present disclosure.
  • the array substrate may further include a third color sub-pixel 130, and the third color sub-pixel 130 includes a third driving transistor 131.
  • the first color sub-pixel 110 is a blue sub-pixel
  • the second color sub-pixel 120 is a red sub-pixel
  • the third color sub-pixel 130 is a green sub-pixel.
  • the channel width-to-length ratio of the second driving transistor 121 of the red sub-pixel may be the same as the channel width-to-length ratio of the third driving transistor 131 of the green sub-pixel to facilitate manufacturing.
  • the channel width-to-length ratio of the driving transistors of the red sub-pixel and the green sub-pixel can also be adjusted according to the brightness requirements of each color light when the display device realizes high-brightness display.
  • the ratio of the channel width to length ratio of the driving transistors of the red sub-pixel, the green sub-pixel, and the blue sub-pixel is approximately 1:(0.7 ⁇ 1.3):(1.5 ⁇ 2.5), so that the display device can display When the brightness of white light is 800 nits or even 1000 nits, there will be no insufficient blue light brightness.
  • the ratio of the channel width to length ratios of the driving transistors of the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be 1:1:2 to facilitate the actual manufacturing process.
  • FIG. 1D and FIG. 1E are schematic plan views of driving transistors of the first color sub-pixel and the second color sub-pixel, respectively.
  • the portion where the active layer of the first driving transistor 111 of the first color sub-pixel 110 overlaps with the gate 114 is its channel, and the channel width to length ratio of the first driving transistor 111 is W1 /L1 can be 5/25.
  • the overlapping portion of the second driving transistor 121 and the gate 124 of the second color sub-pixel 120 is a channel, and the channel width to length ratio W2/L2 of the second driving transistor 121 may be 3/30.
  • FIG. 1D and FIG. 1E are schematic plan views of driving transistors of the first color sub-pixel and the second color sub-pixel, respectively.
  • the portion where the active layer of the first driving transistor 111 of the first color sub-pixel 110 overlaps with the gate 114 is its channel, and the channel width to length ratio of the first driving transistor 111 is W1 /L1 can be 5/25.
  • the center points of the overlapping part of the active layer of the first driving transistor 111 and the edge of the gate 114 extending in the X direction are respectively O and O', and the active layer of the first driving transistor 111
  • the center line C1 of the portion overlapping with the gate 114 extends from O to O'.
  • the "long" in the above-mentioned channel aspect ratio refers to the length L1 of the center line C1
  • the "wide” in the channel aspect ratio refers to the overlap between the first driving transistor 111 and the edge of the gate 114 extending in the X direction.
  • the size of the part Similarly, as shown in FIG.
  • the “length” in the channel width-to-length ratio of the second driving transistor 121 refers to the length L2 of its center line C2, and the “wide” in the channel width-to-length ratio refers to the second driving transistor 121
  • the channel of the driving transistor T1 in each sub-pixel includes a plurality of channel sub-portions connected in sequence, and at least part of the plurality of channel sub-portions extends along the first direction.
  • the orthographic projections of the two channel sub-portions extending along the first direction on the second straight line extending along the first direction do not overlap.
  • the plurality of channel sub-portions includes five channel sub-portions T1c-1, T1c-2, T1c-3, T1c-4, and T1c-5 that are sequentially connected, and three channel sub-portions T1c-1 , T1c-3 and T1c-5 extend in the first direction, the orthographic projections of the two channel sub-portions T1c-2 and T1c-4 on the first straight line extending in the second direction overlap, and the three channel sub-portions T1c -1, the orthographic projections of the two channel sub-portions T1c-1 and T1c-5 in T1c-3 and T1c-5 on the second straight line do not overlap, and the orthographic projections on the first straight line overlap.
  • the five channel sub-portions T1c-1, T1c-2, T1c-3, T1c-4, and T1c-5 include a first channel sub-portion T1c-1 and a second channel sub-portion that are sequentially connected T1c-2, the third channel sub-portion T1c-3, the fourth channel sub-portion T1c-4, and the fifth channel sub-portion T1c-5, the first channel sub-portion T1c-1, the third channel sub-portion T1c-3, and the The five-channel sub-portion T1c-5 extends in the first direction, the first channel sub-portion T1c-1 and the third channel sub-portion T1c-3 are parallel to each other, and the first channel sub-portion T1c-1 and the fifth channel sub-portion T1c-5 are parallel to each other.
  • the orthographic projections passed by the third straight line extending in the first direction and on the second straight line do not overlap, and the second channel sub-portion T1c-2 and the fourth channel sub-portion T1c-4 are parallel
  • the channel of the driving transistor T1 when the channel width is relatively large, includes three channel sub-portions connected in sequence, and the three channel sub-portions all extend in the first direction and form a shape similar to " n" shaped channel shape.
  • the channel aspect ratio of the driving transistor of the blue sub-pixel may be 5/25, and the channel aspect ratio of the green sub-pixel and the red sub-pixel may both be 3/30.
  • the embodiment of the present disclosure does not limit the specific channel width to length ratio of the driving transistor of each color sub-pixel, as long as the ratio of the channel width to length ratio of the driving transistor of each color sub-pixel satisfies the above ratio range.
  • each color sub-pixel in the array substrate includes an organic light-emitting element, a light-emitting layer of the organic light-emitting element, a first electrode and a second electrode located on both sides of the organic light-emitting layer, one of the first electrode and the second electrode and a driving transistor Connection, that is, the array substrate in the embodiment of the present disclosure is an array substrate applied to an organic light emitting diode display device.
  • the first color sub-pixel 110 includes a first organic light-emitting layer 112, a first electrode 114 located on the side of the first organic light-emitting layer 112 away from the base substrate 100, and a first organic light-emitting layer 112.
  • the layer 112 faces the second electrode 113 on the side of the base substrate 100, and the second electrode 113 is connected to one of the source and drain of the first driving transistor 111.
  • the second color sub-pixel 120 includes a second organic light emitting layer 122, a first electrode 124 located on the side of the second organic light emitting layer 122 away from the base substrate 100, and a first electrode 124 located on the side of the second organic light emitting layer 122 facing the base substrate 100.
  • the first electrodes of the sub-pixels of different colors shown in FIG. 1B may be common electrodes, and the first electrodes of the sub-pixels of different colors may be made of the same layer and the same material to save process.
  • the second electrode 133 of the organic light emitting element in the third color sub-pixel 130 is connected to one of the source and drain of the third driving transistor 131.
  • the array substrate further includes a pixel defining layer 101 located between adjacent organic light-emitting layers and a flat layer 102 located between the second electrode and the driving transistor.
  • the first electrode of each color sub-pixel may be a cathode.
  • the cathode serves as a connection electrode for the negative voltage of each color sub-pixel, and has better conductivity and lower work function value.
  • the second electrode of each color sub-pixel may be an anode.
  • the anode serves as a connection electrode for the forward voltage of each color sub-pixel, and has good conductivity and a higher work function value. This embodiment includes but is not limited to this.
  • the driving transistors of each color sub-pixel in the embodiments of the present disclosure may be low-temperature polysilicon (LTPS) thin film transistors.
  • LTPS low-temperature polysilicon
  • the saturation current I flowing through the organic light-emitting element satisfies the following relationship:
  • W and L are the channel width and channel length of the drive transistor
  • K1 is related to the channel mobility and unit area channel capacitance of the drive transistor
  • Vgs and Vth are the gate of the drive transistor.
  • the voltage between the source and the threshold voltage, K1 is a coefficient determined by the characteristics of the channel of each driving transistor, such as channel mobility.
  • K2 is a coefficient involving K1, (Vgs-Vth) 2, and S. Therefore, the channel aspect ratio of the first driving transistor of the first color sub-pixel, the channel aspect ratio of the second driving transistor of the second color sub-pixel, and the third driving transistor of the third color sub-pixel all satisfy the above Relationship (4).
  • S is the area of the effective display area included in the array substrate.
  • S is the area of the effective display area of the display screen of the display device.
  • the above Y is taken as the brightness of each color sub-pixel when the white light formed by the mixture satisfies the white balance of each color sub-pixel.
  • the embodiment of the present disclosure may be described as an example in which Y is the maximum brightness of each color sub-pixel for display after passing through the display screen when the white light formed by mixing each color sub-pixel satisfies the highest gray level.
  • Y may be the display brightness of the light emitted by the organic light emitting element after passing through the display screen.
  • the overall transmittance T of the display screen to white light is generally about 0.4, and the overall transmittance of light of different colors will be slightly different.
  • the overall transmittance of the screen to white light, red light, green light, and blue light is set to 0.42 in this embodiment, and this embodiment includes but is not limited to this.
  • the channel width-to-length ratios of the driving transistors in the red sub-pixels, the green sub-pixels, and the blue sub-pixels included in the array substrate satisfy the following proportional relational expression (5):
  • the channel mobility and the channel capacitance per unit area of the driving transistor in each color sub-pixel are both the same value.
  • Vdata is a data signal input to a sub-pixel including a driving transistor
  • Vdd is a power supply voltage input to the driving transistor.
  • the magnitude of the driving current I is directly related to the data signal Vdata (that is, the display data voltage).
  • the output current I of the driving transistor is zero, that is, no current flows through the organic light-emitting element.
  • the sub-pixels including the organic light-emitting element do not emit light, that is, display black;
  • the output current I of the driving transistor is not zero, that is, a current flows through the organic light-emitting element.
  • the sub-pixel including the organic light-emitting element emits light.
  • the greater the difference between the data signal Vdata and the power supply voltage Vdd the greater the output current I, the higher the gray scale displayed by the corresponding sub-pixel, and the greater the brightness of the sub-pixel.
  • the ratio between the channel width and length ratios of the driving transistors of each color sub-pixel can be calculated by the relationship (5) and the relationship (6), and then the ratio can be determined. Adjust the scope to meet the technological process. For example, when the ratio between the channel width and length ratios of the driving transistors of each color sub-pixel is calculated as 1:0.97:2.03 through the above proportional relationship, it can be considered to adjust the above ratio to 1 in order to facilitate the design and the realization of the production process. :1:2.
  • FIG. 2 is a schematic flowchart of a manufacturing method of an array substrate according to an embodiment of the present disclosure. As shown in FIG. 2, the method for fabricating driving transistors of sub-pixels of various colors according to an embodiment of the present disclosure includes the following steps.
  • S101 Obtain optical parameters of a display device including an array substrate, and calculate preset brightness of each color sub-pixel according to the optical parameters.
  • the array substrate may include three-color sub-pixels, namely, blue sub-pixels (first color sub-pixels), red sub-pixels (second color sub-pixels), and green sub-pixels (third color sub-pixels).
  • the tristimulus value of the object color of blue light emitted by the blue sub-pixel is (X [B] , Y [B] , Z [B] )
  • the tristimulus value of the object color of green light emitted by the green sub-pixel is (X [G] , Y [G] , Z [G] )
  • the tristimulus value of the object color of the red light emitted by the red sub-pixel is (X [R] , Y [R] , Z [R] )
  • the tristimulus value of the object color of the mixed white light is (X [W] , Y [W] , Z [W] ).
  • the tristimulus value of the object color here refers to the number of the three primary colors of red, green, and blue needed to match the reflected color light of the object (the three primary colors here are not physical real colors, but imaginary colors), and also refer to the chromaticity value of the object color.
  • Object color refers to the color of the object seen by the eye, that is, the color of light reflected or transmitted by the object.
  • the object color tristimulus values X, Y, and Z of the above-mentioned color sub-pixels respectively satisfy:
  • the ⁇ ( ⁇ ) in the above relationship (7) represents the function of the emission spectrum of the light with wavelength ⁇ and the wavelength, the above as well as They respectively represent the spectral tristimulus value, also known as the CIE1931 standard chromaticity observer spectral tristimulus value.
  • the Y in the above-mentioned tristimulus values of each color light may represent the maximum brightness that the brightness of the color light to be matched can be achieved when the white light formed by the display device is in a white balance state.
  • Y [B] , Y [G] , Y [R] and Y [W] can be the maximum brightness of blue, green, red, and white light when the white light is in the white balance state, and the maximum brightness is also this
  • the preset brightness of each color light in the embodiment is disclosed.
  • the color coordinate center value of each color light is (x, y, z), and the color coordinate center value of each color light and the object color tristimulus value satisfy the following relationship:
  • the proportional relationship of the three parameters in the chromaticity value of the object color can be obtained.
  • the chromaticity value of the object color of white light formed by the mixture of red light, green light and blue light satisfies the following relationship with the chromaticity value of the object color of the three types of light:
  • the proportions of red light, green light and blue light in white light respectively are: Y [R] /Y [W] , Y [G] /Y [W] , Y [B] /Y [W] .
  • the optical parameters may include the target brightness of the white light emitted by the organic light emitting diode display device (the preset brightness, for example, the maximum brightness after passing through the display screen), the target white balance coordinates of the white light (the preset white balance coordinates) ) And the target color coordinate center value (preset color coordinates) of each color sub-pixel, such as the preset color coordinates of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel.
  • the preset brightness for example, the maximum brightness after passing through the display screen
  • the target white balance coordinates of the white light the preset white balance coordinates
  • the target color coordinate center value preset color coordinates
  • calculating the preset brightness of each color sub-pixel according to optical parameters includes: obtaining the chromaticity value of the object color of white light (X [W] , Y [W] , Z [W] ); According to the matrix relationship (12) and the preset color coordinates of each color sub-pixel, the preset brightness of each color sub-pixel can be calculated.
  • the preset brightness of the white light may be set to 800 nits, and the preset white balance coordinates of the white light may be (0.30, 0.32). Since Y in the chromaticity value of the white light object color is 800, according to the relation (8-9), the chromaticity value of the white light object color can be obtained (750,800,950).
  • the center value of the preset color coordinates of the red sub-pixel may be (0.685, 0.315)
  • the center value of the preset color coordinates of the green sub-pixel may be (0.252, 0.718)
  • the center value of the preset color coordinates of the blue sub-pixel The center value can be (0.135,0.05).
  • the embodiments of the present disclosure do not limit this, and can be selected according to specific requirements.
  • the preset brightness of each color sub-pixel can be calculated (that is, the maximum brightness after passing through the display screen), the preset brightness of the red sub-pixel is 184.1 nits, and the preset brightness of the green sub-pixel is 559.1 nits , The default brightness of the blue sub-pixel is 56.8 nits.
  • the preset brightness of white light of 800 nits is the maximum brightness that takes into account the overall transmittance of the display screen of the display device including the array substrate. Therefore, the preset brightness of each color sub-pixel is also considered to be the maximum brightness of the display screen. The maximum brightness of the overall transmittance.
  • the preset brightness of the white light can be set to 800 nits, and the preset white balance coordinates of the white light can be (0.307, 0.321), then the chromaticity value of the object color of the white light It is (765.1,800,927.1).
  • the center value of the preset color coordinates of the red sub-pixel may be (0.697, 0.303), the center value of the preset color coordinates of the green sub-pixel may be (0.290, 0.68), and the center value of the preset color coordinates of the blue sub-pixel
  • the center value can be (0.132, 0.062).
  • the preset brightness of the red sub-pixel is 163.2 nits
  • the preset brightness of the green sub-pixel is 567.4 nits
  • the preset brightness of the blue sub-pixel is 69.4 nits.
  • the preset brightness of the white light can be set to 1000 nits, and the preset white balance coordinates of the white light can be (0.307, 0.321), then the chromaticity value of the object color of the white light It is (956.4,1000,1158.9).
  • the center value of the preset color coordinates of the red sub-pixel may be (0.698, 0.302), the center value of the preset color coordinates of the green sub-pixel may be (0.298, 0.662), and the center value of the preset color coordinates of the blue sub-pixel
  • the center value can be (0.137, 0.062).
  • the preset brightness of the red sub-pixel is 190.4 nits
  • the preset brightness of the green sub-pixel is 723.3 nits
  • the preset brightness of the blue sub-pixel is 86.3 nits.
  • the current efficiency of each color sub-pixel can be directly measured by optical testing equipment and electrical testing equipment.
  • the optical test equipment may be, for example, a spectrophotometer PR788, and the electrical test equipment may be, for example, a digital source meter Keithley 2400.
  • the required preset current efficiency can be obtained according to the current efficiency measured for each color sub-pixel in a general display device. According to the different materials of the organic light-emitting elements of the sub-pixels of different colors, the preset current efficiency of each organic light-emitting element is also different.
  • the current efficiencies of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are 48 cd/A, 118 cd/A, and 7.2 cd/A, respectively.
  • the red sub-pixels, green sub-pixels, and blue sub-pixels can be obtained.
  • the currents are 292 mA, 361 mA and 601 mA. It should be noted that the brightness used in calculating the current is the brightness considering the overall transmittance of the screen.
  • the overall transmittance of the display screen is 42%, and the brightness of the red sub-pixel used to calculate the current is 438.3 nits, the brightness of the green sub-pixel for current calculation is 1331.2 nits, and the brightness of the blue sub-pixel for current calculation is 135.2 nits.
  • the driving transistors of each color sub-pixel use the same channel width-to-length ratio, the current that needs to be provided to the blue sub-pixel is 2.06 times the current that needs to be provided to the red sub-pixel, and the current that needs to be provided to the blue sub-pixel is 2.06 times that of the red sub-pixel.
  • the current provided by the pixel is 1.67 times the current that needs to be provided to the green sub-pixel.
  • the current efficiencies of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are 24 cd/A, 98 cd/A, and 5.8 cd/A, respectively.
  • the required currents of the red sub-pixel, the green sub-pixel, and the blue sub-pixel can be obtained. It is 518 mA, 441 mA and 911 mA.
  • the driving transistors of each color sub-pixel use the same channel width-to-length ratio, the current that needs to be provided to the blue sub-pixel is 1.76 and 2.06 of the current that needs to be provided to the red sub-pixel and the green sub-pixel, respectively. Times. As a result, the driving transistor of the blue sub-pixel may not be able to provide such a large current due to insufficient driving capability, resulting in insufficient blue light brightness of the display device, thereby affecting the white balance of white light.
  • the current efficiencies of the red sub-pixel, the green sub-pixel, and the blue sub-pixel are 30 cd/A, 118 cd/A, and 8 cd/A, respectively.
  • the required currents of the red sub-pixel, the green sub-pixel, and the blue sub-pixel can be obtained. It is 483 mA, 467 mA and 821 mA.
  • the driving transistors of each color sub-pixel use the same channel width-to-length ratio, the current that needs to be provided to the blue sub-pixel is 1.7 and 1.76 of the current that needs to be provided to the red sub-pixel and the green sub-pixel, respectively. Times.
  • the driving transistor of the blue sub-pixel may not be able to provide such a large current due to insufficient driving capability, resulting in insufficient blue light brightness of the display device, thereby affecting the white balance of white light.
  • the channel width-to-length ratio of the driving transistor of the blue sub-pixel can be designed to be larger than that of the driving transistors of other color sub-pixels, so that the driving transistor of the blue sub-pixel can provide blue color.
  • the current value required for the maximum brightness or the maximum gray scale of the color sub-pixels, so that the brightness of the white light can reach 800 nits or more while ensuring that the white light of the display device is in the preset white balance color coordinate state.
  • S103 Calculate the ratio of the channel width to length ratio of the driving transistor of each color subpixel according to the preset brightness and the preset current efficiency of each color subpixel.
  • the preset current efficiencies of the first color sub-pixel and the second color sub-pixel are E1 and E2, respectively, and the preset brightness of the first color sub-pixel and the second color sub-pixel are Y1 and Y2, respectively.
  • the preset brightness and preset current efficiency of the pixels and the second color sub-pixels calculating the ratio of the channel width-to-length ratio of the first driving transistor to the channel width-to-length ratio of the second driving transistor includes:
  • the ratio is calculated according to the ratio relation (W1/L1): (W2/L2) that the ratio of the channel width-to-length ratio of the first driving transistor to the channel width-to-length ratio of the second driving transistor approximately satisfies.
  • the preset current efficiencies of the blue sub-pixel, the red sub-pixel, and the green sub-pixel are respectively E B , E R and E G
  • the preset brightness of the blue sub-pixel, the red sub-pixel, and the green sub-pixel are Y [ B] , Y [R] and Y [B] .
  • the ratio of the channel width to length ratio of the driving transistor of each color sub-pixel can be calculated according to the above-mentioned parameters and the relational formula (5). Assuming that the preset data signal Vdata input to each color sub-pixel is the same and the brightness of each color sub-pixel is at the highest brightness or highest gray level of the display device, the driving transistors in the red sub-pixel, green sub-pixel, and blue sub-pixel are The channel width to length ratio satisfies the following proportional relationship (13):
  • the difference between the input data signals of each color sub-pixel can be designed to be small (for example, the difference between the input data signals of different color sub-pixels is not more than 1.5V) so that each color sub-pixel has approximately the same data signal range.
  • the ratio of the channel width to length ratio of the driving transistors in the red sub-pixel, the green sub-pixel, and the blue sub-pixel can be set to 1:1:2.
  • the embodiments of the present disclosure are not limited to this, as long as the ratio of the channel width to length ratio of the driving transistors of the red sub-pixel, the green sub-pixel, and the blue sub-pixel satisfies the following range 1: (0.7 ⁇ 1.3): (1.5 ⁇ 2.5) can.
  • the channel width-to-length ratio of the driving transistors of the blue sub-pixels can be designed to be 5/25 according to the ratio between the channel width-to-length ratios of the driving transistors of the respective color sub-pixels, and the green sub-pixels and the red sub-pixels can be designed as 5/25.
  • the channel width to length ratio of the pixels are all designed to be 3/30.
  • the embodiments of the present disclosure are not limited to this, and can be adjusted according to actual process requirements.
  • the channel width-to-length ratio of the driving transistors of the blue sub-pixels can be designed to be 4/25 ⁇ 6.5/25
  • the channel width-to-length ratios of the driving transistors of the blue sub-pixels can be designed to be 4/25 ⁇ 6.5/25
  • the green sub-pixels The channel width-to-length ratios of the pixels and the red sub-pixels are both designed to be 2.4/30 to 4/30.
  • FIG. 3 is a simulation curve diagram of the data voltage of each color sub-pixel and the current between the drain and source of the thin film transistor driving the organic light-emitting element of each color sub-pixel in the second example of the embodiment of the disclosure.
  • the proportional relationship of the channel width to length ratio of the driving transistors of each color sub-pixel in the second example above ie (W/L) R : (W/L) G : (W/L) B ⁇ 1:1 : 2), setting the channel width to length ratio of the driving transistor of each color sub-pixel, thereby obtaining the simulation graph shown in FIG. 3.
  • the blue sub-pixel is driven by
  • the current between the drain and source of the thin film transistor of the organic light-emitting element of the pixel 110 is about 666.9 nanoamps, and the current value required by all the blue sub-pixels is 666.9*1920*720 nanoamps, that is, 921 milliamperes;
  • the current between the drain and source of the thin film transistor driving the organic light-emitting element of the red sub-pixel 120 is about 322.9 nanoamperes, and the current value required by all the red sub-pixels is 322.9*1920*720 nanoamperes, that is, 446 milliamperes;
  • the current between the drain and source of the thin film transistor of the organic light-emitting element of the green sub-pixel 130 is approximately 378.3 nanoamperes, and the current value
  • the result in the simulation curve is roughly consistent with the value of the current required by each color sub-pixel in the second example. Therefore, by designing the channel width-to-length ratio of the driving transistor of the blue sub-pixel to be larger than that of the driving transistors of other color sub-pixels, the driving transistor of the blue sub-pixel can provide blue sub-pixels.
  • FIG. 4 is a graph of the gate voltage and the current between the drain and the source of driving transistors with different channel width to length ratios.
  • the different curves in Figure 4 represent different channel width to length ratios.
  • the threshold voltage of the drive transistor in a drive transistor with a channel width to length ratio of 3/35, the threshold voltage of the drive transistor is -2.47094V, and the gate The voltage is -5.9V; in a driving transistor with a channel aspect ratio of 4/35, the threshold voltage of the driving transistor is -2.5126V, and the gate voltage is -5.9V; when the channel aspect ratio is 5/35 In the driving transistor, the threshold voltage of the driving transistor is -2.4872V, and the gate voltage is -5.4V. From the above-mentioned values of the gate voltage and threshold voltage of each driving transistor, it can be seen that changing the channel width-to-length ratio of the driving transistor does not basically affect the driving characteristics of the driving transistor.
  • FIG. 5A-5C are graphs showing the relationship between the channel width-to-length ratio and the charging rate of the driving transistor in each color sub-pixel.
  • FIG. 5A shows that the driving circuit of the red sub-pixel writes data signals corresponding to high gray scales (for example, 255 gray scales), medium gray scales (for example, 128 gray scales), and low gray scales (for example, 32 gray scales).
  • the charging rate when the channel aspect ratio of the driving transistor is 5/35 and 4/35 is greater than the charging rate when the channel aspect ratio of the driving transistor is 3/35.
  • FIG. 5A shows that the charging rate when the channel aspect ratio of the driving transistor is 5/35 and 4/35 is greater than the charging rate when the channel aspect ratio of the driving transistor is 3/35.
  • 5B shows a situation in which data signals corresponding to high gray scales (for example, 255 gray scales), medium gray scales (for example, 128 gray scales), and low gray scales (for example, 32 gray scales) are written in the driving circuit of the green sub-pixel Below, the change of the charging rate of the different channel width-to-length ratios of the driving transistor. As shown in FIG. 5B, the charging rate when the channel aspect ratio of the driving transistor is 5/35 and 4/35 is greater than the charging rate when the channel aspect ratio of the driving transistor is 3/35.
  • 5C is a case in which data signals corresponding to high gray scales (for example, 255 gray scales), medium gray scales (for example, 128 gray scales), and low gray scales (for example, 32 gray scales) are written in the driving circuit of the blue sub-pixel, The change of the charging rate of the different channel width-to-length ratios of the driving transistor. As shown in FIG. 5C, the charging rate when the channel aspect ratio of the driving transistor is 5/35 and 4/35 is greater than the charging rate when the channel aspect ratio of the driving transistor is 3/35.
  • the charging rate can reduce the charging time.
  • Another embodiment of the present disclosure provides an organic light emitting diode display device including the above-mentioned array substrate.
  • the organic light emitting diode display device is a vehicle-mounted display device.
  • the embodiments of the present disclosure are not limited to organic light-emitting diodes as vehicle-mounted display devices, but can also be any products or components with display functions such as digital cameras, mobile phones, watches, tablet computers, and notebook computers.
  • the embodiment is not limited thereto.
  • FIG. 6 is a schematic block diagram of a display substrate provided according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a repeating unit of a display substrate provided according to an embodiment of the present disclosure
  • FIG. 8 is A schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 1000 provided by the embodiment of the present disclosure includes a base substrate 100 and a base substrate 100 arranged on the base substrate 100 along a first direction (ie Y direction) and a second direction (ie X Direction) a plurality of repeating units 11 arranged, the first direction and the second direction intersect.
  • first direction and the second direction are perpendicular.
  • Each repeating unit 11 includes a plurality of sub-pixels 22, such as a first color sub-pixel 110 and a second color sub-pixel 120.
  • Each color sub-pixel 22 includes an organic light-emitting element 220 and a pixel circuit 221.
  • the pixel circuit 221 is used to drive the organic light-emitting element 220 to emit light, and the pixel circuit 221 includes a driving circuit 222.
  • the driving circuit 222 of the first color sub-pixel 110 includes a first driving transistor 111
  • the driving circuit 222 of the second color sub-pixel 120 includes a second driving transistor 121.
  • the channel aspect ratio of the first driving transistor 111 is larger than that of the second driving transistor. 121 channel width to length ratio.
  • the relationship between the channel width-to-length ratio of the first driving transistor and the channel width-to-length ratio of the second driving transistor in the embodiments of the present disclosure is the same as that of the first driving transistor in the embodiment shown in FIGS. 1A-1E
  • the relationship between the ratio and the channel width-to-length ratio of the second driving transistor is the same, and will not be repeated here.
  • the display substrate 1000 may be applied to a display panel, such as an active matrix organic light emitting diode (AMOLED) display panel, etc.
  • the display substrate 1000 may be an array substrate.
  • the base substrate 100 may be a suitable substrate such as a glass substrate, a quartz substrate, or a plastic substrate.
  • each repeating unit 11 further includes a third color sub-pixel 130
  • the third color sub-pixel 130 includes a third driving transistor 131
  • the channel width to length ratio of the third driving transistor 131 is smaller than that of the first driving transistor.
  • the channel width to length ratio of the transistor 111 is smaller than that of the first driving transistor.
  • the relationship between the channel width-to-length ratios of the first driving transistor, the second driving transistor, and the third driving transistor in the embodiment of the present disclosure is similar to that of the first driving transistor and the second driving transistor in the embodiment shown in FIGS. 1A-1E.
  • the relationship between the channel width-to-length ratio of the transistor and the third driving transistor is the same, and will not be repeated here.
  • the pixel circuits of the first color sub-pixel 110, the second color sub-pixel 120, and the third color sub-pixel 130 are sequentially along the first direction (the arrow in the Y direction indicates Direction) arranged.
  • a column of sub-pixels arranged along the X direction are sub-pixels of the same color.
  • the area covered by the orthographic projection of the pixel circuit of each color sub-pixel on the base substrate 100 is approximately within a rectangle (the dashed frame 1101 shown in FIG. 10). It should be noted that some signal lines of the pixel circuit include parts located in the rectangle and parts extending outside the rectangle. Therefore, the orthographic projection of the pixel circuit on the substrate here mainly includes the structure of various transistors, capacitors and other elements. The orthographic projection on the base substrate and the orthographic projection of the part of each signal line in the rectangle on the base substrate.
  • the organic light emitting element 220 of each sub-pixel 22 includes a first electrode, a second electrode, and a light emitting layer disposed between the first electrode and the second electrode.
  • One of the first electrode and the second electrode of the organic light emitting element 220 is electrically connected to the driving transistor.
  • FIGS. 7-9E are described by taking the second electrode of the organic light emitting element electrically connected to the driving transistor as an example.
  • the pixel circuit 221 further includes a second light emission control circuit 223 and a first light emission control circuit 224.
  • the driving circuit 222 includes a control terminal, a first terminal, and a second terminal, and is configured to provide the organic light emitting element 220 with a driving current for driving the organic light emitting element 220 to emit light.
  • the second light emission control circuit 223 is connected to the first terminal of the driving circuit 222 and the first voltage terminal VDD, and is configured to realize that the connection between the driving circuit 222 and the first voltage terminal VDD is turned on or off.
  • the light emitting control circuit 224 is electrically connected to the second end of the driving circuit 222 and the first electrode of the organic light emitting element 220, and is configured to realize the on or off of the connection between the driving circuit 222 and the organic light emitting element 220.
  • the pixel circuit 221 further includes a data writing circuit 226, a storage circuit 227, a threshold compensation circuit 228, and a reset circuit 229.
  • the data writing circuit 226 is electrically connected to the first terminal of the driving circuit 222, and is configured to write the data signal into the storage circuit 227 under the control of the scan signal;
  • the storage circuit 227 and the control terminal and the first voltage terminal of the driving circuit 222 VDD is electrically connected and configured to store data signals;
  • the threshold compensation circuit 228 is electrically connected to the control terminal and the second terminal of the drive circuit 222, and is configured to perform threshold compensation on the drive circuit 222;
  • the control terminal is electrically connected to the first electrode of the organic light emitting element 220, and is configured to reset the control terminal of the driving circuit 222 and the first electrode of the organic light emitting element 220 under the control of the reset control signal.
  • the driving circuit 222 includes a driving transistor T1
  • the control terminal of the driving circuit 222 includes the gate of the driving transistor T1
  • the first terminal of the driving circuit 222 includes the first electrode of the driving transistor T1
  • the driving circuit 222 includes the driving circuit 222
  • the second terminal includes the second terminal of the driving transistor T1.
  • the data writing circuit 226 includes a data writing transistor T2
  • the storage circuit 227 includes a storage capacitor C
  • the threshold compensation circuit 228 includes a threshold compensation transistor T3
  • the second light emission control circuit 223 includes a second light emission control transistor.
  • the first light emission control circuit 224 includes a first light emission control transistor T5
  • the reset circuit 229 includes a first reset transistor T6 and a second reset transistor T7
  • the reset control signal may include a first sub-reset control signal and a second sub-reset control signal .
  • the first pole of the data writing transistor T2 is electrically connected to the first pole of the driving transistor T1, and the second pole of the data writing transistor T2 is configured to be electrically connected to the data line Vd to receive the data signal.
  • the gate of the data writing transistor T2 is configured to be electrically connected to the first scan signal line Ga1 to receive the scan signal; the first electrode of the storage capacitor C is electrically connected to the first power supply terminal VDD, and the second electrode of the storage capacitor C is electrically connected to The gate of the driving transistor T1 is electrically connected; the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the threshold compensation transistor T3 The gate is configured to be electrically connected to the second scan signal line Ga2 to receive the compensation control signal; the first electrode of the first reset transistor T6 is configured to be electrically connected to the first reset power terminal Vinit1 to receive the first reset signal, The
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power terminal VSS may be a voltage source to output a constant first voltage.
  • Two voltages, the second voltage is a negative voltage, etc.
  • the second power supply terminal VSS may be grounded.
  • the scan signal and the compensation control signal may be the same, that is, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may be electrically connected to the same signal line, such as the first scan signal line.
  • Ga1 is used to receive the same signal (for example, a scan signal).
  • the display substrate 1000 may not be provided with the second scan signal line Ga2 to reduce the number of signal lines.
  • the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may also be electrically connected to different signal lines, that is, the gate of the data writing transistor T2 is electrically connected to the first scanning signal line Ga1, and the threshold The gate of the compensation transistor T3 is electrically connected to the second scan signal line Ga2, and the first scan signal line Ga1 and the second scan signal line Ga2 transmit the same signal.
  • the scan signal and the compensation control signal may also be different, so that the gate of the data writing transistor T2 and the threshold compensation transistor T3 can be controlled separately, which increases the flexibility of controlling the pixel circuit.
  • the first light emission control signal and the second light emission control signal may be the same, that is, the gate of the second light emission control transistor T4 and the gate of the first light emission control transistor T5 may be electrically connected to the same signal Lines, such as the first light emission control signal line EM1, to receive the same signal (e.g., the first light emission control signal).
  • the display substrate 1000 may not be provided with the second light emission control signal line EM2 to reduce the number of signal lines.
  • the gate of the second light emission control transistor T4 and the gate of the first light emission control transistor T5 may also be electrically connected to different signal lines, that is, the gate of the second light emission control transistor T4 is electrically connected to the first light emission.
  • the control signal line EM1 the gate of the first light emission control transistor T5 is electrically connected to the second light emission control signal line EM2
  • the first light emission control signal line EM1 and the second light emission control signal line EM2 transmit the same signal.
  • the second light-emission control transistor T4 and the first light-emission control transistor T5 are different types of transistors, for example, the second light-emission control transistor T4 is a P-type transistor, and the first light-emission control transistor T5 is an N-type transistor.
  • the first lighting control signal and the second lighting control signal may also be different, which is not limited in the embodiment of the present disclosure.
  • the first sub-reset control signal and the second sub-reset control signal may be the same, that is, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may be electrically connected to the same signal line, for example, the first reset The signal line Rst1 is controlled to receive the same signal (for example, the first sub-reset control signal).
  • the display substrate 1000 may not be provided with the second reset control signal line Rst2 to reduce the number of signal lines.
  • the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may also be electrically connected to different signal lines, that is, the gate of the first reset transistor T6 is electrically connected to the first reset control signal line Rst1 , The gate of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2, and the first reset control signal line Rst1 and the second reset control signal line Rst2 transmit the same signal.
  • the first sub-reset control signal and the second sub-reset control signal may also be different.
  • the second sub-reset control signal may be the same as the scan signal, that is, the gate of the second reset transistor T7 may be electrically connected to the first scan signal line Ga1 to receive the scan signal as the second sub-reset control signal.
  • the gate of the first reset transistor T6 and the source of the second reset transistor T7 are respectively connected to the first reset power terminal Vinit1 and the second reset power terminal Vinit2, and the first reset power terminal Vinit1 and the second reset power terminal Vinit2 can be It is the DC reference voltage terminal to output a constant DC reference voltage.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same.
  • the gate of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the same reset power terminal.
  • the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 may be high-voltage terminals or low-voltage terminals, as long as they can provide the first reset signal and the second reset signal to the gate of the driving transistor T1 and the light-emitting element 220.
  • the first electrode only needs to be reset, which is not limited in the present disclosure.
  • the driving circuit 222, the data writing circuit 226, the storage circuit 227, the threshold compensation circuit 228, and the reset circuit 229 in the pixel circuit shown in FIG. 8 are only illustrative, and the driving circuit 222, the data writing circuit
  • the specific structures of the circuits 226, the storage circuit 227, the threshold compensation circuit 228, and the reset circuit 229 can be set according to actual application requirements, which are not specifically limited in the embodiment of the present disclosure.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type MOS transistors) as an example to explain in detail the description of the present disclosure.
  • the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the second light emission control transistor T4, the first light emission control transistor T5, the first reset transistor T6, and the first The two reset transistors T7 and so on can all be P-type transistors.
  • the transistors of the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs. .
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors. .
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, all or part of the transistors in the embodiments of the present disclosure have the first pole and the second pole.
  • the first pole and the second pole are interchangeable as needed.
  • the pixel circuit of the sub-pixel can be a structure including other numbers of transistors in addition to the 7T1C (that is, seven transistors and one capacitor) structure shown in FIG. 8.
  • the 7T2C structure that is, seven transistors and one capacitor
  • a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure which is not limited in the embodiment of the present disclosure.
  • FIGS. 9A-10A are schematic diagrams of various layers of a pixel circuit provided by some embodiments of the present disclosure. The following describes the positional relationship of the various circuits in the pixel circuit on the backplane with reference to FIGS. 9A-10A.
  • the example shown in FIGS. 9A-10A takes the pixel circuit 221 of a repeating unit 11 as an example, and uses the first color sub-pixel 110
  • the positions of the transistors of the included pixel circuits are illustrated, and the positions of the components included in the pixel circuits in the sub-pixels of other colors are approximately the same as the positions of the transistors included in the sub-pixels of the first color.
  • FIG. 9A-10A are schematic diagrams of various layers of a pixel circuit provided by some embodiments of the present disclosure. The following describes the positional relationship of the various circuits in the pixel circuit on the backplane with reference to FIGS. 9A-10A.
  • the example shown in FIGS. 9A-10A takes the pixel circuit 221 of a repeat
  • the pixel circuit 221 of the first color sub-pixel 110 includes the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the second light emission control transistor T4, and the first light emission control transistor shown in FIG. T5, the first reset transistor T6 and the second reset transistor T7, and the storage capacitor C.
  • 9A-10A also show the first scan signal line Ga1, the second scan signal line Ga2, and the first reset control signal line Rst1, the second reset control signal line Rst2, which are electrically connected to the pixel circuits 121 of the respective color sub-pixels.
  • the first power source signal line VDD1 and the second power source signal line VDD2 are electrically connected to each other, and the first power source signal line VDD1 and the third power source signal line VDD3 are electrically connected to each other.
  • the power line VDD3 overlaps the data line Vd in the third direction perpendicular to the base substrate.
  • the first scan signal line Ga1 and the second scan signal line Ga2 are the same signal line
  • the first reset power signal line Init1 and the second reset power signal line Init2 Is the same signal line
  • the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same signal line
  • the first light emission control signal line EM1 and the second light emission control signal line EM2 are the same signal line, but not Limited to this.
  • FIG. 9A shows the active semiconductor layer 310 of the pixel circuit in the display substrate.
  • the active semiconductor layer 310 may be formed by patterning a semiconductor material.
  • the active semiconductor layer 310 can be used to make the aforementioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, second light emission control transistor T4, first light emission control transistor T5, first reset transistor T6, and second reset transistor T7.
  • the active semiconductor layer 310 includes the active layer pattern and the doped region pattern of each transistor of each sub-pixel (that is, the source region s and the drain region d shown in the third color sub-pixel), and in the same pixel circuit
  • the active layer pattern and the doped region pattern of each transistor are integrally arranged.
  • the active layer may include an integrally formed low-temperature polysilicon layer, in which the source region and the drain region may be conductive through doping or the like to achieve electrical connection of each structure. That is, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed by p-silicon, and each transistor in the same pixel circuit includes a pattern of doped regions (ie source region s and drain region d) and In the source layer pattern, the active layers of different transistors are separated by a doped structure.
  • the active semiconductor layers in the pixel circuits of the sub-pixels of different colors arranged in the first direction have no connection relationship and are disconnected from each other.
  • the active semiconductor layers in the pixel circuits of the sub-pixels of the same color arranged in the second direction may be integrated, or may be disconnected from each other.
  • the active semiconductor layer 310 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the gate metal layer of the pixel circuit may include a first conductive layer and a second conductive layer.
  • a gate insulating layer (as shown in FIG. 10B and FIG. 10C) is formed on the above-mentioned active semiconductor layer 310 to protect the above-mentioned active semiconductor layer 310.
  • FIG. 9B shows the first conductive layer 320 included in the display substrate.
  • the first conductive layer 320 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 310.
  • the first conductive layer 320 may include the second electrode CC2 of the storage capacitor C, the first scan signal line Ga1, the first reset control signal line Rst1, the first light emission control signal line EM1, the driving transistor T1, the data writing transistor T2, and the threshold value.
  • the gate of the data writing transistor T2 may be the part where the first scan signal line Ga1 overlaps the active semiconductor layer 310;
  • the gate of the second light emission control transistor T4 may be the first light emission control The first part where the signal line EM1 overlaps the active semiconductor layer 310, and the gate of the first light emission control transistor T5 may be the second part where the first light emission control signal line EM1 overlaps the active semiconductor layer 310;
  • the first reset transistor The gate of T6 is the first part where the first reset control signal line Rst1 overlaps the active semiconductor layer 310, and the gate of the second reset transistor T7 is the second part where the first reset control signal line Rst1 overlaps the active semiconductor layer 310
  • the threshold compensation transistor T3 may be a thin film transistor with a double-gate structure, the first gate of the threshold compensation transistor T3 may be the overlapped portion of the first scan signal line Ga1 and the active semiconductor layer 310, and the second gate of the threshold compensation transistor T3 Each gate may be a portion where the protrusion
  • each dashed rectangular frame in FIG. 9A shows each part where the first conductive layer 320 and the active semiconductor layer 310 overlap.
  • the first scan signal line Ga1, the first reset control signal line Rst1, and the first light emission control signal line EM1 are arranged along the second direction X.
  • the first scan signal line Ga1 is located between the first reset control signal line Rst1 and the first light emission control signal line EM1.
  • the second electrode CC2 of the storage capacitor C (that is, the gate of the driving transistor T1) is located between the first scan signal line Ga1 and the first light emission control signal line EM1.
  • the protrusion P protruding from the first scan signal line Ga1 is located on the side of the first scan signal line Ga1 away from the first light emission control signal line EM1.
  • the gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6, and the gate of the second reset transistor T7 are all Located on the first side of the gate of the driving transistor T1, the gate of the second light-emitting control transistor T4 and the gate of the first light-emitting control transistor T5 are both located on the second side of the gate of the driving transistor T1.
  • the first side and the second side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel are mutually in the second direction X. Opposite sides.
  • FIGS. 9A-10A Opposite sides.
  • the first side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel may be the upper side of the gate of the driving transistor T1.
  • the second side of the gate of the driving transistor T1 of the pixel circuit of the pixel may be the lower side of the gate of the driving transistor T1.
  • the lower side for example, the side of the display substrate for bonding the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor T1 is the side closer to the IC of the gate of the driving transistor T1.
  • the upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor T1 farther away from the IC.
  • the gate of the data writing transistor T2 and the gate of the second light emission control transistor T4 are both located at the gate of the driving transistor T1.
  • the first gate of the threshold compensation transistor T3, the gate of the first light emission control transistor T5, and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1.
  • the third side and the fourth side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel are mutually in the first direction Y. Opposite sides. For example, as shown in FIGS.
  • the third side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel may be the left side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel
  • the fourth side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel may be the right side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel.
  • the left side and the right side for example, in the same pixel circuit, the data line is on the left side of the first power signal line VDD1, and the first power signal line VDD1 is on the right side of the data line.
  • a first insulating layer (as shown in FIGS. 10B and 10C) is formed on the above-mentioned first conductive layer 320 to protect the above-mentioned first conductive layer 320.
  • 9C shows the second conductive layer 330 of the pixel circuit.
  • the second conductive layer 330 includes the first electrode CC1 of the storage capacitor C, the first reset power supply signal line Init1, the second power supply signal line VDD2, and the light shielding part S.
  • the second power signal line VDD2 is integrally formed with the first pole CC1 of the storage capacitor C.
  • the first pole CC1 of the storage capacitor C and the second pole CC2 of the storage capacitor C at least partially overlap to form the storage capacitor C.
  • FIG. 9D shows the source and drain metal layer 340 of the pixel circuit.
  • the source and drain metal layer 340 includes a data line Vd, a first power signal line VDD1 and a shielding line 344.
  • the above-mentioned data line Vd, the first power supply signal line VDD1, and the shielding line 344 all extend in the X direction.
  • the shielding line 344 and the data line Vd are arranged in the same layer and the same material, so that the shielding line and the data line can be formed at the same time in the same patterning process, avoiding adding additional patterning processes for making the shielding line, thereby simplifying the production process of the display substrate. Save production cost.
  • the source-drain metal layer 340 further includes a first connection portion 341, a second connection portion 342, and a third connection portion 343 (ie, the connection structure 343).
  • FIG. 9D also shows exemplary positions of a plurality of via holes, and the source-drain metal layer 340 is connected to a plurality of film layers located between the source-drain metal layer 340 and the base substrate through the plurality of via holes shown.
  • different filled vias indicate that the source and drain metal layers 340 are connected to different film layers through them.
  • a white filled via means that the source and drain metal layer 340 is connected to the active semiconductor layer 310 shown in FIG.
  • a black dot filled via means that the drain metal layer 340 is connected to the second layer shown in FIG. 9C through it.
  • the second conductive layer, the specific film layer where each via is located, and the specific connection relationship will be described in detail in the subsequent figure shown in FIG. 10A.
  • a third insulating layer and a fourth insulating layer are formed on the aforementioned source and drain metal layer 340 to protect the aforementioned source and drain metal layer 340.
  • the second electrode of the organic light emitting element of each sub-pixel may be arranged on the side of the third insulating layer and the fourth insulating layer away from the base substrate.
  • FIG. 9E shows the third conductive layer 350 of the pixel circuit.
  • the third conductive layer 350 includes a fourth connection portion 353 and a third power signal line VDD3 distributed across the X direction and the Y direction.
  • FIG. 9E also shows exemplary positions of a plurality of via holes 351 and 354, and the third conductive layer 350 is connected to the source and drain metal layer 340 through the plurality of via holes 351 and 354 as shown.
  • FIG. 10A is a schematic diagram of the stacked positional relationship of the above-mentioned active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the source/drain metal layer 340, and the third conductive layer 350.
  • the data line Vd passes through at least one via (for example, via 381) among the gate insulating layer, the first insulating layer, and the second insulating layer to write data in the active semiconductor layer 310.
  • the source region of the transistor T2 is connected.
  • the first power signal line VDD1 passes through at least one of the gate insulating layer, the first insulating layer, and the second insulating layer (for example, the via 382) and the corresponding second light emitting control transistor T4 in the active semiconductor layer 310.
  • the source regions are connected.
  • one end of the first connection portion 341 passes through at least one of the gate insulating layer, the first insulating layer, and the second insulating layer through at least one via (for example, via 384) and the active semiconductor layer 310
  • the drain region of the corresponding threshold compensation transistor T3 is connected, and the other end of the first connection portion 341 is connected to the first conductive layer 320 through at least one via (for example, via 385) in the first insulating layer and the second insulating layer.
  • the gate of the driving transistor T1 that is, the second electrode CC2 of the storage capacitor C
  • the second connecting portion 342 is connected to the first reset power signal line Init1 through a via (for example, via 386) in the second insulating layer, and the other end of the second connecting portion 342 is connected to the first reset power signal line Init1 through the gate insulating layer, the first At least one via (for example, via 387) in the insulating layer and the second insulating layer is connected to the drain region of the second reset transistor T7 in the active semiconductor layer 310.
  • the third connection portion 343 (connection structure 343) passes through an inorganic layer between the connection structure 343 and the active semiconductor layer 310, such as at least one of the gate insulating layer 103, the first insulating layer 104, and the second insulating layer 105.
  • the hole (for example, the via hole 352, that is, the first connection hole 343-1) is connected to the drain region of the first light emission control transistor T5 in the active semiconductor layer 310.
  • source region and drain region of the transistor used in the embodiments of the present disclosure can be the same in structure, so the source region and drain region can be the same in structure, so as needed The two are interchangeable.
  • the first power supply signal line VDD1 passes through at least one via (for example, via 3832) in the second insulating layer between the second conductive layer 330 and the source/drain metal layer 340 and The first pole CC1 of the storage capacitor C in the second conductive layer 330 is connected.
  • the shield line 344 extends along the X direction, and its orthographic projection on the base substrate is located between the orthographic projection of the drive transistor on the base substrate and the orthographic projection of the data line on the base substrate. between.
  • the shielding line in the pixel circuit of the first color sub-pixel can reduce the influence of the signal transmitted on the data line in the pixel circuit of the second color sub-pixel on the performance of the threshold compensation transistor T3 of the first color sub-pixel.
  • the influence of coupling between the gate of the driving transistor of the first color sub-pixel and the data line of the second color sub-pixel is reduced, and the crosstalk problem is reduced.
  • the shielding line 344 is connected to the first reset power signal line Init1 through at least one via (for example, via 332) in the second insulating layer.
  • the shielding line In addition to making the shielding line have a fixed potential, It also makes the voltage of the initialization signal transmitted on the first reset power signal line more stable, which is more conducive to the working performance of the pixel driving circuit.
  • the shield line 344 is respectively coupled to two first reset power signal lines Init1 extending in the Y direction so that the shield line 344 has a fixed potential, and the two first reset power signal lines Init1 is located on both sides of the shield line 344 in the X direction, respectively.
  • the two first reset power supply signal lines correspond to the pixel circuit in the nth row and the pixel circuit in the n+1th row, respectively.
  • the same column of shielding line 344 may be a whole shielding line, the whole shielding line includes a plurality of sub-parts located between two adjacent first reset power signal lines, and each sub-part is located in the column respectively. Within each pixel circuit area.
  • the shield line 344 can also be coupled with the first power signal line, so that the shield line 344 has the same fixed potential as the power signal transmitted by the first power signal line. .
  • the orthographic projection of the shielding line 344 on the base substrate is located between the orthographic projection of the threshold compensation transistor T3 on the base substrate and the orthographic projection of the data line Vd on the base substrate, so that the shielding line 344 can be reduced due to the data.
  • the orthographic projection of the shielding line 344 on the base substrate may be located between the orthographic projection of the first connecting portion 341 on the base substrate and the orthographic projection of the data line on the base substrate; the shielding line 344 is on the base substrate
  • the orthographic projection of is located between the orthographic projection of the driving transistor T1 on the base substrate and the orthographic projection of the data line on the base substrate.
  • the above arrangement method reduces the first crosstalk between the data line and the threshold compensation transistor, and the second crosstalk between the data line and the first connection part, thereby reducing the first crosstalk and the second crosstalk caused by the above-mentioned first crosstalk and the second crosstalk.
  • the resulting indirect crosstalk to the drive transistor reduces the direct crosstalk between the data line and the driving transistor, thereby better ensuring the working performance of the display substrate.
  • the shielding line 344 is not limited to the above-mentioned arrangement.
  • the shielding line 344 can also be coupled only to the reset power signal line corresponding to the pixel circuit in the nth row, or only to the reset power signal line corresponding to the pixel circuit in the n+1th row. Coupling.
  • the extension length of the shielded wire 344 in the X direction can also be set according to actual needs.
  • the pixel circuit of each color sub-pixel further includes a light-shielding portion S1, the light-shielding portion S1 and the shielding line 344 are arranged in different layers, and the orthographic projection of the light-shielding portion S1 on the base substrate and the orthographic projection of the shielding line 344 on the base substrate There is overlap.
  • the shielding line 344 is connected to the light shielding portion S1 in the second conductive layer 330 through the via 331 in the second insulating layer, so that the light shielding portion S1 has a fixed potential, thereby better reducing the threshold compensation transistor T3 and other nearby conductive parts.
  • the coupling effect between the graphics makes the working performance of the display substrate more stable.
  • the active semiconductor layer 310 between the light shielding portion S1 and the two gates of the threshold compensation transistor T3 overlaps to prevent the active semiconductor layer 310 between the two gates from being exposed to light to change characteristics, for example, to prevent this part
  • the voltage of the active semiconductor layer changes to prevent crosstalk.
  • This example schematically shows that the light shielding part is connected to the shielding wire, but it is not limited to this, and the two may not be connected.
  • the third power signal line VDD3 is connected to the first power signal line VDD1 through at least one via 351 in the third insulating layer and the fourth insulating layer, and the fourth connecting portion 353 passes through the third insulating layer.
  • the vias 354 in the insulating layer and the fourth insulating layer are connected to the third connection portion 343.
  • the third insulating layer may be a passivation layer
  • the fourth insulating layer may be a first flat layer
  • the third insulating layer is located between the fourth insulating layer and the base substrate.
  • the fourth insulating layer may be an organic layer, and the thickness of the organic layer is thicker than an inorganic layer such as a passivation layer.
  • the via 351 and the via 354 are both nested vias, that is, the via 351 includes the first via in the third insulating layer and the second via in the fourth insulating layer, and the second via in the third insulating layer A via hole is opposite to the position of the second via hole in the fourth insulating layer, and the orthographic projection of the second via hole in the fourth insulating layer on the base substrate is located on the liner of the first via hole in the third insulating layer. In the orthographic projection on the base substrate.
  • the third power supply signal line VDD3 is distributed in a grid shape, which includes a portion extending in the X direction and a portion extending in the Y direction.
  • the orthographic projection of the third power signal line VDD3 extending in the X direction on the base substrate roughly coincides with the orthographic projection of the first power signal line VDD1 on the base substrate, or the first power signal line VDD1 is on the base substrate.
  • the orthographic projection is located in the orthographic projection of the portion of the third power signal line VDD3 extending in the X direction on the base substrate (FIG.
  • 10A shows that the projections of the two are roughly overlapped as an example), and the third power signal line VDD3 and the first power source
  • the electrical connection of the signal line VDD1 can reduce the voltage drop of the first power supply signal line VDD1, thereby improving the uniformity of the display device.
  • the third power signal line VDD3 may use the same material as the source and drain metal layers.
  • FIG. 10A does not illustrate the positional relationship between the via hole and each layer.
  • an example of the present disclosure takes the first color sub-pixel 110 and the third color sub-pixel 130 as an example where the relative positional relationship of each component included in the pixel circuit is the same, for example, the first color
  • the fourth connection portion 353 of the sub-pixel 110 and the third color sub-pixel 130 overlaps with the drain region of the first light-emitting control transistor T5 included in each sub-pixel.
  • the fourth connection portion 353 in the pixel circuit of the second color sub-pixel 120 does not overlap with the drain region of the first light-emitting control transistor T5, such as the fourth connection portion of the second color sub-pixel 120 353 and the drain region of the first light emission control transistor T5 are respectively located on both sides of the third power signal line VDD3 extending in the Y direction.
  • the third connecting portion 343 of the first color sub-pixel and the third color sub-pixel are both block-shaped structures, and the third connecting portion 343 of the second color sub-pixel is a strip extending in the X direction.
  • One end of the strip portion is used to connect to the fourth connecting portion 353 formed later, and the other end of the strip portion is used to connect to the drain region of the first light-emitting control transistor T5, so that the fourth connecting portion is connected to the The drain region of the first light emission control transistor T5 is connected. Then, the anode of each color sub-pixel to be formed subsequently is connected to the corresponding fourth connection portion 353 through the via hole so as to be connected to the drain region of the first light-emitting control transistor T5.
  • This embodiment includes but is not limited to this.
  • the position of the fourth connecting portion in each color sub-pixel is determined according to the arrangement rule of the organic light-emitting elements and the position of the light-emitting region.
  • FIG. 10B is a partial cross-sectional structural diagram taken along the line AA' in FIG. 10A.
  • the second electrode (for example, the drain electrode T5d) of the first light-emitting control transistor T5 in the active semiconductor layer in the pixel circuit of the second color sub-pixel 120 is disposed on a side away from the base substrate 100
  • There is a gate insulating layer 103 the side of the gate insulating layer 103 away from the base substrate 100 is provided with a first light-emitting control signal line EM1, and the side of the first light-emitting control signal line EM1 away from the base substrate 100 is provided with a first insulation Layer 104, the side of the first insulating layer 104 away from the base substrate 100 is provided with a second power signal line VDD2, the side of the second power signal line VDD2 away from the base substrate 100 is provided with a second insulating layer 105, the second insulating layer A third connecting portion 343 is provided on the side
  • the third connecting portion 343 of the second color sub-pixel 120 passes through the vias 352 of the gate insulating layer 103, the first insulating layer 104, and the second insulating layer 105 and the first light emitting control transistor T5 in the active semiconductor layer 310.
  • the two poles are connected with T5d.
  • the third connection portion 343 overlaps the second power signal line VDD2 and the first light emission control signal line EM1.
  • a third insulating layer 106 and a fourth insulating layer 107 are successively arranged on the side of the third connecting portion 343 away from the base substrate 100, and a fourth connecting portion 353 and a fourth insulating layer 353 are arranged on the side of the fourth insulating layer 107 away from the base substrate 100.
  • the third power signal line VDD3 overlaps the second power signal line VDD2.
  • the fourth connection portion 353 is connected to the third connection portion 343 through nested vias 354 located in the third insulating layer 106 and the fourth insulating layer 107, thereby realizing connection with the second light-emitting control transistor.
  • the data line Vd is connected to the source T2s of the data writing transistor T2 through the vias 381 in the gate insulating layer 103, the first insulating layer 104, and the second insulating layer 105;
  • One end of 341 is connected to the drain T3d of the threshold compensation transistor T3 through the gate insulating layer 103, the first insulating layer 104 and the via 384 of the second insulating layer 105, and the other end of the first connecting portion 341 is connected through the first insulating layer 104 and the via 385 in the second insulating layer 105 are connected to the gate of the driving transistor T1 (that is, the second electrode CC2 of the storage capacitor C);
  • the channel T1c of the driving transistor T1 is located on a side of the gate facing the base substrate 100
  • the source electrode T1d of the driving transistor T1 and its gate electrode and the first electrode CC1 of the storage capacitor C all overlap.
  • FIG. 10C is a schematic partial cross-sectional structure diagram taken along the line BB' in FIG. 10A.
  • the difference between the first color sub-pixel 110 and the second color sub-pixel 120 lies in the orthographic projection of the fourth connection portion 353 in the second color sub-pixel 120 on the base substrate 100 and the first
  • the orthographic projection of the second electrode T5d of the light-emitting control transistor T5 on the base substrate 100 does not overlap, and the orthographic projection of the fourth connection portion 353 in the first color sub-pixel 130 on the base substrate 100 and its first light-emitting control
  • the orthographic projection of the second electrode T5d of the transistor T5 on the base substrate 100 overlaps.
  • the third connection portion 343 does not overlap with the second power supply signal line VDD2 and the first light emission control signal line EM1.
  • the channel T1c of the driving transistor T1 is located on the side of its gate facing the base substrate 100 and overlaps the via 385. It can be seen that the channel width of the driving transistor of the first color sub-pixel is greater than the channel width of the second color sub-pixel.
  • the first scan signal line Ga1, the first reset control signal line Rst1, and the first reset power signal line Init1 are all located in the pixel circuit of the first color sub-pixel.
  • the first light emission control signal line EM1 is located on the second side of the driving transistor T1 of the pixel circuit of the first color sub-pixel.
  • the first scan signal line Ga1, the first reset control signal line Rst1, the first light emission control signal line EM1, and the first reset power signal line Init1 all extend in the first direction Y, and the data line Vd extends in the second direction X .
  • the first power supply signal line VDD1 extends in the second direction X
  • the second power supply signal line VDD2 extends in the first direction Y.
  • the signal line of the first power supply terminal VDD is gridded and wired on the display substrate. That is to say, on the entire display substrate, the first power supply signal line VDD1 and the second power supply signal line VDD2 are arranged in a grid pattern, so that the resistance of the signal line of the first power supply terminal VDD is small, and the voltage drop is low. Improve the stability of the power supply voltage provided by the first power supply terminal VDD.
  • the positional arrangement of the driving circuit, the first light emission control circuit, the second light emission control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit, and the reset circuit in each pixel circuit is not limited to FIG. 9A In the example shown in -10A, according to actual application requirements, the positions of the driving circuit, the first light-emitting control circuit, the second light-emitting control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit, and the reset circuit can be specifically set.
  • FIG. 11A is a schematic diagram of a partial structure of an array substrate provided by an example of this embodiment.
  • the pixel circuit included in each color sub-pixel in the array substrate of this example is the pixel circuit shown in FIG. 10A.
  • the side of the third power signal line VDD3 away from the first power signal line VDD1 is further provided with a fifth insulating layer (not shown).
  • the fifth insulating layer may be the second flat layer, and its material may be the same as that of the fourth insulating layer (ie, the first flat layer), such as an organic material.
  • the first electrode of the first light-emitting control transistor T5 of the second color sub-pixel 120 is electrically connected to the connection structure 343 through the first connection hole 343-1.
  • connection structure 343 is electrically connected to the second electrode 123 of the second color sub-pixel 120 through the second connection hole 343-2 (that is, the via hole 352), and at least part of the first connection hole 343-1 is an orthographic projection on the base substrate Located on the side of the orthographic projection of the light emission control signal line EM1 on the base substrate, the orthographic projection of at least part of the second connection hole 343-2 on the base substrate 100 is located on the light emission control signal line EM1 on the base substrate 100 The other side of the orthographic projection; in at least one pixel unit, the second electrode 133 of the third color sub-pixel 130 controls the driving of the organic light-emitting element of the third color sub-pixel 130 in a third direction perpendicular to the base substrate 100 The channel T1c of the transistor T1 does not overlap.
  • the present disclosure provides a pixel arrangement structure.
  • the positional relationship between the two connecting holes and the light-emitting control signal line and the positional relationship between the second electrode of the third color sub-pixel and the channel of the driving transistor are set. It is possible to effectively drive the second color sub-pixels to emit light through the connection structure on the basis of increasing the compactness of the pixel arrangement to increase the pixel resolution.
  • the second electrodes of the second color sub-pixels 120 and the second electrodes of the third color sub-pixels 130 are alternately arranged along the second direction.
  • the second electrode of the third color sub-pixel and the pixel circuit of the second color sub-pixel overlap in a direction perpendicular to the base substrate.
  • the compactness of the pixel arrangement can be effectively improved.
  • the center of the orthographic projection of the first connection hole 343-1 on the base substrate 100 is located on the side of the orthographic projection of the emission control signal line EM1 on the base substrate 100, and the second connection hole 343-2 is on the base substrate 100.
  • the center of the orthographic projection on 100 is located on the other side of the light-emission control signal line EM1 on the orthographic projection of the base substrate 100.
  • connection structure 343 passes through the second connection hole 343 in at least one of the inorganic layer and the organic layer located between the connection structure 343 and the second electrode 123.
  • -2 is electrically connected to the second electrode 123.
  • the insulating layer 106 may be an inorganic layer
  • the insulating layer 107 may be an organic layer 107, but is not limited thereto.
  • the inorganic layer has the function of electrical insulation and isolation of water and oxygen
  • the organic layer has the function of ensuring the flatness of the anode.
  • the second connection hole 343-2 is a via hole 354 located in the fourth insulating layer 107.
  • connection structure is electrically connected to the second electrode through the second connection hole, and the connection structure and the second electrode may also include via holes located in other film layers for switching.
  • the connecting structure 343 is connected to the fourth connecting portion 353 through the second connecting hole 343-2 located in the third insulating layer 106 and the fourth insulating layer 107, and the fourth connecting portion 353 is connected to the fourth connecting portion 353 through a via hole located in the fifth insulating layer. It is connected with the second electrode, so as to realize the electrical connection between the connection structure and the second electrode.
  • the orthographic projection of the first connection hole 343-1 (that is, 352) on the base substrate 100 has a first area
  • the orthographic projection of the second connection hole 343-2 (ie, 354) on the base substrate 100 has a second area, and the first area and the second area are different.
  • the first connection hole 343-1 has a first distance from the light emission control signal line M1 in the second direction
  • the second The connection hole 343-2 has a second distance to the light emission control signal line EM2 in the second direction, and the first distance and the second distance are different.
  • the distance between the connection hole and the light-emitting control signal line can refer to the distance between the connection hole and the edge of the light-emitting control signal line that are close to each other, but it is not limited to this. It can also be between the center of the connection hole and the center line of the light-emitting control signal line. The distance between.
  • the second electrode 113 (that is, the anode) of the organic light-emitting element of the first color sub-pixel 110 is connected to the fourth connecting portion 353 through the via hole 1133 of the fifth insulating layer, so as to realize the connection with the fourth connecting portion 353.
  • the drain region of a light emission control transistor T5 is connected.
  • the second electrode 133 (that is, the anode) of the organic light-emitting element of the third color sub-pixel 130 is connected to the fourth connecting portion 353 through the via 1333 of the fifth insulating layer, so as to realize the leakage of the first light-emitting control transistor T5.
  • the polar regions are connected.
  • the second electrode 123 (that is, the anode) of the organic light-emitting element of the second color sub-pixel 120 is connected to the fourth connecting portion 353 through the via hole of the fifth insulating layer, and further connected to the third connecting portion 343 to realize the first light emission.
  • the drain region of the control transistor T5 is connected.
  • the second electrode 133 of the third color sub-pixel 130 interacts with other color sub-pixels (such as the first color sub-pixel 110 and the second color sub-pixel 110 in the third direction). None of the channels of the driving transistors T1 of the organic light-emitting element of the sub-pixel 120) overlap.
  • the orthographic projection of the first connection hole 343-1 of the second color sub-pixel 120 on the base substrate 100 is compared with that of the second color sub-pixel 120.
  • the orthographic projection of the connection hole 343-2 on the base substrate 100 is away from the orthographic projection of the second electrode 123 of the second color sub-pixel 120 on the base substrate 100.
  • the first connection hole and the second connection hole in the second color sub-pixel are far away from the light-emitting area of the second color sub-pixel, so the second connection hole is farther away from the second electrode and the light-emitting area.
  • the overlapped area is close, and the flatness of the light-emitting layer and the second electrode in the light-emitting area will not be affected.
  • the second electrode 123 of the second color sub-pixel 120 is connected in the third direction with the groove of the driving transistor T1 of the organic light-emitting element driving the second color sub-pixel 130.
  • the channels overlap, so that the pixels can be arranged closely and the resolution of the pixels can be improved.
  • the data line Vd connected to the pixel circuit of the second color sub-pixel 120 and the second electrode 123 of the second color sub-pixel 120 are in the first direction (ie Y direction) are spaced apart from each other.
  • the orthographic projection of the data line Vd connected to the pixel circuit of the second color sub-pixel 120 on the base substrate 100 and the orthographic projection of the second electrode 123 of the second color sub-pixel 120 on the base substrate 100 do not overlap.
  • the second electrode 123 of the second color sub-pixel 120 and the data line Vd connected to the pixel circuit of the third color sub-pixel 130 overlap in the third direction.
  • the second electrode 113 of the first color sub-pixel 110 and the second electrode 133 of the third color sub-pixel 130 are in a first straight line extending in the second direction.
  • the orthographic projections above overlap with the orthographic projections of the connecting structure 343 of the second color sub-pixel 120 on the first straight line.
  • the orthographic projection of the second electrode 133 of the third color sub-pixel 130 on the second straight line extending along the first direction is connected to the second color sub-pixel 120
  • the orthographic projections of the structure 343 on the second straight line overlap.
  • the second electrode of the organic light emitting element of each color sub-pixel includes a main body electrode and a connecting electrode, and the shape of the main body electrode of each color sub-pixel is a hexagon.
  • the second electrode 113 of the first color sub-pixel 110 includes a first body electrode 1131 and a first connection electrode 1132.
  • the first body electrode 1131 and the first connection electrode 1132 may be an integral structure, and the first A connecting electrode 1132 is connected to the fourth connecting portion 353 through the connecting hole 1133, and then connected to the third connecting portion 343 to connect to the second electrode of the first light-emitting control transistor T5 of the first color sub-pixel 110.
  • the second electrode 123 of the second color sub-pixel 120 includes a second body electrode 1231 and a second connection electrode 1232.
  • the second body electrode 1231 and the second connection electrode 1232 may be an integral structure, and the second connection electrode 1232 passes through the connection hole 1233.
  • the second electrode 133 of the third color sub-pixel 130 includes a third body electrode 1331 and a third connection electrode 1332.
  • the third body electrode 1331 and the third connection electrode 1332 may be an integral structure, and the third connection electrode 1332 passes through the connection hole 1333 It is connected to the fourth connection portion 353 and further connected to the third connection portion 343 to realize connection with the second electrode of the first light-emitting control transistor T5 of the third color sub-pixel 130.
  • the orthographic projection of the body electrode 1131 of the first color sub-pixel 110 on the first straight line and the orthographic projection of the connecting structure 343 of the second color sub-pixel 120 on the first straight line intersect Stacked.
  • the orthographic projection of the main electrode 1331 of the third color sub-pixel 130 on the second straight line overlaps the orthographic projection of the connection structure 343 of the second color sub-pixel 120 on the second straight line.
  • the second electrode 123 of the second color sub-pixel 120 overlaps the scan signal line Ga1 in the third direction.
  • the orthographic projection of the second electrode 123 of the second color sub-pixel 120 on the base substrate 100 overlaps the orthographic projection of the scan signal line Ga1 on the base substrate 100.
  • the second electrode 123 of the second color sub-pixel 120 overlaps the scan signal line Ga1 electrically connected to the pixel circuit of the second color sub-pixel 120 in the third direction.
  • the orthographic projection of the second electrode 123 of the second color sub-pixel 120 on the base substrate 100 and the orthographic projection of the scan signal line Ga1 electrically connected to the pixel circuit of the second color sub-pixel 120 on the base substrate 100 overlap.
  • the second electrode 113 of the first color sub-pixel 110 and the second electrode 133 of the third color sub-pixel 130 are both connected to the emission control signal line EM1 in the third direction. overlap.
  • the orthographic projection of the second electrode 113 of the first color sub-pixel 110 on the base substrate 100 and the orthographic projection of the second electrode 133 of the third color sub-pixel 130 on the base substrate 100 are equal. It overlaps with the orthographic projection of the emission control signal line EM1 on the base substrate 100.
  • the second electrode 113 of the first color sub-pixel 110 includes a first electrode sub-portion 113-1 and a second electrode sub-portion 113- respectively located on both sides of the emission control signal line EM1. 2.
  • the area of the first electrode sub-portion 113-1 is larger than the area of the second electrode sub-portion 113-2.
  • the portions of the second electrode 113 of the first color sub-pixel 110 located on both sides of the center line of the emission control signal line are the first electrode sub-portion 113-1 and the second electrode sub-portion 113-1, respectively.
  • the center of the orthographic projection of the second connection hole 343-2 on the base substrate 100 and the first electrode sub-portion 113-1 on the base substrate 100 are respectively located on both sides of the orthographic projection of the emission control signal line EM1 on the base substrate 100.
  • the second pole CC2 of the storage capacitor C is multiplexed as the gate of the driving transistor T1, and the second pole CC2 of the storage capacitor C of the first color sub-pixel 110 is multiplexed.
  • the area of is different from the area of the second pole CC2 of the storage capacitor C of the second color sub-pixel 120.
  • the area of the second electrode 113 of the first color sub-pixel 110 is larger than the area of the second electrode 123 of the second color sub-pixel 120, and the storage capacitor C of the first color sub-pixel 110 is The area of the second pole CC2 is larger than the area of the second pole CC2 of the storage capacitor C of the second color sub-pixel 120.
  • the first pole CC1 of the storage capacitor C overlaps the connection structure 343 in the third direction.
  • the second electrode 113 of the first color sub-pixel 110 overlaps the data line Vd in the third direction, and the length of the overlapped portion along the second direction is greater than that of the second electrode 113 along the second direction. 80% of the maximum length of the direction, thereby improving the flatness of the second electrode of the first color sub-pixel.
  • the orthographic projection of the second electrode 113 of the first color sub-pixel 110 on the base substrate 100 overlaps the orthographic projection of the data line Vd on the base substrate 100, and the length of the overlapped portion in the second direction is greater than that of the first color.
  • the orthographic projection of the two electrodes 113 is 80% of the maximum length in the second direction.
  • the second electrode 113 of the first color sub-pixel 110 overlaps the power supply line VDD3 in the third direction, and the length of the overlapped portion along the second direction is greater than that of the second electrode 113 along the second direction. 80% of the maximum length of the direction, thereby improving the flatness of the second electrode of the first color sub-pixel.
  • the orthographic projection of the second electrode 113 of the first color sub-pixel 110 on the base substrate 100 overlaps the orthographic projection of the power line VDD3 on the base substrate 100, and the length of the overlapped portion along the second direction is greater than that of the first color.
  • the orthographic projection of the two electrodes 113 is 80% of the maximum length in the second direction.
  • the first connection electrode 1132 of the first color sub-pixel 110 is located on the side of the center of the first body electrode 1131 away from the data line of the sub-pixel pixel circuit in the Y direction, and is located on the first body electrode 1131 in the X direction. The center is far away from the side of the light emission control signal line of the sub-pixel pixel circuit.
  • the first connection electrode 1132 and the first body electrode 1131 of the first color sub-pixel 110 are arranged in the X direction, and the first connection electrode 1132 is located at the lower right corner of the first body electrode 1131.
  • the second connecting electrode 1232 of the second color sub-pixel 120 is located on the side of the second body electrode 1231 away from the data line of the sub-pixel pixel circuit in the Y direction, and located at the center of the second body electrode 1231 in the X direction Close to the side of the light-emitting control signal line of the sub-pixel pixel circuit.
  • the second connection electrode 1232 and the second body electrode 1231 of the second color sub-pixel 120 are arranged in the X direction, and the second connection electrode 1232 is located at the lower right corner of the first body electrode 1231.
  • the third connection electrode 1332 and the third main body electrode 1331 of the third color sub-pixel 130 are arranged in the Y direction, and the third connection electrode 1332 is located on the right side of the third main body electrode 1331, that is, close to the sub-pixel pixel circuit and close to the shield.
  • the third connection electrode 1332 is located on the right side of the third main body electrode 1331, that is, close to the sub-pixel pixel circuit and close to the shield.
  • One side of the line is, close to the sub-pixel pixel circuit and close to the shield.
  • a pixel defining layer (the pixel defining layer 101 shown in FIG. 1B) is also provided between adjacent sub-pixels, and the pixel defining layer includes a light emitting layer used to define sub-pixels of each color.
  • the orthographic projection of the opening of the pixel defining layer on the base substrate is within the orthographic projection of the main body electrode of the corresponding second electrode on the base substrate.
  • the display substrate further includes a pixel defining layer 101 located on the side of the second electrode of each sub-pixel away from the base substrate 100.
  • the pixel defining layer 101 includes a light-emitting layer for defining each sub-pixel. At least part of the organic light-emitting layer of each sub-pixel is located in the opening 1010.
  • the orthographic projection of the opening 1010 of the pixel defining layer 101 on the base substrate 100 is located in the main electrode of the second electrode of each sub-pixel. In the orthographic projection on the base substrate 100.
  • the area of the opening 1010-3 that defines the light-emitting area of each third color sub-pixel 130 is larger than the area of the opening 1010-2 that defines the light-emitting area of each second color sub-pixel 120, and is smaller than that of each first color sub-pixel 120.
  • each color sub-pixel further includes an organic light-emitting layer (the organic light-emitting layer 112 or 122 as shown in FIG. 1B), and the organic light-emitting layer is located on the side of the second electrode away from the base substrate.
  • the second electrode of each color sub-pixel is in contact with the organic light-emitting layer at the opening of the pixel defining layer, and the opening of the pixel defining layer defines the shape of the light-emitting area of the sub-pixel.
  • the second electrode (for example, the anode) of the organic light-emitting element may be disposed under the pixel defining layer.
  • the pixel defining layer includes an opening for defining sub-pixels, and the opening exposes a part of the second electrode.
  • the organic light-emitting layer is formed on When the above-mentioned pixel defining layer is in the opening, the organic light-emitting layer is in contact with the second electrode, so that this part can drive the organic light-emitting layer to emit light.
  • the orthographic projection of the opening of the pixel defining layer on the base substrate is within the orthographic projection of the corresponding organic light emitting layer on the base substrate, that is, the organic light emitting layer covers the opening of the pixel defining layer.
  • the area of the organic light-emitting layer is larger than the area of the opening of the corresponding pixel defining layer, that is, the organic light-emitting layer includes at least the part located inside the opening of the pixel defining layer, and at least the part covering the physical structure of the pixel defining layer, usually in the pixel defining layer.
  • the physical structure of the pixel defining layer at each boundary of the opening covers the organic light-emitting layer.
  • the above description of the organic light-emitting layer pattern is based on, for example, the patterned organic light-emitting layer of each sub-pixel formed by the FMM process.
  • the FMM manufacturing process there are also some organic light-emitting layers that use the open mask process to display the entire display.
  • the area forms an integral film layer, and the orthographic projection of its shape on the base substrate is continuous, so there must be a part located in the opening of the pixel defining layer and a part located on the physical structure of the pixel defining layer.
  • Another embodiment of the present disclosure provides a display device including the display substrate shown in FIGS. 9A-11B.
  • the shape of the second electrode of the organic light-emitting element of each color sub-pixel is a hexagon.
  • the plurality of sub-pixels may be divided into a plurality of pixel unit groups 10 arranged in an array along the X direction and the Y direction.
  • Each pixel unit group 10 includes two columns of sub-pixels arranged along the Y direction, and each column of sub-pixels includes a first-color sub-pixel 110, a second-color sub-pixel 120, and a third-color sub-pixel 130.
  • the two columns of sub-pixels in each pixel unit group 10 are offset by less than one sub-pixel pitch.
  • the two columns of sub-pixels in each pixel unit group 10 are offset from each other by about half a sub-pixel pitch.
  • the sides of two adjacent sub-pixels facing each other are substantially parallel.
  • the sequence of the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels in adjacent columns is the same.
  • the first color sub-pixel is located between the second color sub-pixel and the third color sub-pixel in the adjacent column
  • the second color sub-pixel is located in the first color sub-pixel in the adjacent column.
  • the sub-pixels of the third color are located between the sub-pixels of the first color and the sub-pixels of the second color in adjacent columns.
  • one first-color sub-pixel in the first column and one second-color sub-pixel and one third-color sub-pixel adjacent to the one first-color sub-pixel in the second column Pixels constitute a pixel unit, which can realize a pixel point display.
  • the first column of sub-pixels and the second column of sub-pixels in the first pixel unit are swapped with the first column and second column of the second pixel unit,
  • the first color sub-pixel in the first pixel unit is located in the first column
  • the second color sub-pixel and the third color sub-pixel are located in the second column
  • the first color sub-pixel in the second pixel unit is located in the second column.
  • the two-color sub-pixel and the third-color sub-pixel are located in the first column.
  • the first color sub-pixel is a blue sub-pixel
  • the second color sub-pixel is a red sub-pixel
  • the third color sub-pixel is a green sub-pixel.
  • Each pixel unit includes a blue sub-pixel in a column and a One red sub-pixel and one green sub-pixel adjacent to the blue sub-pixel in the adjacent column.
  • the area of the light-emitting area of a blue sub-pixel is larger than the area of the light-emitting area of a red sub-pixel or a green sub-pixel.
  • the anode area of a blue sub-pixel is larger than the anode area of a red sub-pixel or a green sub-pixel.
  • the shape of the body electrode of the anode of the first color sub-pixel and the third color sub-pixel is approximately a regular hexagon
  • the shape of the body electrode of the anode of the second color sub-pixel is a non-regular hexagon and includes two symmetry axes .
  • the size of the axis of symmetry in the X direction is greater than the size of the axis of symmetry in the Y direction.
  • the first body electrode 1131 of the second electrode 113 of the first color sub-pixel 110 covers the driving transistor of the first color sub-pixel 110, and the second electrode 123 of the second color sub-pixel 120 is
  • the main body electrode 1231 and the driving transistor of the second color sub-pixel 120 basically do not overlap or partially overlap.
  • the third main body electrode 1331 of the second electrode 133 of the third color sub-image 130 and the driving transistor of the third color sub-pixel 130 There is no overlap.
  • the first body electrode 1131 of the first color sub-pixel 110 overlaps the scan line and the light-emitting control signal line; the second color sub-pixel 120 (such as the red sub-pixel) )
  • the second body electrode 1231 overlaps the scan line and the reset control signal line;
  • the third body electrode 1331 of the third color sub-pixel 130 for example, the green sub-pixel
  • the light-emitting control signal line the reset control of the next row of pixel circuits
  • the signal line and the reset power signal line of the pixel circuit of the next row overlap.
  • the third body electrode 1331 of the third color sub-pixel 130 overlaps the pixel driving circuit area of the first color sub-pixel (for example, the blue sub-pixel) adjacent to it in the next row.
  • the first body electrode 1131 of the first color sub-pixel 110 overlaps with a portion of the driving transistor of the adjacent third color sub-pixel 130, and the first body electrode 1131 of the first color sub-pixel 110 and its pixel circuit
  • the data lines, the shielding lines, and the data lines in the pixel circuit adjacent to the second color sub-pixel 120 all overlap.
  • the second body electrode 1231 of the second color sub-pixel 120 does not overlap with the data line in its pixel circuit, and the first power signal line in its pixel circuit and the first power signal line in the adjacent third color sub-pixel 130 in the pixel circuit.
  • a power signal line and data line are overlapped.
  • the third body electrode 1331 of the third color sub-pixel 130 overlaps with the data line and the first power signal line in the pixel circuit thereof, and overlaps with the first power signal line in the pixel circuit of the adjacent second color sub-pixel 120 There is overlap.
  • the side of the first body electrode 1131 of the first color sub-pixel 110 close to the reset control signal line of the next row is provided with a first connection electrode 1132 connected to it;
  • the side of the main body electrode 1231 close to the reset control signal line of the next row is provided with a second connection electrode 1232 connected to it;
  • the third main body electrode 1331 of the third color sub-pixel 130 is provided with a side close to its second light-emitting control transistor connected to it The third connection electrode 1332.
  • the first connection electrode 1132 of the first color sub-pixel 110 overlaps with the second electrode of the second light-emitting control transistor in the pixel circuit.
  • the second connection electrode 1232 of the second color sub-pixel 120 does not overlap with the second electrode of the second light-emitting control transistor in the pixel circuit, and the second electrode of the second light-emitting control transistor of the second color sub-pixel 120 is not overlapped with the second electrode of the second light-emitting control transistor of the second color sub-pixel 120.
  • the third body electrode 1331 of the color sub-pixel 130 overlaps.
  • the third connection electrode 1332 of the third color sub-pixel 130 overlaps with the second electrode of the second light-emitting control transistor in the pixel circuit.
  • FIG. 12 is a schematic diagram of a partial structure of an array substrate provided by another example of this embodiment.
  • the pixel circuit included in each color sub-pixel in the array substrate in this example is different from the pixel circuit shown in FIG. 10 in that the pixel circuit of the second color sub-pixel 120 in this example is The shape and relative positional relationship of the third connecting portion and the third connecting portion of the third color sub-pixel are the same.
  • the fourth connection portion 353 in the pixel circuit is connected to the connection via 354 of the third connection portion 343, which is located at the second pole of the first light-emitting control transistor T5. A side away from the first light emission control signal line EM1.
  • the fourth connection portion 353 in the pixel circuit is connected to the connection via 354 of the third connection portion 343, which is located at the second pole of the first light emission control transistor T5 near the first light emission control signal line EM1 On the side. For example, it may overlap with the first light emission control signal line EM1.
  • the second connection electrode 1232 of the second electrode 123 of the second color sub-pixel 120 is connected to the second anode connection via 1233 of the fourth connection portion 353 at the side of the via 354 close to the first light emission control signal line EM1.
  • the third connection electrode 1332 of the second electrode 133 of the third color sub-pixel 130 is connected to the third anode connection via 1333 of the fourth connection portion 353 at the side of the via 354 close to the first light emission control signal line EM1.
  • the first connection electrode 1132 of the second electrode 113 of the first color sub-pixel 110 is connected to the first anode connection via 1133 of the fourth connection portion 353 at the side of the via 354 away from the first light emission control signal line EM1 to There is a certain distance between the connecting electrode of the second electrode of the first color sub-pixel and the main body electrode of the second electrode of the third color sub-pixel, so as to prevent the two from overlapping or close to cause defects.
  • the second-color sub-pixels 120 for example, red sub-pixels
  • the third-color sub-pixels 130 for example, green sub-pixels
  • the first-color sub-pixels 110 for example, blue sub-pixels
  • the sub-pixel row formed by the second-color sub-pixel 120 and the third-color sub-pixel 130 is aligned with The sub-pixels formed by the first color sub-pixels 110 are arranged alternately in the X direction.
  • the area of the main body electrode of the second electrode of one first color sub-pixel 110 is greater than the area of the main body electrode of the second electrode of one second color sub-pixel 120, and is greater than the area of the main body electrode of the second electrode of one third color sub-pixel 130 .
  • the area of the main body electrode of the second electrode of one third color sub-pixel 130 is larger than the area of the main body electrode of the second electrode of one second color sub-pixel 120.
  • the size of the body electrode of the second electrode of one first color sub-pixel 110 in the Y direction is larger than the size of the body electrode of the second electrode of one second color sub-pixel 120 in the Y direction, and is larger than that of one third color sub-pixel 130
  • the size of the body electrode of the second electrode in the Y direction is larger than the size of the main electrode of the second electrode of one first color sub-pixel 110 in the Y direction.
  • the size of the main electrode of the second electrode of one first color sub-pixel 110 in the Y direction does not exceed the main electrode of the second electrode of one second color sub-pixel 120 and the main electrode of the second electrode of one third color sub-pixel 130.
  • the span in the Y direction that is, the body electrode of the second electrode of the first color sub-pixel 110, the body electrode of the second electrode of the second color sub-pixel 120, and the body electrode of the second electrode of the third color sub-pixel 130 are in the Y direction. Projection on a straight line, the projection of the body electrode of the second electrode of the first color sub-pixel 110 is located at the farthest of the projection of the body electrode of the second electrode of the second color sub-pixel 120 and the body electrode of the second electrode of the third color sub-pixel 130 Between two points.
  • the size of the body electrode of the second electrode of the first color sub-pixel 110 in the X direction, the size of the body electrode of the second electrode of the second color sub-pixel 120 in the X direction, and the body of the second electrode of the third color sub-pixel 130 The size of the electrodes in the X direction is approximately the same.
  • the size of the body electrode of the second electrode of the second color sub-pixel 120 in the X direction and the size of the body electrode of the second electrode of the third color sub-pixel 130 in the X direction are approximately the same, and are approximately equal to the size of one first color sub-pixel 110
  • the ratio of the dimensions of the main electrodes of the two electrodes in the X direction is 0.8 to 1.2.
  • the connecting electrode of the second electrode of the second color sub-pixel 120 and the connecting electrode of the second electrode of the third color sub-pixel 130 are both located on the side facing the second electrode body electrode of the first color sub-pixel 110.
  • the connecting electrode of the second electrode of the first color sub-pixel 110 is located between the sub-pixel row formed by the second color sub-pixel 120 and the third color sub-pixel 130 and the sub-pixel row formed by the first color sub-pixel 110, and The side closer to the second electrode of the third color sub-pixel 130 and away from the second electrode of the second color sub-pixel 120.
  • the second anode connection via 1233 of the second color sub-pixel 120 and the third anode connection via 1233 of the third color sub-pixel 130 1333 is located on a straight line extending along the Y direction, and the first anode connection via 1133 of the first color sub-pixel 110 adjacent to the second color sub-pixel 120 and the third color sub-pixel 130 is located in this straight line away from the first scan One side of the line Ga1.
  • the first anode connection via 1133 of the first color sub-pixel 110 and the connection via 354 of the second color sub-pixel 120 and the third color sub-pixel 130 are approximately located on the same line extending in the Y direction.
  • An anode connection via 1133 is located on the side of the second pole of the first emission control transistor T5 away from the first emission control signal line EM1.
  • the fourth connection part in the pixel circuit of the second color sub-pixel 120 overlaps with the drain region of the first light-emitting control transistor T5, and the second color sub-pixel 120 in the pixel circuit of the second color sub-pixel 120 overlaps with the drain region of the first light-emitting control transistor T5.
  • the shape and relative positional relationship of the four connecting parts and the fourth connecting parts of the third color sub-pixels are the same.
  • the length of the fourth connecting portion 353 in the pixel circuit of the first color sub-pixel 110 in the X direction is greater than the length of the fourth connecting portion 353 of the other two color sub-pixels in the X direction.
  • the fourth connection portion 353 in the pixel circuit of the first color sub-pixel 110 overlaps with the first emission control signal line EM1, while the fourth connection 353 of the other two color sub-pixels does not overlap the first emission control signal line EM1. Stacked.
  • the display substrate in this example includes a plurality of pixel units 1 arranged in an array along a first direction and a second direction.
  • One of the pixel units 1 includes one first color sub-pixel 110 and the same.
  • a second-color sub-pixel 120 and a third-color sub-pixel 130 are adjacent to each other.
  • the drawings schematically show the shape, size and position of the second electrode of each sub-pixel.
  • the actual light-emitting area is defined by the pixel defining layer opening.
  • the pixel defining layer has a grid-like structure covering the edge of the second electrode (for example, the anode) of each sub-pixel, and the pixel defining layer includes a plurality of openings, each of which exposes a part of the second electrode of one sub-pixel,
  • the light-emitting layer is formed at least in the plurality of openings, and a first electrode (for example, a cathode) is also formed on the side of the light-emitting layer away from the base substrate, and the first electrode and the second electrode corresponding to the corresponding opening of each sub-pixel drive light emission Layer luminescence.
  • the projection of the pixel defining layer opening of each sub-pixel on the base substrate is located within the projection of the second electrode of the sub-pixel on the base substrate, so the arrangement of the sub-pixels is consistent with the arrangement of the pixel defining layer openings.
  • the arrangement position of the electrode is one-to-one correspondence.
  • the pixel circuits of each sub-pixel are arrayed in multiple rows and multiple columns in the X and Y directions, and the pixel circuit structure of each sub-pixel can be roughly the same except for the size of the driving transistor and the structure of the connecting electrode, such as data lines and power supplies.
  • the pixel circuits of each sub-pixel are arranged in the order of the pixel circuits of the first color sub-pixels, the pixel circuits of the second color sub-pixels, and the pixel circuits of the third color sub-pixels.
  • each row The pixel circuits of the sub-pixels are repeatedly arranged.

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Abstract

一种显示基板以及显示装置。显示基板包括第一颜色子像素、第二颜色子像素和第三颜色子像素；发光控制信号线、数据线以及电源线，电源线与数据线交叠。子像素包括有机发光元件和像素电路，有机发光元件包括第二电极，像素电路包括驱动晶体管和第一发光控制晶体管，像素电路还包括连接结构，第二颜色子像素中，第一发光控制晶体管的一极通过第一连接孔与连接结构电连接，连接结构通过第二连接孔与第二电极电连接，第一连接孔的至少部分和第二连接孔的至少部分分别位于发光控制信号线的两侧；第三颜色子像素中，第二电极与驱动晶体管的沟道没有交叠。本公开在提高像素排列紧凑程度的基础上，通过连接结构有效驱动第二颜色子像素发光。

Description

显示基板以及显示装置
本申请要求于2019年11月29日递交的PCT国际申请第PCT/CN2019/122129号的优先权，在此全文引用上述PCT国际申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一个实施例涉及一种显示基板以及显示装置。
背景技术
有机发光二极管具有自发光、高效率、色彩鲜艳、轻薄省电、可卷曲以及使用温度范围宽等优点，已经逐步应用于大面积显示、照明以及车载显示等领域。
发明内容
本公开的至少一实施例提供一种显示基板以及显示装置。显示基板，包括：衬底基板以及设置在所述衬底基板上的多个第一颜色子像素、多个第二颜色子像素和多个第三颜色子像素；发光控制信号线，沿第一方向延伸；数据线，沿第二方向延伸，所述第一方向与所述第二方向相交；以及电源线，所述电源线在垂直于所述衬底基板的第三方向上与所述数据线交叠。至少一个所述子像素包括有机发光元件和驱动所述有机发光元件的像素电路，所述有机发光元件包括第一电极、第二电极和设置在所述第一电极和所述第二电极之间的发光层，所述像素电路包括驱动晶体管和第一发光控制晶体管，所述像素电路还包括与所述数据线同层设置的连接结构，至少一个所述第二颜色子像素中，所述第二颜色子像素的所述第一发光控制晶体管的第一极通过第一连接孔与所述连接结构电连接，所述连接结构通过第二连接孔与所述第二颜色子像素的第二电极电连接，所述第一连接孔的至少部分在所述衬底基板上的正投影位于所述发光控制信号线在所述衬底基板上的正投影的一侧，所述第二连接孔的至少部分在所述衬底基板上的正投影位于所述发光控制信号线在衬底基板的上正投影的另一侧；在至少一个所述第三颜色子像素中，所述第三颜色子像素的所述第二电极在所述第三方向上与控制所述第三颜色子像素的有机发光元件的所述驱动晶体管的沟道没有交叠。
例如，在本公开至少一实施例中，至少一个所述第三颜色子像素的所述第二电极在所述第三方向上与控制其他颜色子像素的有机发光元件的所述驱动晶体管的沟道均没有交叠。
例如，在本公开至少一实施例中，所述显示基板包括有源半导体层，所述有源半导体层包括各子像素的各晶体管的沟道和源漏区，所述连接结构通过位于所述连接结构与所述有源半导体层之间的无机层中的所述第一连接孔与所述有源半导体层电连接；所述连接结构通过位于所述连接结构和所述第二电极之间的有机层和无机层至少之一中的所述第二连接孔与所述第二电极电连接，所述第二颜色子像素中，所述第一连接孔在所述 衬底基板上的正投影的中心和所述第二连接孔在所述衬底基板上的正投影的中心分别位于所述发光控制信号线在所述衬底基板上的正投影的两侧。
例如，在本公开至少一实施例中，在至少一个所述第二颜色子像素中，所述第二颜色子像素的所述第一连接孔在所述衬底基板上正投影相较于所述第二颜色子像素的所述第二连接孔在所述衬底基板上正投影远离所述第二颜色子像素的所述第二电极在所述衬底基板上的正投影。
例如，在本公开至少一实施例中，在至少一个所述第二颜色子像素中，所述第二颜色子像素的所述第二电极在所述第三方向上与驱动所述第二颜色子像素的有机发光元件的所述驱动晶体管的沟道交叠。
例如，在本公开至少一实施例中，至少一个所述第二颜色子像素的所述像素电路连接的所述数据线和所述第二颜色子像素的所述第二电极在所述第一方向上彼此间隔。
例如，在本公开至少一实施例中，至少一个所述第二颜色子像素的所述第二电极和与所述第三颜色子像素的像素电路连接的所述数据线在所述第三方向上交叠。
例如，在本公开至少一实施例中，至少一个所述第一颜色子像素的所述第二电极和至少一个所述第三颜色子像素的所述第二电极在沿所述第二方向延伸的第一直线上的正投影均与至少一个所述第二颜色子像素的所述连接结构在所述第一直线上的正投影交叠。
例如，在本公开至少一实施例中，至少一个所述第三颜色子像素的所述第二电极在沿所述第一方向延伸的第二直线上的正投影与至少一个所述第二颜色子像素的所述连接结构在所述第二直线上的正投影交叠。
例如，在本公开至少一实施例中，至少一个所述子像素的所述第二电极包括主体电极和连接电极，所述连接电极与所述第一发光控制晶体管电连接，至少一个所述第一颜色子像素的所述主体电极在所述第一直线上的正投影与至少一个所述第二颜色子像素的所述连接结构在所述第一直线上的正投影交叠。
例如，在本公开至少一实施例中，至少一个所述第三颜色子像素的所述主体电极在所述第二直线上的正投影与至少一个所述第二颜色子像素的所述连接结构在所述第二直线上的正投影交叠。
例如，在本公开至少一实施例中，显示基板还包括：扫描信号线和复位电源信号线。在至少一个所述子像素中，所述像素电路还包括数据写入晶体管和复位晶体管，所述数据写入晶体管的栅极被配置为与所述扫描信号线电连接以接收扫描信号，所述复位晶体管的栅极被配置为与所述复位电源信号线电连接以接收复位控制信号。
例如，在本公开至少一实施例中，在至少一个所述子像素中，所述像素电路还包括第二发光控制晶体管，所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的的栅极均与所述发光控制信号线电连接以接收发光控制信号。
例如，在本公开至少一实施例中，至少一个所述第二颜色子像素的所述第二电极在所述第三方向上与所述扫描信号线交叠。
例如，在本公开至少一实施例中，至少一个所述第二颜色子像素的所述第二电极在所述第三方向上和与该第二颜色子像素的所述像素电路电连接的所述扫描信号线交叠。
例如，在本公开至少一实施例中，至少一个所述第一颜色子像素的所述第二电极和至少一个所述第三颜色子像素的所述第二电极在所述第三方向上均与所述发光控制信号线交叠。
例如，在本公开至少一实施例中，至少一个所述第一颜色子像素的所述第二电极包括分别位于所述发光控制信号线两侧的第一电极子部和第二电极子部，所述第一电极子部的面积大于所述第二电极子部的面积；至少一个所述第一颜色子像素中，所述第二连接孔在所述衬底基板上的正投影的中心和所述第一电极子部在所述衬底基板上的正投影分别位于所述发光控制信号线在所述衬底基板上的正投影的两侧。
例如，在本公开至少一实施例中，在至少一个所述子像素中，所述像素电路还包括存储电容，所述存储电容的第二极复用为所述驱动晶体管的栅极，至少一个所述第一颜色子像素的所述存储电容的第二极的面积与至少一个所述第二颜色子像素的所述存储电容的第二极的面积不同。
例如，在本公开至少一实施例中，至少一个所述第一颜色子像素的所述第二电极的面积大于至少一个所述第二颜色子像素的所述第二电极的面积，且至少一个所述第一颜色子像素的所述存储电容的第二极的面积大于至少一个所述第二颜色子像素的所述存储电容的第二极的面积。
例如，在本公开至少一实施例中，至少一个所述第二颜色子像素中，所述存储电容的第一极在所述第三方向上与所述连接结构交叠。
例如，在本公开至少一实施例中，在至少一个子像素中，所述子像素的所述驱动晶体管的沟道包括依次连接的多个沟道子部，所述多个沟道子部中的至少部分沿所述第一方向延伸，且沿所述第一方向延伸的两个沟道子部在所述第二直线上的正投影没有交叠。
例如，在本公开至少一实施例中，所述多个沟道子部包括依次连接的五个沟道子部，所述五个沟道子部中的三个沟道子部沿所述第一方向延伸，所述三个沟道子部中的两个沟道子部在所述第二直线上的正投影没有交叠，在所述第一直线上的正投影交叠，所述五个沟道子部中除所述三个沟道子部外的两个沟道子部在所述第一直线上的正投影交叠。
例如，在本公开至少一实施例中，所述五个沟道子部包括依次连接的第一沟道子部、第二沟道子部、第三沟道子部、第四沟道子部以及第五沟道子部，所述第一沟道子部、所述第三沟道子部以及所述第五沟道子部沿所述第一方向延伸，所述第一沟道子部与所述第三沟道子部彼此平行，所述第一沟道子部和所述第五沟道子部被沿所述第一方向延伸的第三直线穿过且在所述第二直线上的正投影没有交叠，所述第二沟道子部和所述第四沟道子部沿所述第二方向延伸且彼此平行。
例如，在本公开至少一实施例中，显示基板还包括：位于各所述子像素的所述第二电极远离所述衬底基板一侧的像素限定层，其中，所述像素限定层包括用于限定各子像 素的发光区的开口，各所述子像素的所述有机发光层的至少部分位于所述开口内，所述像素限定层的开口在所述衬底基板上的正投影位于各所述子像素的所述第二电极的所述主体电极在所述衬底基板上的正投影内；所述像素限定层中，限定各所述第三颜色子像素的发光区的开口的面积大于限定各所述第二颜色子像素的发光区的开口的面积，且小于限定各所述第一颜色子像素的发光区的开口的面积。
例如，在本公开至少一实施例中，至少一个所述第一颜色子像素的所述第二电极在所述第三方向上与所述数据线交叠，且交叠部分沿所述第二方向的长度大于所述第二电极沿所述第二方向的最大长度的80％。
例如，在本公开至少一实施例中，至少一个所述第一颜色子像素的所述第二电极在所述第三方向上与所述电源线交叠，且交叠部分沿所述第二方向的长度大于所述第二电极沿所述第二方向的最大长度的80％。
例如，在本公开至少一实施例中，在至少一个所述第二颜色子像素中，所述第一连接孔在所述衬底基板上的正投影具有第一面积，所述第二连接孔在所述衬底基板上的正投影具有第二面积，所述第一面积和所述第二面积不同。
例如，在本公开至少一实施例中，在至少一个所述第二颜色子像素中，所述第一连接孔在所述第二方向上到所述发光控制信号线具有第一距离，所述第二连接孔在所述第二方向上到所述发光控制信号线具有第二距离，所述第一距离和所述第二距离不同。
本公开另一实施例提供一种显示装置，包括上述显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为根据本公开实施例提供的阵列基板的平面示意图；
图1B为图1A所示的阵列基板沿AA线所截的部分截面示意图；
图1C为根据本公开实施例提供的阵列基板的平面示意图；
图1D和图1E分别为第一颜色子像素和第二颜色子像素的驱动晶体管的示意性平面图；
图2为根据本公开实施例提供的阵列基板的制作方法的示意性流程图；
图3为本公开实施例的第二示例中给各颜色子像素输入的数据信号与流过各颜色子像素的有机发光元件的饱和电流的仿真曲线图；
图4为本公开一实施例中沟道宽长比不同的驱动晶体管的栅极电压与饱和电流的曲线图；
图5A-图5C分别为各颜色子像素中驱动晶体管的沟道宽长比与充电率的关系图；
图6为根据本公开实施例提供的显示基板的示意性框图；
图7为根据本公开实施例提供的显示基板的重复单元的示意图；
图8为根据本公开实施例提供的一种显示基板的平面示意图；
图9A-10A为本公开一些实施例提供的一种像素电路的各层的示意图；
图10B和图10C分别为沿图10A所示的AA’线和BB’线所截的截面示意图；
图11A为本公开一实施例的一示例提供的阵列基板的局部结构示意图；
图11B为图11A所示的像素的排列结构示意图；以及
图12为本实施例的另一示例提供的阵列基板的局部结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
本公开的至少一实施例提供一种显示基板以及显示装置。显示基板，包括：衬底基板以及设置在衬底基板上的多个第一颜色子像素、多个第二颜色子像素和多个第三颜色子像素；发光控制信号线，沿第一方向延伸；数据线，沿第二方向延伸，第一方向与第二方向相交；以及电源线，电源线在垂直于衬底基板的第三方向上与数据线交叠。至少一个子像素包括有机发光元件和驱动有机发光元件的像素电路，有机发光元件包括第一电极、第二电极和设置在第一电极和第二电极之间的发光层，像素电路包括驱动晶体管和第一发光控制晶体管，像素电路还包括与数据线同层设置的连接结构，至少一个第二颜色子像素中，第二颜色子像素的第一发光控制晶体管的第一极通过第一连接孔与连接结构电连接，连接结构通过第二连接孔与第二颜色子像素的第二电极电连接，第一连接孔的至少部分在衬底基板上的正投影位于发光控制信号线在衬底基板上的正投影的一侧，第二连接孔的至少部分在衬底基板上的正投影位于发光控制信号线在衬底基板的上正投影的另一侧；在至少一个第三颜色子像素中，第三颜色子像素的第二电极在第三方向上与控制第三颜色子像素的有机发光元件的驱动晶体管的沟道没有交叠。本公开提供一种像素排列结构，该像素排列结构中通过对两个连接孔与发光控制信号线的位置关系的设置以及第三颜色子像素的第二电极与驱动晶体管的沟道位置关系的设置可以在提高像素排列紧凑程度以提高像素分辨率的基础上，通过连接结构有效驱动第二颜色子像素发光。本公开通过设置不同层的数据线与电源线，即双层信号线，可以实现像素的紧密排布以及优化布线方式。
下面结合附图对本公开实施例提供的显示基板以及显示装置进行描述。
图1A为根据本公开实施例提供的阵列基板的平面示意图，图1B为图1A所示的阵列基板沿AA线所截的部分截面示意图。如图1A所示，本公开实施例提供一种阵列基板，包括衬底基板100以及位于衬底基板100上的第一颜色子像素110和第二颜色子像素120。第一颜色子像素110包括第一驱动晶体管111，第二颜色子像素120包括第二驱动晶体管121，且第一驱动晶体管111的沟道宽长比W1/L1大于第二驱动晶体管121的沟道宽长比W2/L2。也就是，第一驱动晶体管111的沟道宽度为W1，沟道长度为L1，第二驱动晶体管121的沟道宽度为W2，沟道长度为L2，且W1/L1>W2/L2。图1A示意性的示出第一驱动晶体管和第二驱动晶体管的沟道长度相同，但沟道宽度不同。本公开实施例不限于此，还可以是第一驱动晶体管和第二驱动晶体管的沟道宽度相同，但沟道长度不同，或者第一驱动晶体管和第二驱动晶体管的沟道宽度和沟道长度均不同。
本公开实施例通过优化阵列基板上的不同颜色子像素的驱动晶体管的沟道宽长比，可以提高包括该阵列基板的显示装置的亮度。
在一些示例中，第一颜色子像素的电流效率小于第二颜色子像素的电流效率。这里的电流效率指各颜色子像素在单位电流下的发光强度(单位为坎德拉每安培，cd/A)。由于不同颜色子像素的电流效率存在差异，由此，通过将不同颜色子像素的驱动晶体管的沟道宽长比设置的不同，可以防止包括该阵列基板的显示装置显示的白光处于最高灰阶时，出现第一颜色光亮度不足的现象。
在一些示例中，第一颜色子像素110为蓝色子像素，第二颜色子像素120为红色子像素或者绿色子像素。本公开实施例通过将蓝色子像素的驱动晶体管的沟道宽长比设置为大于红色子像素或者绿色子像素的驱动晶体管的沟道宽长比，可以防止包括该阵列基板的显示装置显示的白光处于最高灰阶时，出现蓝光亮度不足的现象，从而导致最高灰阶的白光的白平衡色坐标偏移设计值。
上述的白平衡(white balance)指白色的平衡，即显示装置显示的红、绿、蓝三基色混合后形成的白光精确度的一项指标。
例如，第一颜色子像素110还可以为蓝色子像素，第二颜色子像素120还可以为黄色子像素。
例如，图1C为根据本公开实施例提供的阵列基板的平面示意图。如图1C所示，阵列基板还可以包括第三颜色子像素130，第三颜色子像素130包括第三驱动晶体管131。
例如，第一颜色子像素110为蓝色子像素，第二颜色子像素120为红色子像素，第三颜色子像素130为绿色子像素。
例如，红色子像素的第二驱动晶体管121的沟道宽长比可以与绿色子像素的第三驱动晶体管131的沟道宽长比相同，以方便制作。但不限于此，也可以根据显示装置实现高亮度显示时的各颜色光的亮度需求调节红色子像素和绿色子像素的驱动晶体管的沟道宽长比。
在一些示例中，红色子像素、绿色子像素以及蓝色子像素的驱动晶体管的沟道宽长比的比值大致为1:(0.7～1.3):(1.5～2.5)，从而可以使显示装置显示白光的亮度为800 尼特甚至1000尼特时，不会出现蓝光亮度不足的现象。
在一些示例中，红色子像素、绿色子像素以及蓝色子像素的驱动晶体管的沟道宽长比的比值可以为1:1:2，以方便实际工艺制作。
在一些示例中，图1D和图1E分别为第一颜色子像素和第二颜色子像素的驱动晶体管的示意性平面图。如图1D和图1E所示，第一颜色子像素110的第一驱动晶体管111的有源层与栅极114重叠的部分为其沟道，该第一驱动晶体管111的沟道宽长比W1/L1可以为5/25。第二颜色子像素120的第二驱动晶体管121与栅极124重叠的部分为其沟道，该第二驱动晶体管121的沟道宽长比W2/L2可以为3/30。例如，如图1D所示，第一驱动晶体管111的有源层与栅极114的沿X方向延伸的边缘交叠部分的中心点分别为O和O’，第一驱动晶体管111的有源层与栅极114重叠部分的中心线C1从O延伸到O’。则上述沟道宽长比中的“长”指中心线C1的长度L1，沟道宽长比中的“宽”指第一驱动晶体管111与栅极114的沿X方向延伸的边缘交叠的部分的尺寸。同理，如图1E所示，第二驱动晶体管121的沟道宽长比中的“长”指其中心线C2的长度L2，沟道宽长比中的“宽”指第二驱动晶体管121的有源层与栅极124的沿X方向延伸的边缘交叠的部分的尺寸。
例如，如图1E所示，在至少一个像素单元中，各子像素中的驱动晶体管T1的沟道包括依次连接的多个沟道子部，多个沟道子部中的至少部分沿第一方向延伸，且沿第一方向延伸的两个沟道子部在沿第一方向延伸的第二直线上的正投影没有交叠。
例如，如图1E所示，多个沟道子部包括依次连接的五个沟道子部T1c-1、T1c-2、T1c-3、T1c-4以及T1c-5，三个沟道子部T1c-1、T1c-3以及T1c-5沿第一方向延伸，两个沟道子部T1c-2和T1c-4在沿第二方向延伸的第一直线上的正投影交叠，三个沟道子部T1c-1、T1c-3以及T1c-5中的两个沟道子部T1c-1和T1c-5在第二直线上的正投影没有交叠，且在第一直线上的正投影交叠。
例如，如图1E所示，五个沟道子部T1c-1、T1c-2、T1c-3、T1c-4以及T1c-5包括依次连接的第一沟道子部T1c-1、第二沟道子部T1c-2、第三沟道子部T1c-3、第四沟道子部T1c-4以及第五沟道子部T1c-5，第一沟道子部T1c-1、第三沟道子部T1c-3以及第五沟道子部T1c-5沿第一方向延伸，第一沟道子部T1c-1与第三沟道子部T1c-3彼此平行，第一沟道子部T1c-1和第五沟道子部T1c-5被沿第一方向延伸的第三直线穿过且在第二直线上的正投影没有交叠，第二沟道子部T1c-2和第四沟道子部T1c-4彼此平行。
例如，如图1D所示，在沟道的宽度较大时，驱动晶体管T1的沟道包括依次连接的三个沟道子部，这三个沟道子部均沿第一方向延伸，且形成类似“n”形的沟道形状。
例如，如图1D和图1E所示，蓝色子像素的驱动晶体管的沟道宽长比可以为5/25，绿色子像素和红色子像素的沟道宽长比可以均为3/30。
本公开实施例对各颜色子像素的驱动晶体管的具体沟道宽长比不作限制，只要各颜色子像素的驱动晶体管的沟道宽长比的比值满足上述比值范围即可。
在一些示例中，阵列基板中各颜色子像素包括有机发光元件，有机发光元件发光层 以及位于有机发光层两侧的第一电极和第二电极，第一电极和第二电极之一与驱动晶体管连接，即，本公开实施例中的阵列基板为应用于有机发光二极管显示装置中的阵列基板。
例如，如图1A和图1B所示，第一颜色子像素110包括第一有机发光层112、位于第一有机发光层112远离衬底基板100一侧的第一电极114以及位于第一有机发光层112面向衬底基板100一侧的第二电极113，且第二电极113与第一驱动晶体管111的源极和漏极之一连接。第二颜色子像素120包括第二有机发光层122、位于第二有机发光层122远离衬底基板100一侧的第一电极124以及位于第二有机发光层122面向衬底基板100一侧的第二电极123，且第二电极123与第二驱动晶体管121的源极和漏极之一连接。图1B所示的不同颜色子像素的第一电极可以为公共电极，不同颜色子像素的第一电极可以为同层同材料制作以节省工艺。
例如，如图1C所示，第三颜色子像素130中的有机发光元件的第二电极133与第三驱动晶体管131的源极和漏极之一连接。
例如，如图1B所示，阵列基板还包括位于相邻有机发光层之间的像素限定层101以及位于第二电极与驱动晶体管之间的平坦层102。
例如，各颜色子像素的第一电极可以为阴极，阴极作为各颜色子像素负向电压的连接电极，具有较好的导电性能和较低的功函数值，本实施例包括但不限于此。各颜色子像素的第二电极可以为阳极，阳极作为各颜色子像素正向电压的连接电极，具有较好的导电性能以及较高的功函数值，本实施例包括但不限于此。
例如，本公开实施例中各颜色子像素的驱动晶体管可以选用低温多晶硅(LTPS)薄膜晶体管，对于包括低温多晶硅薄膜晶体管的子像素，流过有机发光元件的饱和电流I满足如下关系：
I＝K1*(W/L)*(Vgs-Vth) 2，                               (1)
上述关系式(1)中，W和L分别为驱动晶体管的沟道宽度和沟道长度，K1与驱动晶体管的沟道迁移率和单位面积沟道电容有关，Vgs以及Vth分别为驱动晶体管的栅源极间电压以及阈值电压，K1为由各驱动晶体管的沟道的特性决定的系数，例如沟道迁移率等。
上述饱和电流I与子像素的亮度Y以及电流效率E满足如下关系：
I＝(Y*S)/E，                                            (2)
由上述关系式(1)和关系式(2)可以得到：
I＝(Y*S)/E＝K1*(W/L)*(Vgs-Vth) 2，                        (3)
根据关系式(3)可以得到各颜色子像素的驱动晶体管的沟道宽长比满足如下关系：
W/L＝K2*(Y/E)，                                       (4)
K2为涉及K1、(Vgs-Vth) 2以及S的系数。由此，第一颜色子像素的第一驱动晶体管的沟道宽长比、第二颜色子像素的第二驱动晶体管的沟道宽长比以及第三颜色子像素的第三驱动晶体管均满足上述关系式(4)。
上述关系式(2-4)中，S为阵列基板包括的有效显示区的面积。在包括本公开实施例提供的阵列基板的显示装置中，S为显示装置的显示屏的有效显示区的面积。本公开实施例中以上述Y为在各颜色子像素满足混合形成的白光处于白平衡时，各颜色子像素的亮度。
例如，本公开实施例可以Y为在各颜色子像素满足混合形成的白光处于最高灰阶时，各颜色子像素经过显示屏后用于显示的最大亮度为例进行描述。例如，Y可以为有机发光元件发出的光经过显示屏幕后的显示亮度。例如，因包括上述阵列基板的显示装置的显示侧通常有圆偏光片，触摸屏等，显示屏幕对白光的整体透过率T一般为0.4左右，不同颜色光的整体透过率会略有不同，为便于计算，本实施例取屏幕对白光、红光、绿光和蓝光的整体透过率均为0.42，本实施例包括但不限于此。
例如，根据上述关系式(4)，阵列基板包括的红色子像素、绿色子像素以及蓝色子像素中的驱动晶体管的沟道宽长比满足如下比例关系式(5)：
(W/L) R：(W/L) G：(W/L) B＝[K2 R*(Y [R]/E R)]:[K2 G*(Y [G]/E G)]:
[K2 B*(Y [B]/E B)]。
例如，若不考虑工艺过程中造成的均一性差异，各颜色子像素中的驱动晶体管的沟道迁移率和单位面积沟道电容均为相同的值。
若考虑Vth补偿，例如对于驱动晶体管而言，栅极与源极之间的电压差Vgs＝Vdata+Vth-Vdd，驱动晶体管处于饱和状态，为有机发光元件充电，所输出饱和电流I为：
I＝K1*(W/L)*(Vgs-Vth) 2
＝K1*(W/L)*(Vdata+Vth–Vdd-Vth) 2
＝K1*(W/L)*(Vdata-Vdd) 2                               (6)
上述Vdata为输入包括驱动晶体管的子像素的数据信号，Vdd为输入驱动晶体管的电源电压。对于每个子像素，在电源电压Vdd不变的情况下，驱动电流I的大小和数据信号Vdata(即显示数据电压)直接相关。当数据信号Vdata等于电源电压Vdd的情况下，驱动晶体管的输出电流I为零，也即没有电流流过有机发光元件，此时，包括该有机发光元件的子像素不发光，即显示黑；当数据信号Vdata不等于电源电压Vdd的情况下，驱动晶体管的输出电流I不为零，也即有电流流过有机发光元件，此时，包括该有机发光元件的子像素发光。并且数据信号Vdata与电源电压Vdd的差值越大，则输出电流I越大，相应的子像素显示的灰阶越高，子像素的亮度越大。
考虑到实际工艺中造成的均一性差异，可以在通过关系式(5)和关系式(6)计算得到各颜色子像素的驱动晶体管沟道宽长比之间的比值后，对该比值进行一定范围的调整以满足工艺制程。例如，在通过上述比例关系计算得到各颜色子像素的驱动晶体管沟道宽长比之间的比值为1:0.97:2.03时，可以考虑为了便于设计和生产过程的实现，将上述比值调整为1:1:2。
例如，图2为根据本公开实施例提供的阵列基板的制作方法的示意性流程图。如图2所示，根据本公开实施例提供的制作各颜色子像素的驱动晶体管的方法包括如下步骤。
S101：获取包括阵列基板的显示装置的光学参数，并根据光学参数计算各颜色子像素的预设亮度。
在一些示例中，阵列基板可以包括三种颜色子像素，即蓝色子像素(第一颜色像素)、红色子像素(第二颜色子像素)以及绿色子像素(第三颜色子像素)。蓝色子像素发出的蓝光的物体色三刺激值为(X [B]，Y [B]，Z [B])，绿色子像素发出的绿光的物体色三刺激值为(X [G]，Y [G]，Z [G])，红色子像素发出的红光的物体色三刺激值为(X [R]，Y [R]，Z [R])，蓝光、绿光以及红光混合形成的白光的物体色三刺激值为(X [W]，Y [W]，Z [W])。这里的物体色三刺激值指匹配物体反射色光所需要红、绿、蓝三原色(这里的三原色不是物理上的真实色，而是虚构的假想色)的数量，也指物体色的色度值。物体色指眼睛看到的物体的颜色，也就是光被物体反射或透射后的颜色。
例如，上述各颜色子像素的物体色三刺激值X、Y以及Z分别满足：
Figure PCTCN2020132144-appb-000001
上述关系式(7)中的Ф(λ)表示波长为λ的光的发射频谱与波长的函数，上述
Figure PCTCN2020132144-appb-000002
Figure PCTCN2020132144-appb-000003
以及
Figure PCTCN2020132144-appb-000004
分别表示光谱三刺激值，又称为CIE1931标准色度观察者光谱三刺激值。需要说明的是，上述各颜色光三刺激值中的Y可以表示待配色色光的亮度在满足显示装置混合形成的白光处于白平衡状态下能够达到的最大亮度。因此，Y [B]、Y [G]、Y [R]以及Y [W]可以分别为白光为白平衡状态下的蓝光、绿光、红光以及白光的最大亮度，该最大亮度也为本公开实施例中各颜色光的预设亮度。
例如，各颜色光的色坐标中心值为(x,y,z)，且各颜色光的色坐标中心值与物体色三刺激值满足如下关系：
x＝X/(X+Y+Z)，
y＝Y/(X+Y+Z)，
z＝Z/(X+Y+Z)，                                             (8)
根据上述关系式(8)可以得到，x+y+z＝1。                     (9)
根据上述色坐标与物体色的色度值之间的关系，可以在获得各颜色子像素的预设色坐标后，得到物体色的色度值中三个参量的比例关系。
例如，根据加法混色理论，红光、绿光以及蓝光混合形成的白光的物体色的色度值与三种光的物体色的色度值满足如下关系：
X [W]＝X [B]+X [G]+X [R]，
Y [W]＝Y [B]+Y [G]+Y [R]，
Z [W]＝Z [B]+Z [G]+Z [R]。                                      (10)
上式写成矩阵形式为：
Figure PCTCN2020132144-appb-000005
上述红光、绿光以及蓝光的最大亮度Y [R]、Y [G]以及Y [B]可用逆矩阵求出：
Figure PCTCN2020132144-appb-000006
由此，红光、绿光以及蓝光分别占白光的比例为：Y [R]/Y [W]，Y [G]/Y [W]，Y [B]/Y [W]。
在一些示例中，在设计不同颜色子像素的驱动晶体管的沟道宽长比之间的比例时，需要考虑该阵列基板应用于有机发光二极管显示装置后的光学参数。
在一些示例中，光学参数可以包括该有机发光二极管显示装置发出的白光的目标亮度(预设亮度，例如可以为经过显示屏以后的最大亮度)、白光的目标白平衡坐标(预设白平衡坐标)以及各颜色子像素的目标色坐标中心值(预设色坐标)，例如第一颜色子像素、第二颜色子像素以及第三颜色子像素的预设色坐标。
例如，根据光学参数计算各颜色子像素的预设亮度包括：根据白光的预设白平衡坐标以及白光的预设亮度得到白光的物体色的色度值(X [W]，Y [W]，Z [W])；根据矩阵关系式(12)以及各颜色子像素的预设色坐标可以计算得到各颜色子像素的预设亮度。
例如，在本公开实施例的第一个示例中，白光的预设亮度可以设为800尼特，白光的预设白平衡坐标可以为(0.30,0.32)。由于白光的物体色的色度值中的Y为800，根据关系式(8-9)可以得出白光的物体色的色度值为(750,800,950)。
例如，红色子像素的预设色坐标的中心值可以为(0.685,0.315)，绿色子像素的预设色坐标的中心值可以为(0.252,0.718)，蓝色子像素的预设色坐标的中心值可以为(0.135,0.05)。本公开实施例对此不作限制，可以根据具体需求进行选取。
根据上述关系式(8-10)以及关系式(12)可得：
Figure PCTCN2020132144-appb-000007
根据上述计算过程可以计算得到各颜色子像素的预设亮度(即为经过显示屏幕以后的最大亮度)，红色子像素的预设亮度为184.1尼特，绿色子像素的预设亮度为559.1尼特，蓝色子像素的预设亮度为56.8尼特。上述计算中的白光的预设亮度800尼特为考虑了包括阵列基板的显示装置的显示屏的整体透过率的最大亮度，因此，各颜色子像素的 预设亮度也为考虑了显示屏的整体透过率的最大亮度。
例如，在本公开实施例的第二个示例中，白光的预设亮度可以设为800尼特，白光的预设白平衡坐标可以为(0.307,0.321)，则白光的物体色的色度值为(765.1,800,927.1)。
例如，红色子像素的预设色坐标的中心值可以为(0.697,0.303)，绿色子像素的预设色坐标的中心值可以为(0.290,0.68)，蓝色子像素的预设色坐标的中心值可以为(0.132,0.062)。根据上述关系式(8-10)以及关系式(12)可得红色子像素的预设亮度为163.2尼特，绿色子像素的预设亮度为567.4尼特，蓝色子像素的预设亮度为69.4尼特。
例如，在本公开实施例的第三个示例中，白光的预设亮度可以设为1000尼特，白光的预设白平衡坐标可以为(0.307,0.321)，则白光的物体色的色度值为(956.4,1000,1158.9)。
例如，红色子像素的预设色坐标的中心值可以为(0.698,0.302)，绿色子像素的预设色坐标的中心值可以为(0.298,0.662)，蓝色子像素的预设色坐标的中心值可以为(0.137,0.062)。根据上述关系式(8-10)以及关系式(12)可得红色子像素的预设亮度为190.4尼特，绿色子像素的预设亮度为723.3尼特，蓝色子像素的预设亮度为86.3尼特。
S102：获取各颜色子像素的预设电流效率。
例如，各颜色子像素的电流效率可通过光学测试设备和电学测试设备直接测出来。光学测试设备例如可以为分光光度计PR788，电学测试设备例如可以为数字源表Keithley2400。在设计不同颜色子像素的驱动晶体管的沟道宽长比的过程中，可以根据对一般显示装置中各颜色子像素测得的电流效率而获取所需的预设电流效率。根据不同颜色子像素的有机发光元件的材料的不同，各有机发光元件的预设电流效率也不同。
例如，在上述第一个示例中，红色子像素、绿色子像素以及蓝色子像素的电流效率分别为48cd/A、118cd/A以及7.2cd/A。
例如，以包括本公开实施例的阵列基板的显示装置的有效显示区的面积为0.031981平方米为例，根据上述关系式(3)可得红色子像素、绿色子像素以及蓝色子像素所需要的电流分别为292毫安、361毫安以及601毫安。需要说明的是，在计算电流时采用的亮度为考虑屏幕整体透过率的亮度，本公开实施例以显示屏的整体透过率为42％，则红色子像素的用于计算电流的亮度为438.3尼特，绿色子像素的用于计算电流的亮度为1331.2尼特，蓝色子像素的用于计算电流的亮度为135.2尼特。
根据上述参数可知，如果各颜色子像素的驱动晶体管采用相同的沟道宽长比，则需要给蓝色子像素提供的电流为需要给红色子像素提供的电流的2.06倍，需要给蓝色子像素提供的电流为需要给绿色子像素提供的电流的1.67倍。由此，蓝色子像素的驱动晶体管可能由于驱动能力不足而无法提供如此大的电流，从而导致显示装置的蓝光的亮度不足，进而影响白光的白平衡。
例如，在上述第二个示例中，红色子像素、绿色子像素以及蓝色子像素的电流效率分别为24cd/A、98cd/A以及5.8cd/A。
例如，以包括上述阵列基板的显示装置的有效显示区的面积为0.031981平方米为例，根据上述关系式(3)可得红色子像素、绿色子像素以及蓝色子像素的所需要的电流分别 为518毫安、441毫安以及911毫安。
根据上述参数可知，如果各颜色子像素的驱动晶体管采用相同的沟道宽长比，则需要给蓝色子像素提供的电流分别为需要给红色子像素和绿色子像素提供的电流的1.76和2.06倍。由此，蓝色子像素的驱动晶体管可能由于驱动能力不足而无法提供如此大的电流，从而导致显示装置的蓝光的亮度不足，进而影响白光的白平衡。
例如，在上述第三个示例中，红色子像素、绿色子像素以及蓝色子像素的电流效率分别为30cd/A、118cd/A以及8cd/A。
例如，以包括上述阵列基板的显示装置的有效显示区的面积为0.031981平方米为例，根据上述关系式(3)可得红色子像素、绿色子像素以及蓝色子像素的所需要的电流分别为483毫安、467毫安以及821毫安。
根据上述参数可知，如果各颜色子像素的驱动晶体管采用相同的沟道宽长比，则需要给蓝色子像素提供的电流分别为需要给红色子像素和绿色子像素提供的电流的1.7和1.76倍。由此，蓝色子像素的驱动晶体管可能由于驱动能力不足而无法提供如此大的电流，从而导致显示装置的蓝光的亮度不足，进而影响白光的白平衡。
本公开实施例可以通过将蓝色子像素的驱动晶体管的沟道宽长比设计的比其他颜色子像素的驱动晶体管的沟道宽长比大，以使得蓝色子像素的驱动晶体管能够提供蓝色子像素最大亮度或最高灰阶所需要的电流值，从而使得在保证显示装置的白光处于预设的白平衡色坐标状态下，白光的亮度能够达到800尼特或以上。
S103：根据各颜色子像素的预设亮度和预设电流效率计算各颜色子像素的驱动晶体管的沟道宽长比的比值。
例如，第一颜色子像素和第二颜色子像素的预设电流效率分别为E1和E2，第一颜色子像素和第二颜色子像素的预设亮度分别为Y1和Y2，根据第一颜色子像素和第二颜色子像素的预设亮度和预设电流效率计算第一驱动晶体管的沟道宽长比与第二驱动晶体管的沟道宽长比的比值包括：
设定第一驱动晶体管的沟道宽长比为W1/L1，第二驱动晶体管的沟道宽长比为W2/L2；
获取输入第一颜色子像素的预设数据信号Vdata1，输入第二颜色子像素的预设数据信号Vdata2，输入各颜色子像素的预设电源电压Vdd；以及
根据第一驱动晶体管的沟道宽长比和第二驱动晶体管的沟道宽长比的比值大致满足的比值关系式(W1/L1)：(W2/L2)计算得到比值。
例如，蓝色子像素、红色子像素以及绿色子像素的预设电流效率分别为E B、E R以及E G，蓝色子像素、红色子像素以及绿色子像素的预设亮度分别为Y [B]、Y [R]以及Y [B]。
例如，根据上述参数以及关系式(5)可以计算各颜色子像素的驱动晶体管的沟道宽长比的比值。假设输入各颜色子像素的预设数据信号Vdata均相同且各颜色子像素的亮度处于显示装置的最高亮度或最高灰阶时，红色子像素、绿色子像素以及蓝色子像素中的驱动晶体管的沟道宽长比满足如下比例关系式(13)：
(W/L) R：(W/L) G：(W/L) B＝(Y [R]/E R):(Y [G]/E G):(Y [B]/E B)。
将上述第一个示例中的参数代入关系式(13)中可得到：
(W/L) R：(W/L) G：(W/L) B＝1:1.24:2.06。
将上述第二个示例中的参数代入关系式(13)中可得到：
(W/L) R：(W/L) G：(W/L) B＝1:0.85:1.76。
将上述第三个示例中的参数代入关系式(13)中可得到：
(W/L) R：(W/L) G：(W/L) B＝1:0.97:1.7。
实际显示过程中，可以将输入各颜色子像素的数据信号之差设计的较小(例如输入不同颜色子像素的数据信号之差不大于1.5V)以使得各颜色子像素具有大致相同的数据信号范围。
考虑到实际工艺能力的差距，红色子像素、绿色子像素以及蓝色子像素中的驱动晶体管的沟道宽长比的比例可设置为1:1:2。本公开的实施例不限于此，只要红色子像素、绿色子像素以及蓝色子像素的驱动晶体管的沟道宽长比的比值满足如下范围1:(0.7～1.3):(1.5～2.5)即可。
例如，可以根据上述各颜色子像素的驱动晶体管的沟道宽长比之间的比例关系，将蓝色子像素的驱动晶体管的沟道宽长比设计为5/25，绿色子像素和红色子像素的沟道宽长比均设计为3/30。本公开实施例不限于此，可以根据实际工艺需求进行调节。例如，可以根据上述各颜色子像素的驱动晶体管的沟道宽长比之间的比例关系，将蓝色子像素的驱动晶体管的沟道宽长比设计为4/25～6.5/25，绿色子像素和红色子像素的沟道宽长比均设计为2.4/30～4/30。
图3为本公开实施例的第二示例中各颜色子像素的数据电压与驱动各颜色子像素的有机发光元件的薄膜晶体管漏极和源极之间的电流的仿真曲线图。根据上述第二个示例中的各颜色子像素的驱动晶体管的沟道宽长比的比例关系(即(W/L) R：(W/L) G：(W/L) B≈1:1:2)，对各颜色子像素的驱动晶体管的沟道宽长比进行设置，由此得到了图3所示的仿真曲线图。如图3所示，假设该显示装置有效显示面积为0.031981m 2，分辨率为1920*720，在给各颜色子像素输入的预设数据电压均为-2.118V时，流过驱动蓝色子像素110的有机发光元件的薄膜晶体管漏极和源极之间的电流约为666.9纳安，则所有蓝色子像素需要的电流值为666.9*1920*720纳安，即921毫安；流过驱动红色子像素120的有机发光元件的薄膜晶体管漏极和源极之间电流约为322.9纳安，则所有红色子像素需要的电流值为322.9*1920*720纳安，即446毫安；流过驱动绿色子像素130的有机发光元件的薄膜晶体管漏极和源极之间电流约为378.3纳安，则所有绿色子像素需要的电流值为378.3*1920*720纳安，即523毫安。该仿真曲线中的结果与第二个示例中各颜色子像素所需的电流的数值大致吻合。由此，通过将蓝色子像素的驱动晶体管的沟道宽长比设计的比其他颜色子像素的驱动晶体管的沟道宽长比大，以使得蓝色子像素的驱动晶体管能够提供蓝色子像素最大亮度或最高灰阶所需要的电流值，从而使得在保证白光处于白平衡状态下，白光的亮度能够达到800尼特或以上。
图4为沟道宽长比不同的驱动晶体管的栅极电压与漏极和源极之间的电流的曲线图。图4中的不同曲线分别代表不同的沟道宽长比，如图4所示，在沟道宽长比为3/35的驱动晶体管中，该驱动晶体管的阈值电压为-2.47094V，栅极电压为-5.9V；在沟道宽长比为4/35的驱动晶体管中，该驱动晶体管的阈值电压为-2.5126V，栅极电压为-5.9V；在沟道宽长比为5/35的驱动晶体管中，该驱动晶体管的阈值电压为-2.4872V，栅极电压为-5.4V。由上述各驱动晶体管的栅极电压和阈值电压的数值可知，通过改变驱动晶体管的沟道宽长比基本不影响驱动晶体管的驱动特性。
图5A-图5C分别为各颜色子像素中驱动晶体管的沟道宽长比与充电率的关系图。图5A为在红色子像素的驱动电路写入高灰阶(例如255灰阶)、中灰阶(例如128灰阶)和低灰阶(例如32灰阶)对应的数据信号的情况下，驱动晶体管的不同沟道宽长比的充电率的变化情况。如图5A所示，驱动晶体管的沟道宽长比为5/35以及4/35时的充电率均大于驱动晶体管的沟道宽长比为3/35时的充电率。同理，图5B为在绿色子像素的驱动电路写入高灰阶(例如255灰阶)、中灰阶(例如128灰阶)和低灰阶(例如32灰阶)对应的数据信号的情况下，驱动晶体管的不同沟道宽长比的充电率的变化情况。如图5B所示，驱动晶体管的沟道宽长比为5/35以及4/35时的充电率均大于驱动晶体管的沟道宽长比为3/35时的充电率。图5C为在蓝色子像素的驱动电路写入高灰阶(例如255灰阶)、中灰阶(例如128灰阶)和低灰阶(例如32灰阶)对应的数据信号的情况下，驱动晶体管的不同沟道宽长比的充电率的变化情况。如图5C所示，驱动晶体管的沟道宽长比为5/35以及4/35时的充电率均大于驱动晶体管的沟道宽长比为3/35时的充电率。由此可知，在改变各颜色子像素的驱动晶体管的沟道宽长比以满足合适比例关系的过程中，可以考虑增大沟道宽长比(例如增加沟道的宽度)以增加该驱动晶体管的充电率，从而可以减少充电时间。
本公开另一实施例提供一种有机发光二极管显示装置，包括上述阵列基板。
在一些示例中，有机发光二极管显示装置为车载显示装置。
本公开实施例通过将不同颜色子像素的驱动晶体管的沟道宽长比设计的不同，从而能够尽量避免车载显示装置的显示屏显示高亮度画面时出现蓝光亮度不足的现象。
当然，本公开实施例不限于有机发光二极管为车载显示装置，还可以是数码相机、手机、手表、平板电脑、笔记本电脑等任何具有显示功能的产品或者部件，本实施例不限于此。
本公开另一实施例提供一种显示基板，图6为根据本公开实施例提供的显示基板的示意性框图，图7为根据本公开实施例提供的显示基板的重复单元的示意图，图8为根据本公开实施例提供的一种显示基板的平面示意图。
例如，如图6-7所示，本公开的实施例提供的显示基板1000包括衬底基板100和设置在衬底基板100上的沿第一方向(即Y方向)和第二方向(即X方向)排列的多个重复单元11，第一方向和第二方向相交。例如，第一方向和第二方向垂直。每个重复单元11包括多个子像素22，例如包括第一颜色子像素110和第二颜色子像素120。各颜色子 像素22包括有机发光元件220和像素电路221，像素电路221用于驱动有机发光元件220发光，像素电路221包括驱动电路222。第一颜色子像素110的驱动电路222包括第一驱动晶体管111，第二颜色子像素120的驱动电路222包括第二驱动晶体管121，第一驱动晶体管111的沟道宽长比大于第二驱动晶体管121的沟道宽长比。本公开实施例通过优化阵列基板上的不同颜色子像素的驱动晶体管的沟道宽长比，可以提高包括该阵列基板的显示装置的亮度。
本公开实施例中第一驱动晶体管的沟道宽长比和第二驱动晶体管的沟道宽长比的关系与图1A-图1E所示的实施例中的第一驱动晶体管的沟道宽长比和第二驱动晶体管的沟道宽长比的关系相同，在此不再赘述。
例如，显示基板1000可以应用于显示面板，例如有源矩阵有机发光二极管(AMOLED)显示面板等。显示基板1000可以为阵列基板。
例如，衬底基板100可以为玻璃基板、石英基板、塑料基板等合适的基板。
例如，如图7所示，每个重复单元11还包括第三颜色子像素130，第三颜色子像素130包括第三驱动晶体管131，第三驱动晶体管131的沟道宽长比小于第一驱动晶体管111的沟道宽长比。
本公开实施例中第一驱动晶体管、第二驱动晶体管以及第三驱动晶体管的沟道宽长比之间的关系与图1A-图1E所示的实施例中的第一驱动晶体管、第二驱动晶体管以及第三驱动晶体管的沟道宽长比之间的关系相同，在此不再赘述。
例如，如图7所示，每个重复单元11中，第一颜色子像素110、第二颜色子像素120以及第三颜色子像素130的像素电路依次沿第一方向(Y方向的箭头所指的方向)排列。例如，沿X方向排列的一列子像素为相同颜色的子像素。
例如，各颜色子像素的像素电路在衬底基板100上的正投影覆盖的区域大致位于一个矩形内(如图10所示的虚线框1101)。需要说明的是，像素电路的有一些信号线包括位于该矩形内的部分以及延伸出该矩形外的部分，因此这里像素电路在衬底基板上的正投影主要包括各个晶体管、电容等元件的结构在衬底基板上的正投影以及各个信号线位于该矩形内的部分在衬底基板上的正投影。
例如，每个子像素22的有机发光元件220包括第一电极、第二电极和设置在第一电极和第二电极之间的发光层。有机发光元件220的第一电极和第二电极之一与驱动晶体管电连接，图7-图9E所示的示例以有机发光元件的第二电极与驱动晶体管电连接为例进行描述。
例如，如图8所示，像素电路221还包括第二发光控制电路223和第一发光控制电路224。驱动电路222包括控制端、第一端和第二端，且被配置为对有机发光元件220提供驱动有机发光元件220发光的驱动电流。例如，第二发光控制电路223与驱动电路222的第一端和第一电压端VDD连接，且被配置为实现驱动电路222和第一电压端VDD之间的连接导通或断开，第一发光控制电路224与驱动电路222的第二端和有机发光元件220的第一电极电连接，且被配置为实现驱动电路222和有机发光元件220之间的连 接导通或断开。
例如，如图8所示，像素电路221还包括数据写入电路226、存储电路227、阈值补偿电路228和复位电路229。数据写入电路226与驱动电路222的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储电路227；存储电路227与驱动电路222的控制端和第一电压端VDD电连接，且被配置为存储数据信号；阈值补偿电路228与驱动电路222的控制端和第二端电连接，且被配置为对驱动电路222进行阈值补偿；复位电路229与驱动电路222的控制端和有机发光元件220的第一电极电连接，且配置为在复位控制信号的控制下对驱动电路222的控制端和有机发光元件220的第一电极进行复位。
例如，如图8所示，驱动电路222包括驱动晶体管T1，驱动电路222的控制端包括驱动晶体管T1的栅极，驱动电路222的第一端包括驱动晶体管T1的第一极，驱动电路222的第二端包括驱动晶体管T1的第二极。
例如，如图8所示，数据写入电路226包括数据写入晶体管T2，存储电路227包括存储电容C，阈值补偿电路228包括阈值补偿晶体管T3，第二发光控制电路223包括第二发光控制晶体管T4，第一发光控制电路224包括第一发光控制晶体管T5，复位电路229包括第一复位晶体管T6和第二复位晶体管T7，复位控制信号可以包括第一子复位控制信号和第二子复位控制信号。
例如，如图8所示，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线Vd电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与第一扫描信号线Ga1电连接以接收扫描信号；存储电容C的第一极与第一电源端VDD电连接，存储电容C的第二极与驱动晶体管T1的栅极电连接；阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与第二扫描信号线Ga2电连接以接收补偿控制信号；第一复位晶体管T6的第一极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的栅极电连接，第一复位晶体管T6的栅极被配置为与第一复位控制信号线Rst1电连接以接收第一子复位控制信号；第二复位晶体管T7的第一极被配置为与第二复位电源端Vinit2电连接以接收第二复位信号，第二复位晶体管T7的第二极与有机发光元件220的第一电极电连接，第二复位晶体管T7的栅极被配置为与第二复位控制信号线Rst2电连接以接收第二子复位控制信号；第二发光控制晶体管T4的第一极与第一电源端VDD电连接，第二发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第二发光控制晶体管T4的栅极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第一发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第一发光控制晶体管T5的第二极与有机发光元件220的第二电极电连接，第一发光控制晶体管T5的栅极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号；有机发光元件220的第一电极与第二电源端VSS电连接。
例如，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图8所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
例如，如图8所示，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极可以电连接到同一条信号线，例如第一扫描信号线Ga1，以接收相同的信号(例如，扫描信号)，此时，显示基板1000可以不设置第二扫描信号线Ga2，减少信号线的数量。又例如，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T2的栅极电连接到第一扫描信号线Ga1，阈值补偿晶体管T3的栅极电连接到第二扫描信号线Ga2，而第一扫描信号线Ga1和第二扫描信号线Ga2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得数据写入晶体管T2的栅极和阈值补偿晶体管T3可以被分开单独控制，增加控制像素电路的灵活性。
例如，如图8所示，第一发光控制信号和第二发光控制信号可以相同，即，第二发光控制晶体管T4的栅极和第一发光控制晶体管T5的栅极可以电连接到同一条信号线，例如第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板1000可以不设置第二发光控制信号线EM2，减少信号线的数量。又例如，第二发光控制晶体管T4的栅极和第一发光控制晶体管T5的栅极也可以分别电连接至不同的信号线，即，第二发光控制晶体管T4的栅极电连接到第一发光控制信号线EM1，第一发光控制晶体管T5的栅极电连接到第二发光控制信号线EM2，而第一发光控制信号线EM1和第二发光控制信号线EM2传输的信号相同。
需要说明的是，当第二发光控制晶体管T4和第一发光控制晶体管T5为不同类型的晶体管，例如，第二发光控制晶体管T4为P型晶体管，而第一发光控制晶体管T5为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。
例如，第一子复位控制信号和第二子复位控制信号可以相同，即，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极可以电连接到同一条信号线，例如第一复位控制信号线Rst1，以接收相同的信号(例如，第一子复位控制信号)，此时，显示基板1000可以不设置第二复位控制信号线Rst2，减少信号线的数量。又例如，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极也可以分别电连接至不同的信号线，即第一复位晶体管T6的栅极电连接到第一复位控制信号线Rst1，第二复位晶体管T7的栅极电连接到第二复位控制信号线Rst2，而第一复位控制信号线Rst1和第二复位控制信号线Rst2传输的信号相同。需要说明的是，第一子复位控制信号和第二子复位控制信号也可以不相同。
例如，在一些示例中，第二子复位控制信号可以与扫描信号相同，即第二复位晶体管T7的栅极可以电连接到第一扫描信号线Ga1以接收扫描信号作为第二子复位控制信号。
例如，第一复位晶体管T6的栅极和第二复位晶体管T7的源极分别连接到第一复位电源端Vinit1和第二复位电源端Vinit2，第一复位电源端Vinit1和第二复位电源端Vinit2可以为直流参考电压端，以输出恒定的直流参考电压。第一复位电源端Vinit1和第二复位电源端Vinit2可以相同，例如第一复位晶体管T6的栅极和第二复位晶体管T7的源极连接到同一复位电源端。第一复位电源端Vinit1和第二复位电源端Vinit2可以为高压端，也可以为低压端，只要其能够提供第一复位信号和第二复位信号以对驱动晶体管T1的栅极和发光元件220的第一电极进行复位即可，本公开对此不作限制。
需要说明的是，图8所示的像素电路中的驱动电路222、数据写入电路226、存储电路227、阈值补偿电路228和复位电路229仅为示意性的，驱动电路222、数据写入电路226、存储电路227、阈值补偿电路228和复位电路229等电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
例如，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第二发光控制晶体管T4、第一发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
需要说明的是，在本公开实施例中，子像素的像素电路除了可以为图8所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
图9A-10A为本公开一些实施例提供的一种像素电路的各层的示意图。下面结合附图9A-10A描述像素电路中的各个电路在背板上的位置关系，图9A-10A所示的示例以一个重复单元11的像素电路221为例，且以第一颜色子像素110包括的像素电路的各晶体管的位置进行示意，其他颜色子像素中像素电路包括的部件与第一颜色子像素包括的的各晶体管的位置大致相同。如图9A所示，该第一颜色子像素110的像素电路221包括图8所示的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第二发光控制晶体管T4、第一发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7、存储电容C。
图9A-10A还示出了电连接到各个颜色子像素的像素电路121的第一扫描信号线Ga1、第二扫描信号线Ga2、第一复位控制信号线Rst1、第二复位控制信号线Rst2、第一 复位电源端Vinit1的第一复位电源信号线Init1、第二复位电源端Vinit2的第二复位电源信号线Init2、第一发光控制信号线EM1、第二发光控制信号线EM2、数据线Vd、第一电源端VDD的第一电源信号线VDD1、第二电源信号线VDD2、第三电源信号线VDD3(即电源线)、屏蔽线344。第一电源信号线VDD1和第二电源信号线VDD2彼此电连接，且第一电源信号线VDD1和第三电源信号线VDD3彼此电连接。电源线VDD3在垂直于衬底基板的第三方向上与数据线Vd交叠。
需要说明的是，在图9A至9E所示的示例中，第一扫描信号线Ga1和第二扫描信号线Ga2为同一条信号线，第一复位电源信号线Init1和第二复位电源信号线Init2为同一条信号线，第一复位控制信号线Rst1和第二复位控制信号线Rst2为同一条信号线，第一发光控制信号线EM1和第二发光控制信号线EM2为同一条信号线，但不限于此。
例如，图9A示出了该显示基板中像素电路的有源半导体层310。有源半导体层310可采用半导体材料图案化形成。有源半导体层310可用于制作上述的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第二发光控制晶体管T4、第一发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的有源层。有源半导体层310包括各子像素的各晶体管的有源层图案和掺杂区图案(即第三颜色子像素中示出的源极区域s和漏极区域d)，且同一像素电路中的各晶体管的有源层图案和掺杂区图案一体设置。
需要说明的是，有源层可以包括一体形成的低温多晶硅层，其中的源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个子像素的各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素电路中的各晶体管包括掺杂区图案(即源极区域s和漏极区域d)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
例如，沿第一方向排列的不同颜色子像素的像素电路中的有源半导体层没有连接关系，彼此断开。沿第二方向排列的相同颜色子像素的像素电路中的有源半导体层可以为一体设置，也可以彼此断开。
例如，有源半导体层310可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
例如，像素电路的栅极金属层可以包括第一导电层和第二导电层。在上述的有源半导体层310上形成有栅极绝缘层(如图10B和图10C所示)，用于保护上述的有源半导体层310。图9B示出了该显示基板包括的第一导电层320，第一导电层320设置在栅极绝缘层上，从而与有源半导体层310绝缘。第一导电层320可以包括存储电容C的第二极CC2、第一扫描信号线Ga1、第一复位控制信号线Rst1、第一发光控制信号线EM1以及驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第二发光控制晶体管T4、第一发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的栅极。
例如，如图9B所示，数据写入晶体管T2的栅极可以为第一扫描信号线Ga1与有源半导体层310交叠的部分；第二发光控制晶体管T4的栅极可以为第一发光控制信号线EM1与有源半导体层310交叠的第一部分，第一发光控制晶体管T5的栅极可以为第一发光控制信号线EM1与有源半导体层310交叠的第二部分；第一复位晶体管T6的栅极 为第一复位控制信号线Rst1与有源半导体层310交叠的第一部分，第二复位晶体管T7的栅极为第一复位控制信号线Rst1与有源半导体层310交叠的第二部分；阈值补偿晶体管T3可为双栅结构的薄膜晶体管，阈值补偿晶体管T3的第一个栅极可为第一扫描信号线Ga1与有源半导体层310交叠的部分，阈值补偿晶体管T3的第二个栅极可为从第一扫描信号线Ga1突出的突出部P与有源半导体层310交叠的部分。如图8和9B所示，驱动晶体管T1的栅极可为存储电容C的第二极CC2。
需要说明的是，图9A中的各虚线矩形框示出了第一导电层320与有源半导体层310交叠的各个部分。
例如，如图9B所示，第一扫描信号线Ga1、第一复位控制信号线Rst1和第一发光控制信号线EM1沿第二方向X排布。第一扫描信号线Ga1位于第一复位控制信号线Rst1和第一发光控制信号线EM1之间。
例如，在第二方向X上，存储电容C的第二极CC2(即驱动晶体管T1的栅极)位于第一扫描信号线Ga1和第一发光控制信号线EM1之间。从第一扫描信号线Ga1突出的突出部P位于第一扫描信号线Ga1的远离第一发光控制信号线EM1的一侧。
例如，如图9A所示，在第二方向X上，数据写入晶体管T2的栅极、阈值补偿晶体管T3的栅极、第一复位晶体管T6的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第一侧，第二发光控制晶体管T4的栅极、第一发光控制晶体管T5的栅极均位于驱动晶体管T1的栅极的第二侧。例如，图9A-10A所示的示例中，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第一侧和第二侧为在第二方向X上驱动晶体管T1的栅极的彼此相对的两侧。例如，如图9A-10A所示，在XY面内，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第一侧可以为驱动晶体管T1的栅极的上侧，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第二侧可以为驱动晶体管T1的栅极的下侧。所述下侧，例如显示基板的用于绑定IC的一侧为显示基板的下侧，驱动晶体管T1的栅极的下侧，为驱动晶体管T1的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管T1的栅极的更远离IC的一侧。
例如，在一些实施例中，如图9A-10A所示，在第一方向Y上，数据写入晶体管T2的栅极和第二发光控制晶体管T4的栅极均位于驱动晶体管T1的栅极的第三侧，阈值补偿晶体管T3的第一个栅极、第一发光控制晶体管T5的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第四侧。例如，图9A-10A所示的示例中，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第三侧和第四侧为在第一方向Y上驱动晶体管T1的栅极的彼此相对的两侧。例如，如图9A-10A所示，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第三侧可以为第一颜色子像素的像素电路的驱动晶体管T1的栅极的左侧，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第四侧可以为第一颜色子像素的像素电路的驱动晶体管T1的栅极的右侧。所述左侧和右侧，例如在同一像素电路中，数据线在第一电源信号线VDD1左侧，第一电源信号线VDD1在数据线右侧。
例如，在上述的第一导电层320上形成有第一绝缘层(如图10B和图10C所示)， 用于保护上述的第一导电层320。图9C示出了该像素电路的第二导电层330，第二导电层330包括存储电容C的第一极CC1、第一复位电源信号线Init1、第二电源信号线VDD2以及遮光部S。第二电源信号线VDD2与存储电容C的第一极CC1一体形成。存储电容C的第一极CC1与存储电容C的第二极CC2至少部分重叠以形成存储电容C。
例如，在上述的第二导电层330上形成有第二绝缘层(如图10B和图10C所示)，用于保护上述的第二导电层330。图9D示出了该像素电路的源漏极金属层340，源漏极金属层340包括数据线Vd、第一电源信号线VDD1以及屏蔽线344。上述数据线Vd、第一电源信号线VDD1以及屏蔽线344均沿X方向延伸。屏蔽线344与数据线Vd同层同材料设置，使得屏蔽线可与数据线在同一次构图工艺中同时形成，避免为了制作屏蔽线而增加额外的构图工艺，从而简化了显示基板的制作流程，节约了制作成本。
例如，源漏极金属层340还包括第一连接部341、第二连接部342和第三连接部343(即连接结构343)。图9D还示出了多个过孔的示例性位置，源漏金属层340通过所示的多个过孔与位于该源漏金属层340与衬底基板之间的多个膜层连接。如图9D所示，不同填充的过孔表示源漏金属层340通过其连接至不同膜层。例如，白色填充的过孔表示源漏金属层340通过其连接至图9A所示的有源半导体层310，黑点填充的过孔表示有漏金属层340通过其连接至图9C所示的第二导电层，各个过孔所在的具体膜层以及具体连接关系在后续图10A所示的图中将进行详细描述。
例如，在上述的源漏极金属层340上形成有第三绝缘层和第四绝缘层(如图10B和图10C所示)，用于保护上述的源漏极金属层340。各个子像素的有机发光元件的第二电极可设置在第三绝缘层和第四绝缘层远离衬底基板的一侧。
图9E示出了该像素电路的第三导电层350，第三导电层350包括第四连接部353以及沿X方向和Y方向交叉分布的第三电源信号线VDD3。图9E还示出了多个过孔351和354的示例性位置，第三导电层350通过所示的多个过孔351和354与源漏金属层340连接。
图10A为上述的有源半导体层310、第一导电层320、第二导电层330、源漏极金属层340以及第三导电层350的层叠位置关系的示意图。如图9A-10A所示，数据线Vd通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔381)与有源半导体层310中的数据写入晶体管T2的源极区域相连。第一电源信号线VDD1通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔382)与有源半导体层310中对应的第二发光控制晶体管T4的源极区域相连。
如图9A-10C所示，第一连接部341的一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔384)与有源半导体层310中对应的阈值补偿晶体管T3的漏极区域相连，第一连接部341的另一端通过第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔385)与第一导电层320中的驱动晶体管T1的栅极(即存储电容C的第二极CC2)相连。第二连接部342的一端通过第二绝缘层中的一个过孔(例如，过孔386)与第一复位电源信号线Init1相连，第二连接部342的另一端通过栅极绝缘层、 第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔387)与有源半导体层310中的第二复位晶体管T7的漏极区域相连。第三连接部343(连接结构343)通过位于连接结构343与有源半导体层310之间的无机层，例如栅极绝缘层103、第一绝缘层104和第二绝缘层105中的至少一个过孔(例如，过孔352，即第一连接孔343-1)与有源半导体层310中的第一发光控制晶体管T5的漏极区域相连。
需要说明的是，本公开实施例中采用的晶体管的源极区域和漏极区域在结构上可以是相同的，所以其源极区域和漏极区域在结构上可以是没有区别的，因此根据需要二者是可以互换的。
例如，如图9A-10A所示，第一电源信号线VDD1通过位于第二导电层330和源漏金属层340之间的第二绝缘层中的至少一个过孔(例如，过孔3832)与第二导电层330中的存储电容C的第一极CC1相连。
例如，如图9A-10A所示，屏蔽线344沿X方向延伸，且其在衬底基板上的正投影位于驱动晶体管在衬底基板上的正投影与数据线在衬底基板上的正投影之间。例如，第一颜色子像素的像素电路中的屏蔽线能够减小第二颜色子像素的像素电路中的数据线上传输的信号对第一颜色子像素的阈值补偿晶体管T3的性能产生的影响，进而减小第一颜色子像素的驱动晶体管的栅极和第二颜色子像素的数据线之间的耦合的影响，减弱串扰问题。
例如，如图9A-10A所示，屏蔽线344通过第二绝缘层中的至少一个过孔(例如过孔332)与第一复位电源信号线Init1相连，除了使得屏蔽线具有固定电位之外，还使得第一复位电源信号线上传输的初始化信号的电压更稳定，从而更有利于像素驱动电路的工作性能。
例如，如图9A-10A所示，屏蔽线344分别与沿Y方向延伸的两条第一复位电源信号线Init1耦接以使屏蔽线344具有固定电位，且这两条第一复位电源信号线Init1分别位于屏蔽线344沿X方向的两侧。例如，这两条第一复位电源信号线分别与第n行像素电路和第n+1行像素电路对应。
例如，同一列屏蔽线344可以为一整条屏蔽线，该整条屏蔽线包括多个位于相邻两条第一复位电源信号线之间的子部分，且每一子部分分别位于该列的每个像素电路区域内。
例如，除了将屏蔽线344与复位电源信号线耦接外，还可以将屏蔽线344与第一电源信号线耦接，使得屏蔽线344具有与第一电源信号线传输的电源信号相同的固定电位。
例如，屏蔽线344在衬底基板上的正投影位于阈值补偿晶体管T3在衬底基板上的正投影与数据线Vd在衬底基板上的正投影之间，使得屏蔽线344能够减小由于数据线上传输的信号变化对阈值补偿晶体管T3的性能产生的影响，进而减小驱动晶体管的栅极和数据信号线Vd(n+1)之间的耦合的影响，解决垂直串扰的问题，使得显示基板在用于显示时能够获得更好的显示效果。
例如，屏蔽线344在衬底基板上的正投影可以位于第一连接部341在衬底基板上的 正投影与数据线在衬底基板上的正投影之间；屏蔽线344在衬底基板上的正投影位于驱动晶体管T1在衬底基板上的正投影与数据线在衬底基板上的正投影之间。
上述设置方式很好的降低了数据线与阈值补偿晶体管之间产生的第一串扰，以及数据线与第一连接部之间产生的第二串扰，从而降低了由于上述第一串扰和第二串扰导致的对驱动晶体管产生的间接串扰。另外，上述设置方式还降低了数据线与驱动晶体管之间产生的直接串扰，从而更好的保证了显示基板的工作性能。
例如，屏蔽线344不仅限于上述设置方式，屏蔽线344还可以仅与对应于第n行像素电路的复位电源信号线耦接，或者仅与对应于第n+1行像素电路的复位电源信号线耦接。而且，屏蔽线344在X方向的延伸长度也可根据实际需要设置。
例如，各颜色子像素的像素电路还包括遮光部S1，遮光部S1与屏蔽线344异层设置，且遮光部S1在衬底基板上的正投影与屏蔽线344在衬底基板上的正投影有交叠。屏蔽线344通过第二绝缘层中的过孔331与第二导电层330中的遮光部S1相连，使遮光部S1具有固定电位，从而更好的减小了阈值补偿晶体管T3与其附近的其他导电图形之间的耦合作用，使得显示基板的工作性能更稳定。
例如，遮光部S1与阈值补偿晶体管T3的两个栅极之间的有源半导体层310有交叠以防止两个栅极之间的有源半导体层310被光照而改变特性，例如防止该部分有源半导体层的电压发生变化，以防止产生串扰。
本示例示意性的示出遮光部与屏蔽线相连，但不限于此，两者也可以不连接。
例如，如图9A-10A所示，第三电源信号线VDD3通过第三绝缘层和第四绝缘层中的至少一个过孔351与第一电源信号线VDD1相连，第四连接部353通过第三绝缘层和第四绝缘层中的过孔354与第三连接部343相连。
例如，第三绝缘层可以为钝化层，第四绝缘层可以为第一平坦层，第三绝缘层位于第四绝缘层与衬底基板之间。第四绝缘层可以为有机层，且有机层的厚度较钝化层等无机层厚。
例如，过孔351和过孔354均为嵌套过孔，即过孔351包括第三绝缘层中的第一过孔和第四绝缘层中的第二过孔，第三绝缘层中的第一过孔与第四绝缘层中的第二过孔的位置相对，且第四绝缘层中的第二过孔在衬底基板上的正投影位于第三绝缘层中的第一过孔在衬底基板上的正投影内。
例如，第三电源信号线VDD3呈网格状分布，其包括沿X方向延伸的部分和沿Y方向延伸的部分。第三电源信号线VDD3沿X方向延伸的部分在衬底基板上的正投影与第一电源信号线VDD1在衬底基板上的正投影大致重合或者第一电源信号线VDD1在衬底基板上的正投影位于第三电源信号线VDD3沿X方向延伸的部分在衬底基板上的正投影内(图10A以二者投影大致重合为例进行示意)，且第三电源信号线VDD3与第一电源信号线VDD1电连接可以降低第一电源信号线VDD1的电压降，从而改善显示器件的均一性。
例如，第三电源信号线VDD3可以与源漏金属层采用相同的材料。
为了清楚的示意各个过孔，图10A没有示意过孔与各层之间的位置关系。
例如，如图9A-10A所示，本公开一示例以第一颜色子像素110和第三颜色子像素130中的像素电路包括的各个部件的相对位置关系相同为例，例如，以第一颜色子像素110和第三颜色子像素130的第四连接部353均与各子像素包括的第一发光控制晶体管T5的漏极区域有交叠为例。而第二颜色子像素120(例如红色子像素)的像素电路中的第四连接部353与第一发光控制晶体管T5的漏极区域没有交叠，例如第二颜色子像素120的第四连接部353和第一发光控制晶体管T5的漏极区域分别位于沿Y方向延伸的第三电源信号线VDD3的两侧。例如，如图9D所示，第一颜色子像素和第三颜色子像素的第三连接部343均为块状结构，而第二颜色子像素的第三连接部343为沿X方向延伸的条状部，该条状部的一端用于与后续形成的第四连接部353相连，条状部的另一端用于与第一发光控制晶体管T5的漏极区域相连，以使第四连接部与第一发光控制晶体管T5的漏极区域相连。则后续形成的各颜色子像素的阳极会通过过孔与相应的第四连接部353连接以实现与第一发光控制晶体管T5的漏极区域相连。
本实施例包括但不限于此，各颜色子像素中的第四连接部的位置根据有机发光元件的排列规律以及发光区域的位置而定。
例如，图10B为沿图10A中的AA’线所截的局部截面结构示意图。如图10A和10B所示，第二颜色子像素120的像素电路中有源半导体层中的第一发光控制晶体管T5的第二极(例如为漏极T5d)远离衬底基板100的一侧设置有栅极绝缘层103，栅极绝缘层103远离衬底基板100的一侧设置有第一发光控制信号线EM1，第一发光控制信号线EM1远离衬底基板100的一侧设置有第一绝缘层104，第一绝缘层104远离衬底基板100的一侧设置有第二电源信号线VDD2，第二电源信号线VDD2远离衬底基板100的一侧设置有第二绝缘层105，第二绝缘层105远离衬底基板100的一侧设置有第三连接部343。第二颜色子像素120的第三连接部343通过栅极绝缘层103、第一绝缘层104以及第二绝缘层105的过孔352与有源半导体层310中的第一发光控制晶体管T5的第二极T5d相连。第三连接部343与第二电源信号线VDD2和第一发光控制信号线EM1均有交叠。第三连接部343远离衬底基板100的一侧依次设置有第三绝缘层106和第四绝缘层107，第四绝缘层107远离衬底基板100的一侧设置有第四连接部353以及第三电源信号线VDD3。第三电源信号线VDD3与第二电源信号线VDD2有交叠。第四连接部353通过位于第三绝缘层106和第四绝缘层107中的嵌套过孔354与第三连接部343相连，进而实现与第二发光控制晶体管相连。
例如，如图10B所示，数据线Vd通过栅极绝缘层103、第一绝缘层104和第二绝缘层105中的过孔381与数据写入晶体管T2的源极T2s相连；第一连接部341的一端通过栅极绝缘层103、第一绝缘层104和第二绝缘层中105的过孔384与阈值补偿晶体管T3的漏极T3d相连，第一连接部341的另一端通过第一绝缘层104和第二绝缘层105中的过孔385与驱动晶体管T1的栅极(即存储电容C的第二极CC2)相连；驱动晶体管T1的沟道T1c位于其栅极面向衬底基板100的一侧，且与过孔385没有交叠，驱动晶体管 T1的源极T1d与其栅极以及存储电容C的第一极CC1均有交叠。
例如，图10C为沿图10A中的BB’线所截的局部截面结构示意图。如图10A-10C所示，第一颜色子像素110与第二颜色子像素120不同之处在于第二颜色子像素120中的第四连接部353在衬底基板100上的正投影与其第一发光控制晶体管T5的第二极T5d在衬底基板100上的正投影没有交叠，而第一颜色子像素130中的第四连接部353在衬底基板100上的正投影与其第一发光控制晶体管T5的第二极T5d在衬底基板100上的正投影有交叠。第一颜色子像素110中，第三连接部343与第二电源信号线VDD2和第一发光控制信号线EM1均没有交叠。第一颜色子像素110中，驱动晶体管T1的沟道T1c位于其栅极面向衬底基板100的一侧，且与过孔385有交叠。由此可以看出第一颜色子像素的驱动晶体管的沟道宽度大于第二颜色子像素的沟道宽度。
例如，如图9A-10A所示，在第二方向X上，第一扫描信号线Ga1、第一复位控制信号线Rst1和第一复位电源信号线Init1均位于第一颜色子像素的像素电路的驱动晶体管T1的栅极的第一侧，第一发光控制信号线EM1位于第一颜色子像素的像素电路的驱动晶体管T1的第二侧。
例如，第一扫描信号线Ga1、第一复位控制信号线Rst1、第一发光控制信号线EM1、和第一复位电源信号线Init1均沿第一方向Y延伸，数据线Vd沿第二方向X延伸。
例如，第一电源信号线VDD1沿第二方向X延伸，第二电源信号线VDD2沿第一方向Y延伸。第一电源端VDD的信号线在显示基板上网格化布线。也就是说，在整个显示基板上，第一电源信号线VDD1和第二电源信号线VDD2呈网格状排列，从而第一电源端VDD的信号线的电阻较小、压降较低，进而可以提高第一电源端VDD提供的电源电压的稳定性。
需要说明的是，每个像素电路中的驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、存储电路、阈值补偿电路和复位电路等的位置排布关系不限于图9A-10A所示的示例，根据实际应用需求，可以具体设置驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、存储电路、阈值补偿电路和复位电路的位置。
图11A为本实施例的一示例提供的阵列基板的局部结构示意图。如图11A所示，本示例的阵列基板中的各颜色子像素包括的像素电路为图10A所示的像素电路。例如，如图9A-11A所示，第三电源信号线VDD3远离第一电源信号线VDD1的一侧还设置有第五绝缘层(未示出)。例如，第五绝缘层可以为第二平坦层，其材料可以与第四绝缘层(即第一平坦层)的材料相同，例如有机材料。
例如，如图9A至图11B所示，在至少一个像素单元中，第二颜色子像素120的第一发光控制晶体管T5的第一极通过第一连接孔343-1与连接结构343电连接，连接结构343通过第二连接孔343-2(即过孔352)与第二颜色子像素120的第二电极123电连接，第一连接孔343-1的至少部分在衬底基板上的正投影位于发光控制信号线EM1在衬底基板上的正投影的一侧，第二连接孔343-2的至少部分在衬底基板100上的正投影位于发光控制信号线EM1在衬底基板100的上正投影的另一侧；在至少一个像素单元中，第三 颜色子像素130的第二电极133在垂直于衬底基板100的第三方向上与控制第三颜色子像素130的有机发光元件的驱动晶体管T1的沟道T1c没有交叠。
本公开提供一种像素排列结构，该像素排列结构中通过对两个连接孔与发光控制信号线的位置关系的设置以及第三颜色子像素的第二电极与驱动晶体管的沟道位置关系的设置可以在提高像素排列紧凑程度以提高像素分辨率的基础上，通过连接结构有效驱动第二颜色子像素发光。
本公开通过设置不同层的数据线与电源线，即双层信号线，可以实现像素的紧密排布以及优化布线方式。
例如，如图11A和11B所示，第二颜色子像素120的第二电极和第三颜色子像素130的第二电极沿第二方向交替排列。例如，第三颜色子像素的第二电极与第二颜色子像素的像素电路在垂直于衬底基板的方向上交叠。本公开中通过将第三颜色子像素的第二电极设置为与第二颜色子像素的像素电路交叠，可以有效提高像素排列紧凑程度。
例如，第一连接孔343-1在衬底基板100上的正投影的中心位于发光控制信号线EM1在衬底基板100上的正投影的一侧，第二连接孔343-2在衬底基板100上的正投影的中心位于发光控制信号线EM1在衬底基板100的上正投影的另一侧。
例如，如图9A-11B所示，第二颜色子像素120中，连接结构343通过位于连接结构343和第二电极123之间的无机层和有机层的至少之一中的第二连接孔343-2与第二电极123电连接。例如，绝缘层106可以为无机层，绝缘层107可以为有机层107，但不限于此。无机层具有电气绝缘、隔绝水氧的作用，有机层具有保证阳极平坦的作用。例如，第二连接孔343-2为位于第四绝缘层107中的过孔354。上述第一连接孔和第二连接孔均是与连接结构直接相连的孔。例如，连接结构通过第二连接孔实现与第二电极的电连接，连接结构与第二电极之间还可以包括位于其他膜层的过孔进行转接。例如，连接结构343通过位于第三绝缘层106和第四绝缘层107的第二连接孔343-2与第四连接部353连接，第四连接部353通过位于第五绝缘层中的转接孔与第二电极连接，从而实现连接结构与第二电极的电连接。
例如，如图10A、图10B以及图11A所示，在至少一个第二颜色子像素120中，第一连接孔343-1(即352)在衬底基板100上的正投影具有第一面积，第二连接孔343-2(即354)在衬底基板100上的正投影具有第二面积，第一面积和第二面积不同。
例如，如图10A、图10B以及图11A所示，在至少一个第二颜色子像素120中，第一连接孔343-1在第二方向上到发光控制信号线M1具有第一距离，第二连接孔343-2在第二方向上到发光控制信号线EM2具有第二距离，第一距离和第二距离不同。这里连接孔到发光控制信号线的距离可以指连接孔与发光控制信号线的彼此靠近的边缘之间的距离，但不限于此，也可以为连接孔的中心与发光控制信号线的中心线之间的距离。
例如，如图9A-11B所示，第一颜色子像素110的有机发光元件的第二电极113(即阳极)通过第五绝缘层的过孔1133与第四连接部353相连，从而实现与第一发光控制晶体管T5的漏极区域相连。同理，第三颜色子像素130的有机发光元件的第二电极133(即 阳极)通过第五绝缘层的过孔1333与第四连接部353相连，从而实现与第一发光控制晶体管T5的漏极区域相连。第二颜色子像素120的有机发光元件的第二电极123(即阳极)通过第五绝缘层的过孔与第四连接部353相连，进而与第三连接部343相连，以实现与第一发光控制晶体管T5的漏极区域相连。
例如，如图9A-11B所示，在至少一个像素单元中，第三颜色子像素130的第二电极133在第三方向上与控制其他颜色子像素(如第一颜色子像素110和第二颜色子像素120)的有机发光元件的驱动晶体管T1的沟道均没有交叠。
例如，如图9A-11B所示，至少一个像素单元中，第二颜色子像素120的第一连接孔343-1在衬底基板100上正投影相较于第二颜色子像素120的第二连接孔343-2在衬底基板100上正投影远离第二颜色子像素120的第二电极123在衬底基板100上的正投影。在本公开实施例中，第二颜色子像素中的第一连接孔和第二连接孔均与第二颜色子像素的发光区的距离较远，所以第二连接孔即使距离第二电极与发光层交叠的区域较近，也不会影响发光区内发光层以及第二电极的平坦性。
例如，如图9A-11B所示，在至少一个像素单元中，第二颜色子像素120的第二电极123在第三方向上与驱动第二颜色子像素130的有机发光元件的驱动晶体管T1的沟道交叠，从而可以实现像素的紧密排布，提高像素的分辨率。
例如，如图9A-11B所示，在至少一个像素单元中，与第二颜色子像素120的像素电路连接的数据线Vd和第二颜色子像素120的第二电极123在第一方向(即Y方向)上彼此间隔。与第二颜色子像素120的像素电路连接的数据线Vd在衬底基板100上的正投影和第二颜色子像素120的第二电极123在衬底基板100上的正投影没有交叠。
例如，如图9A-11B所示，第二颜色子像素120的第二电极123和与第三颜色子像素130的像素电路连接的数据线Vd在第三方向上交叠。
例如，如图9A-11B所示，至少一个像素单元中，第一颜色子像素110的第二电极113和第三颜色子像素130的第二电极133在沿第二方向延伸的第一直线上的正投影均与第二颜色子像素120的连接结构343在第一直线上的正投影交叠。
例如，如图9A-11B所示，至少一个像素单元中，第三颜色子像素130的第二电极133在沿第一方向延伸的第二直线上的正投影与第二颜色子像素120的连接结构343在第二直线上的正投影交叠。
例如，如图11A所示，各颜色子像素的有机发光元件的第二电极均包括主体电极和连接电极，且各颜色子像素的主体电极的形状均为六边形。
例如，如图11A所示，第一颜色子像素110的第二电极113包括第一主体电极1131和第一连接电极1132，第一主体电极1131和第一连接电极1132可以为一体结构，且第一连接电极1132通过连接孔1133连接至第四连接部353，进而与第三连接部343相连以实现与第一颜色子像素110的第一发光控制晶体管T5的第二极相连。第二颜色子像素120的第二电极123包括第二主体电极1231和第二连接电极1232，第二主体电极1231和第二连接电极1232可以为一体结构，且第二连接电极1232通过连接孔1233连接至第 四连接部353，进而与第三连接部343相连以实现与第二颜色子像素120的第一发光控制晶体管T5的第二极相连。第三颜色子像素130的第二电极133包括第三主体电极1331和第三连接电极1332，第三主体电极1331和第三连接电极1332可以为一体结构，且第三连接电极1332通过连接孔1333连接至第四连接部353，进而与第三连接部343相连以实现与第三颜色子像素130的第一发光控制晶体管T5的第二极相连。
例如，如图9A-11B所示，第一颜色子像素110的主体电极1131在第一直线上的正投影与第二颜色子像素120的连接结构343在第一直线上的正投影交叠。
例如，如图9A-11B所示，第三颜色子像素130的主体电极1331在第二直线上的正投影与第二颜色子像素120的连接结构343在第二直线上的正投影交叠。
例如，如图9A-11B所示，第二颜色子像素120的第二电极123在第三方向上与扫描信号线Ga1交叠。第二颜色子像素120的第二电极123在衬底基板100上的正投影与扫描信号线Ga1在衬底基板100上的正投影交叠。
例如，如图9A-11B所示，第二颜色子像素120的第二电极123在第三方向上和与该第二颜色子像素120的像素电路电连接的扫描信号线Ga1交叠。例如，第二颜色子像素120的第二电极123在衬底基板100上的正投影和与该第二颜色子像素120的像素电路电连接的扫描信号线Ga1在衬底基板100上的正投影交叠。
例如，如图9A-11B所示，至少一个像素单元中，第一颜色子像素110的第二电极113和第三颜色子像素130的第二电极133在第三方向上均与发光控制信号线EM1交叠。例如，至少一个像素单元中，第一颜色子像素110的第二电极113在衬底基板100上的正投影和第三颜色子像素130的第二电极133在衬底基板100上的正投影均与发光控制信号线EM1在衬底基板100上的正投影交叠。
例如，如图9A-11B所示，第一颜色子像素110的第二电极113包括分别位于所述发光控制信号线EM1两侧的第一电极子部113-1和第二电极子部113-2，第一电极子部113-1的面积大于第二电极子部113-2的面积。图11A所示以发光控制信号线的中心线为基准，第一颜色子像素110的第二电极113位于发光控制信号线的中心线两侧的部分分别为第一电极子部113-1和第二电极子部113-2。
例如，如图9A-11B所示，第一颜色子像素110中，第二连接孔343-2在衬底基板100上的正投影的中心和第一电极子部113-1在衬底基板100上的正投影分别位于发光控制信号线EM1在衬底基板100上的正投影的两侧。
例如，如图9A-11B所示，在至少一个像素单元中，存储电容C的第二极CC2复用为驱动晶体管T1的栅极，第一颜色子像素110的存储电容C的第二极CC2的面积与第二颜色子像素120的存储电容C的第二极CC2的面积不同。
例如，如图9A-11B所示，第一颜色子像素110的第二电极113的面积大于第二颜色子像素120的第二电极123的面积，且第一颜色子像素110的存储电容C的第二极CC2的面积大于第二颜色子像素120的存储电容C的第二极CC2的面积。
例如，如图9A-11B所示，第二颜色子像素120中，存储电容C的第一极CC1在第 三方向上与连接结构343交叠。
例如，如图9A-11B所示，第一颜色子像素110的第二电极113在第三方向上与数据线Vd交叠，且交叠部分沿第二方向的长度大于第二电极113沿第二方向的最大长度的80％，从而提高第一颜色子像素的第二电极的平坦性。例如，第一颜色子像素110的第二电极113在衬底基板100上的正投影与数据线Vd在衬底基板100上的正投影交叠，且交叠部分沿第二方向的长度大于第二电极113的正投影沿第二方向的最大长度的80％。
例如，如图9A-11B所示，第一颜色子像素110的第二电极113在第三方向上与电源线VDD3交叠，且交叠部分沿第二方向的长度大于第二电极113沿第二方向的最大长度的80％，从而提高第一颜色子像素的第二电极的平坦性。例如，第一颜色子像素110的第二电极113在衬底基板100上的正投影与电源线VDD3在衬底基板100上的正投影交叠，且交叠部分沿第二方向的长度大于第二电极113的正投影沿第二方向的最大长度的80％。
例如，第一颜色子像素110的第一连接电极1132，在Y方向上位于第一主体电极1131中心远离该子像素像素电路的数据线的一侧，且在X方向上位于第一主体电极1131中心远离该子像素像素电路的发光控制信号线的一侧。例如，第一颜色子像素110的第一连接电极1132和第一主体电极1131在X方向排布，第一连接电极1132位于第一主体电极1131的右下角。例如，第二颜色子像素120的第二连接电极1232，在Y方向上位于第二主体电极1231中心远离该子像素像素电路数据线的一侧，且在X方向上位于第二主体电极1231中心靠近该子像素像素电路发光控制信号线的一侧。例如，第二颜色子像素120的第二连接电极1232和第二主体电极1231在X方向排布，第二连接电极1232位于第一主体电极1231的右下角。例如，第三颜色子像素130的第三连接电极1332与第三主体电极1331在Y方向排布，第三连接电极1332位于第三主体电极1331的右侧，即靠近该子像素像素电路靠近屏蔽线的一侧。
例如，例如，如图9A-11B所示，相邻子像素之间还设置有像素限定层(如图1B所示的像素限定层101)，像素限定层包括用于限定各颜色子像素的发光区的开口。像素限定层的开口在衬底基板上的正投影位于相应的第二电极的主体电极在衬底基板上的正投影内。
例如，如图1B、9A-11B所示，显示基板还包括位于各子像素的第二电极远离衬底基板100一侧的像素限定层101，像素限定层101包括用于限定各子像素的发光区的开口1010，各子像素的有机发光层的至少部分位于开口1010内，所述像素限定层101的开口1010在衬底基板100上的正投影位于各子像素的第二电极的主体电极在衬底基板100上的正投影内。像素限定层101中，限定各第三颜色子像素130的发光区的开口1010-3的面积大于限定各第二颜色子像素120的发光区的开口1010-2的面积，且小于限定各第一颜色子像素110的发光区的开口1010-1的面积。
例如，各颜色子像素还包括有机发光层(如图1B所示的有机发光层112或122)，有机发光层位于第二电极远离衬底基板的一侧。各颜色子像素的第二电极与有机发光层 在像素限定层的开口处接触，像素限定层的开口定义了子像素发光区的形状。例如，有机发光元件的第二电极(例如，阳极)可以设置在像素限定层的下方，像素限定层包括用于限定子像素的开口，该开口露出第二电极的一部分，当有机发光层形成在上述像素限定层中的开口中时，有机发光层与第二电极接触，从而这部分能够驱动有机发光层进行发光。
例如，像素限定层的开口在衬底基板上的正投影位于相应的有机发光层在衬底基板上的正投影内，即有机发光层覆盖了像素限定层的开口。例如，有机发光层的面积大于对应的像素限定层开口的面积，即有机发光层除位于像素限定层开口内部的部分，至少还包括覆盖像素限定层的实体结构上的部分，通常在像素限定层开口的各个边界处的像素限定层的实体结构上均覆盖有机发光层。需要说明的是，以上对于有机发光层图案的描述，是基于例如FMM工艺形成的图案化的各个子像素的有机发光层，除了FMM制作工艺，也有一些有机发光层是采用open mask工艺在整个显示区形成整体的膜层，其形状在衬底基板上的正投影是连续的，所以必然有位于像素限定层开口内的部分和位于像素限定层实体结构上的部分。
本公开另一实施例提供一种显示装置，包括图9A-11B所示的显示基板。
如图11A所示，各颜色子像素的有机发光元件的第二电极的形状为六边形。多个子像素可以划分为沿X方向和Y方向阵列排布的多个像素单元组10。每个像素单元组10包括沿Y方向排列的两列子像素，每列子像素均包括第一颜色子像素110、第二颜色子像素120以及第三颜色子像素130。沿X方向，各像素单元组10中的两列子像素彼此错开小于一个子像素的节距，例如，各像素单元组10中的两列子像素彼此错开约半个子像素的节距。例如，相邻两个子像素彼此相对的边大致平行。例如，相邻列中第一颜色子像素、第二颜色子像素、第三颜色子像素排列顺序相同。例如，在例如X(列)方向上，第一颜色子像素位于相邻列中第二颜色子像素和第三颜色子像素之间，第二颜色子像素位于相邻列中第一颜色子像素和第三颜色子像素之间，第三颜色子像素位于相邻列中第一颜色子像素和第二颜色子像素之间。
例如，在一个像素单元组10中，第一列中的一个第一颜色子像素与第二列中与所述一个第一颜色子像素相邻的一个第二颜色子像素和一个第三颜色子像素构成一个像素单元，可以实现一个像素点显示。在一个像素单元组10中，相邻的两个像素单元中，第一个像素单元中的第一列子像素和第二列子像素与第二个像素单元中的第一列和第二列对调，如第一个像素单元中第一颜色子像素位于第一列，第二颜色子像素和第三颜色子像素位于第二列，第二个像素单元中第一颜色子像素位于第二列，第二颜色子像素和第三颜色子像素位于第一列。例如，第一颜色子像素为蓝色子像素，第二颜色子像素为红色子像素，第三颜色子像素为绿色子像素，每一像素单元均包括位于一列中的一个蓝色子像素以及位于相邻列中与该蓝色子像素相邻的一个红色子像素和一个绿色子像素。
例如，一个蓝色子像素的发光区的面积大于一个红色子像素或一个绿色子像素的发光区的面积。例如，一个蓝色子像素的阳极面积大于一个红色子像素或一个绿色子像素 的阳极面积。例如，第一颜色子像素和第三颜色子像素的阳极的主体电极的形状大致为正六边形，第二颜色子像素的阳极的主体电极的形状为非正六边形，且包括两个对称轴，其在X方向的对称轴的尺寸大于Y方向的对称轴的尺寸。
例如，如图11A所示，第一颜色子像素110的第二电极113的第一主体电极1131覆盖第一颜色子像素110的驱动晶体管，第二颜色子像素120的第二电极123的第二主体电极1231与第二颜色子像素120的驱动晶体管基本没有交叠或者有部分交叠，第三颜色子像130的第二电极133的第三主体电极1331与第三颜色子像素130的驱动晶体管没有交叠。
例如，如图11A所示，第一颜色子像素110(例如蓝色子像素)的第一主体电极1131与扫描线和发光控制信号线有交叠；第二颜色子像素120(例如红色子像素)的第二主体电极1231与扫描线和复位控制信号线有交叠；第三颜色子像素130(例如绿色子像素)的第三主体电极1331与发光控制信号线、下一行像素电路的复位控制信号线以及下一行像素电路的复位电源信号线有交叠。例如第三颜色子像素130(例如绿色子像素)的第三主体电极1331与下一行与其相邻的第一颜色子像素(例如蓝色子像素)的像素驱动电路区域有交叠。
例如，第一颜色子像素110的第一主体电极1131与相邻的第三颜色子像素130的驱动晶体管的部分交叠，且第一颜色子像素110的第一主体电极1131与其像素电路中的数据线、屏蔽线以及相邻第二颜色子像素120的像素电路中的数据线均有交叠。第二颜色子像素120的第二主体电极1231与其像素电路中的数据线没有交叠，且与其像素电路中的第一电源信号线和相邻的第三颜色子像素130的像素电路中的第一电源信号线以及数据线均有交叠。第三颜色子像素130的第三主体电极1331与其像素电路中的数据线和第一电源信号线均有交叠，且与相邻第二颜色子像素120的像素电路中的第一电源信号线有交叠。
例如，如图11A所示，第一颜色子像素110的第一主体电极1131靠近下一行复位控制信号线的一侧设置有与其连接的第一连接电极1132；第二颜色子像素120的第二主体电极1231靠近下一行复位控制信号线的一侧设置有与其连接的第二连接电极1232；第三颜色子像素130的第三主体电极1331靠近其第二发光控制晶体管的一侧设置有与其连接的第三连接电极1332。
例如，如图11A所示，第一颜色子像素110的第一连接电极1132与其像素电路中的第二发光控制晶体管的第二极有交叠。第二颜色子像素120的第二连接电极1232与其像素电路中的第二发光控制晶体管的第二极没有交叠，而第二颜色子像素120的第二发光控制晶体管的第二极与第三颜色子像素130的第三主体电极1331有交叠。第三颜色子像素130的第三连接电极1332与其像素电路中的第二发光控制晶体管的第二极有交叠。
图12为本实施例的另一示例提供的阵列基板的局部结构示意图。如图12所示，本示例中的阵列基板中的各颜色子像素包括的像素电路与图10所示的像素电路不同之处在于，本示例中的第二颜色子像素120的像素电路中的第三连接部与第三颜色子像素的第 三连接部的形状以及相对位置关系均相同。并且，第二颜色子像素120和第三颜色子像素130中，像素电路中的第四连接部353连接至第三连接部343的连接过孔354位于第一发光控制晶体管T5的第二极的远离第一发光控制信号线EM1的一侧。而第一颜色子像素110中，像素电路中的第四连接部353连接至第三连接部343的连接过孔354位于第一发光控制晶体管T5的第二极的靠近第一发光控制信号线EM1的一侧。例如，可以与第一发光控制信号线EM1有交叠。第二颜色子像素120的第二电极123的第二连接电极1232连接至第四连接部353的第二阳极连接过孔1233位于过孔354的靠近第一发光控制信号线EM1的一侧。第三颜色子像素130的第二电极133的第三连接电极1332连接至第四连接部353的第三阳极连接过孔1333位于过孔354的靠近第一发光控制信号线EM1的一侧。第一颜色子像素110的第二电极113的第一连接电极1132连接至第四连接部353的第一阳极连接过孔1133位于过孔354的远离第一发光控制信号线EM1的一侧，以使第一颜色子像素的第二电极的连接电极与第三颜色子像素的第二电极的主体电极之间具有一定距离，防止两者交叠或者靠近引起不良。
例如，如图12所示，第二颜色子像素120(例如为红色子像素)和第三颜色子像素130(例如为绿色子像素)在Y方向交替排列，与所述第二颜色子像素120和第三颜色子像素130相邻的第一颜色子像素110(例如为蓝色子像素)也在Y方向排列，且第二颜色子像素120和第三颜色子像素130构成的子像素排与第一颜色子像素110构成的子像素排在X方向交替分布。例如，一个第一颜色子像素110第二电极的主体电极的面积大于一个第二颜色子像素120第二电极的主体电极的面积，且大于一个第三颜色子像素130第二电极的主体电极面积。例如，一个第三颜色子像素130第二电极的主体电极面积大于一个第二颜色子像素120第二电极的主体电极的面积。例如，一个第一颜色子像素110第二电极的主体电极在Y方向的尺寸大于一个第二颜色子像素120第二电极的主体电极的在Y方向的尺寸，且大于一个第三颜色子像素130第二电极的主体电极在Y方向的尺寸。例如，一个第一颜色子像素110第二电极的主体电极在Y方向的尺寸不超出一个第二颜色子像素120第二电极的主体电极与一个第三颜色子像素130第二电极的主体电极在Y方向的跨度，即第一颜色子像素110第二电极的主体电极、第二颜色子像素120第二电极的主体电极、第三颜色子像素130第二电极的主体电极分别在沿Y方向的直线上投影，第一颜色子像素110第二电极的主体电极的投影位于第二颜色子像素120第二电极的主体电极和第三颜色子像素130第二电极的主体电极的投影的最远的两点之间。例如，一个第一颜色子像素110第二电极的主体电极在X方向的尺寸、第二颜色子像素120第二电极的主体电极在X方向的尺寸、第三颜色子像素130第二电极的主体电极在X方向的尺寸大致相等。例如，第二颜色子像素120第二电极的主体电极在X方向的尺寸、第三颜色子像素130第二电极的主体电极在X方向的尺寸大致相等，且与一个第一颜色子像素110第二电极的主体电极在X方向的尺寸的比值为0.8～1.2。例如，第二颜色子像素120第二电极的连接电极与第三颜色子像素130第二电极的连接电极均位于朝向第一颜色子像素110的第二电极主体电极的一侧。例如，第一颜色子像素110的第二电极的 连接电极位于第二颜色子像素120和第三颜色子像素130构成的子像素排和第一颜色子像素110构成的子像素排之间，且更靠近第三颜色子像素130第二电极的远离第二颜色子像素120第二电极的一侧。
例如，在Y方向排列的第二颜色子像素120和第三颜色子像素130中，第二颜色子像素120的第二阳极连接过孔1233与第三颜色子像素130的第三阳极连接过孔1333位于沿Y方向延伸的直线上，与所述第二颜色子像素120和第三颜色子像素130相邻的第一颜色子像素110的第一阳极连接过孔1133位于该直线远离第一扫描线Ga1的一侧。例如，第一颜色子像素110的第一阳极连接过孔1133与第二颜色子像素120和第三颜色子像素130的连接过孔354大致位于同一条沿Y方向延伸的直线上第二颜色子像素120的第二阳极连接过孔1233与第三颜色子像素130的第三阳极连接过孔1333与各自的第一发光控制晶体管T5的第二极有交叠，第一颜色子像素110的第一阳极连接过孔1133位于其第一发光控制晶体管T5的第二极远离第一发光控制信号线EM1的一侧。
例如，如图12所示，第二颜色子像素120的像素电路中的第四连接部与第一发光控制晶体管T5的漏极区域有交叠，第二颜色子像素120的像素电路中的第四连接部与第三颜色子像素的第四连接部的形状以及相对位置关系均相同。第一颜色子像素110的像素电路中的第四连接部353沿X方向的长度大于另外两种颜色子像素的第四连接353部沿X方向的长度。第一颜色子像素110的像素电路中的第四连接部353与第一发光控制信号线EM1有交叠，而另外两种颜色子像素的第四连接353与第一发光控制信号线EM1没有交叠。
例如，如图12所示，本示例中的显示基板包括沿第一方向和第二方向阵列排布的多个像素单元1，一个所述像素单元1包括一个第一颜色子像素110和与其相邻的一个第二颜色子像素120和一个第三颜色子像素130。
需要说明的是，以上示例中，附图中示意性示出了各个子像素的第二电极的形状、大小和位置，对于各个子像素，实际发光区域由像素限定层开口限定。例如，像素限定层为网格状结构，覆盖各个子像素的第二电极(例如为阳极)的边缘，并且像素限定层包括多个开口，每个开口暴露一个子像素的第二电极的部分，发光层至少形成在所述多个开口内，在发光层远离衬底基板一侧还形成有第一电极(例如为阴极)，对应各个子像素对应的开口的第一电极和第二电极驱动发光层发光。例如，每个子像素的像素限定层开口在衬底基板的投影位于该子像素的第二电极在衬底基板的投影内，所以各个子像素的排布与像素限定层开口的排布、第二电极的排布位置是一一对应的。例如，各个颜色子像素第二电极排布位置可以有多种方式，如图11A和图12所示，除此之外还可以适用于其他像素排布。例如，各个子像素的像素电路在X方向和Y方向阵列排布为多行和多列，每个子像素的像素电路结构除驱动晶体管的尺寸以及连接电极结构外可以大致相同，例如数据线，电源线、电容电极等。例如，沿Y方向，各个子像素的像素电路按照第一颜色子像素的像素电路、第二颜色子像素的像素电路、第三颜色子像素的像素电路的顺序依次排列，沿X方向，各排子像素的像素电路重复排列。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (29)

  1. 一种显示基板，包括：
    衬底基板以及设置在所述衬底基板上的多个第一颜色子像素、多个第二颜色子像素和多个第三颜色子像素；
    发光控制信号线，沿第一方向延伸；
    数据线，沿第二方向延伸，所述第一方向与所述第二方向相交；以及
    电源线，所述电源线在垂直于所述衬底基板的第三方向上与所述数据线交叠，
    其中，至少一个所述子像素包括有机发光元件和驱动所述有机发光元件的像素电路，
    所述有机发光元件包括第一电极、第二电极和设置在所述第一电极和所述第二电极之间的发光层，所述像素电路包括驱动晶体管和第一发光控制晶体管，所述像素电路还包括与所述数据线同层设置的连接结构，
    至少一个所述第二颜色子像素中，所述第二颜色子像素的所述第一发光控制晶体管的第一极通过第一连接孔与所述连接结构电连接，所述连接结构通过第二连接孔与所述第二颜色子像素的第二电极电连接，所述第一连接孔的至少部分在所述衬底基板上的正投影位于所述发光控制信号线在所述衬底基板上的正投影的一侧，所述第二连接孔的至少部分在所述衬底基板上的正投影位于所述发光控制信号线在衬底基板的上正投影的另一侧；
    在至少一个所述第三颜色子像素中，所述第三颜色子像素的所述第二电极在所述第三方向上与控制所述第三颜色子像素的有机发光元件的所述驱动晶体管的沟道没有交叠。
  2. 根据权利要求1所述的显示基板，其中，至少一个所述第三颜色子像素的所述第二电极在所述第三方向上与控制其他颜色子像素的有机发光元件的所述驱动晶体管的沟道均没有交叠。
  3. 根据权利要求1或2所述的显示基板，其中，所述显示基板包括有源半导体层，所述有源半导体层包括各子像素的各晶体管的沟道和源漏区，所述连接结构通过位于所述连接结构与所述有源半导体层之间的无机层中的所述第一连接孔与所述有源半导体层电连接；
    所述连接结构通过位于所述连接结构和所述第二电极之间的有机层和无机层至少之一中的所述第二连接孔与所述第二电极电连接，所述第二颜色子像素中，所述第一连接孔在所述衬底基板上的正投影的中心和所述第二连接孔在所述衬底基板上的正投影的中心分别位于所述发光控制信号线在所述衬底基板上的正投影的两侧。
  4. 根据权利要求1-3任一项所述的显示基板，其中，在至少一个所述第二颜色子像素中，所述第二颜色子像素的所述第一连接孔在所述衬底基板上正投影相较于所述第二颜色子像素的所述第二连接孔在所述衬底基板上正投影远离所述第二颜色子像素的所述第二电极在所述衬底基板上的正投影。
  5. 根据权利要求1-4任一项所述的显示基板，其中，在至少一个所述第二颜色子像素中，所述第二颜色子像素的所述第二电极在所述第三方向上与驱动所述第二颜色子像素的有机发光元件的所述驱动晶体管的沟道交叠。
  6. 根据权利要求1-5任一项所述的显示基板，其中，至少一个所述第二颜色子像素的所述像素电路连接的所述数据线和所述第二颜色子像素的所述第二电极在所述第一方向上彼此间隔。
  7. 根据权利要求6所述的显示基板，其中，至少一个所述第二颜色子像素的所述第二电极和与所述第三颜色子像素的像素电路连接的所述数据线在所述第三方向上交叠。
  8. 根据权利要求1-7任一项所述的显示基板，其中，至少一个所述第一颜色子像素的所述第二电极和至少一个所述第三颜色子像素的所述第二电极在沿所述第二方向延伸的第一直线上的正投影均与至少一个所述第二颜色子像素的所述连接结构在所述第一直线上的正投影交叠。
  9. 根据权利要求8所述的显示基板，其中，至少一个所述第三颜色子像素的所述第二电极在沿所述第一方向延伸的第二直线上的正投影与至少一个所述第二颜色子像素的所述连接结构在所述第二直线上的正投影交叠。
  10. 根据权利要求9所述的显示基板，其中，至少一个所述子像素的所述第二电极包括主体电极和连接电极，所述连接电极与所述第一发光控制晶体管电连接，
    至少一个所述第一颜色子像素的所述主体电极在所述第一直线上的正投影与至少一个所述第二颜色子像素的所述连接结构在所述第一直线上的正投影交叠。
  11. 根据权利要求10所述的显示基板，其中，至少一个所述第三颜色子像素的所述主体电极在所述第二直线上的正投影与至少一个所述第二颜色子像素的所述连接结构在所述第二直线上的正投影交叠。
  12. 根据权利要求1-11任一项所述的显示基板，还包括：
    扫描信号线和复位电源信号线，
    其中，在至少一个所述子像素中，所述像素电路还包括数据写入晶体管和复位晶体管，所述数据写入晶体管的栅极被配置为与所述扫描信号线电连接以接收扫描信号，所述复位晶体管的栅极被配置为与所述复位电源信号线电连接以接收复位控制信号。
  13. 根据权利要求12所述的显示基板，其中，在至少一个所述子像素中，所述像素电路还包括第二发光控制晶体管，所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的的栅极均与所述发光控制信号线电连接以接收发光控制信号。
  14. 根据权利要求12或13所述的显示基板，其中，至少一个所述第二颜色子像素的所述第二电极在所述第三方向上与所述扫描信号线交叠。
  15. 根据权利要求14所述的显示基板，其中，至少一个所述第二颜色子像素的所述第二电极在所述第三方向上和与该第二颜色子像素的所述像素电路电连接的所述扫描信号线交叠。
  16. 根据权利要求12-15任一项所述的显示基板，其中，至少一个所述第一颜色子 像素的所述第二电极和至少一个所述第三颜色子像素的所述第二电极在所述第三方向上均与所述发光控制信号线交叠。
  17. 根据权利要求16所述的显示基板，其中，至少一个所述第一颜色子像素的所述第二电极包括分别位于所述发光控制信号线两侧的第一电极子部和第二电极子部，所述第一电极子部的面积大于所述第二电极子部的面积；
    至少一个所述第一颜色子像素中，所述第二连接孔在所述衬底基板上的正投影的中心和所述第一电极子部在所述衬底基板上的正投影分别位于所述发光控制信号线在所述衬底基板上的正投影的两侧。
  18. 根据权利要求1-17任一项所述的显示基板，其中，在至少一个所述子像素中，所述像素电路还包括存储电容，所述存储电容的第二极复用为所述驱动晶体管的栅极，至少一个所述第一颜色子像素的所述存储电容的第二极的面积与至少一个所述第二颜色子像素的所述存储电容的第二极的面积不同。
  19. 根据权利要求18所述的显示基板，其中，至少一个所述第一颜色子像素的所述第二电极的面积大于至少一个所述第二颜色子像素的所述第二电极的面积，且至少一个所述第一颜色子像素的所述存储电容的第二极的面积大于至少一个所述第二颜色子像素的所述存储电容的第二极的面积。
  20. 根据权利要求18或19所述的显示基板，其中，至少一个所述第二颜色子像素中，所述存储电容的第一极在所述第三方向上与所述连接结构交叠。
  21. 根据权利要求9-11任一项所述的显示基板，其中，在至少一个子像素中，所述子像素的所述驱动晶体管的沟道包括依次连接的多个沟道子部，所述多个沟道子部中的至少部分沿所述第一方向延伸，且沿所述第一方向延伸的两个沟道子部在所述第二直线上的正投影没有交叠。
  22. 根据权利要求21所述的显示基板，其中，所述多个沟道子部包括依次连接的五个沟道子部，所述五个沟道子部中的三个沟道子部沿所述第一方向延伸，所述三个沟道子部中的两个沟道子部在所述第二直线上的正投影没有交叠，在所述第一直线上的正投影交叠，所述五个沟道子部中除所述三个沟道子部外的两个沟道子部在所述第一直线上的正投影交叠。
  23. 根据权利要求22所述的显示基板，其中，所述五个沟道子部包括依次连接的第一沟道子部、第二沟道子部、第三沟道子部、第四沟道子部以及第五沟道子部，所述第一沟道子部、所述第三沟道子部以及所述第五沟道子部沿所述第一方向延伸，所述第一沟道子部与所述第三沟道子部彼此平行，所述第一沟道子部和所述第五沟道子部被沿所述第一方向延伸的第三直线穿过且在所述第二直线上的正投影没有交叠，所述第二沟道子部和所述第四沟道子部沿所述第二方向延伸且彼此平行。
  24. 根据权利要求10或11所述的显示基板，还包括：
    位于各所述子像素的所述第二电极远离所述衬底基板一侧的像素限定层，其中，所述像素限定层包括用于限定各子像素的发光区的开口，各所述子像素的所述有机发光层 的至少部分位于所述开口内，所述像素限定层的开口在所述衬底基板上的正投影位于各所述子像素的所述第二电极的所述主体电极在所述衬底基板上的正投影内；
    所述像素限定层中，限定各所述第三颜色子像素的发光区的开口的面积大于限定各所述第二颜色子像素的发光区的开口的面积，且小于限定各所述第一颜色子像素的发光区的开口的面积。
  25. 根据权利要求1-24任一项所述的显示基板，其中，至少一个所述第一颜色子像素的所述第二电极在所述第三方向上与所述数据线交叠，且交叠部分沿所述第二方向的长度大于所述第二电极沿所述第二方向的最大长度的80％。
  26. 根据权利要求1-25任一项所述的显示基板，其中，至少一个所述第一颜色子像素的所述第二电极在所述第三方向上与所述电源线交叠，且交叠部分沿所述第二方向的长度大于所述第二电极沿所述第二方向的最大长度的80％。
  27. 根据权利要求1-26任一项所述的显示基板，其中，在至少一个所述第二颜色子像素中，所述第一连接孔在所述衬底基板上的正投影具有第一面积，所述第二连接孔在所述衬底基板上的正投影具有第二面积，所述第一面积和所述第二面积不同。
  28. 根据权利要求1-27任一项所述的显示基板，其中，在至少一个所述第二颜色子像素中，所述第一连接孔在所述第二方向上到所述发光控制信号线具有第一距离，所述第二连接孔在所述第二方向上到所述发光控制信号线具有第二距离，所述第一距离和所述第二距离不同。
  29. 一种显示装置，包括权利要求1-28任一项所述的显示基板。
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