WO2023001205A1 - 显示面板、显示装置以及显示面板的控制方法 - Google Patents

显示面板、显示装置以及显示面板的控制方法 Download PDF

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Publication number
WO2023001205A1
WO2023001205A1 PCT/CN2022/106878 CN2022106878W WO2023001205A1 WO 2023001205 A1 WO2023001205 A1 WO 2023001205A1 CN 2022106878 W CN2022106878 W CN 2022106878W WO 2023001205 A1 WO2023001205 A1 WO 2023001205A1
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sub
light control
substrate
pixel electrode
light
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PCT/CN2022/106878
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English (en)
French (fr)
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牟鑫
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to CN202280002279.XA priority Critical patent/CN115917418A/zh
Publication of WO2023001205A1 publication Critical patent/WO2023001205A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1347—Arrangement of liquid crystal layers or cells in which the final condition of one light beam is achieved by the addition of the effects of two or more layers or cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details

Definitions

  • At least one embodiment of the present disclosure relates to a display panel, a display device, and a control method of the display panel.
  • organic light-emitting diode Organic Light-Emitting Diode, OLED
  • LCD liquid crystal display
  • OLED Organic Light-Emitting Diode
  • At least one embodiment of the present disclosure provides a display panel, which includes a display substrate and a light control panel.
  • the display substrate includes a first substrate and a plurality of sub-pixels disposed on the main surface of the first substrate, each of the plurality of sub-pixels has a first opening, and light for generating a display image passes through the first substrate.
  • An opening emits light; the light control panel and the display substrate are stacked in a direction perpendicular to the main surface of the first substrate, including a plurality of sub-light control units, each of which has a second opening , the plurality of sub-light control units corresponds to the plurality of sub-pixels one by one, and the light emitted from the first opening passes through the second openings of at least some of the sub-light control units in the plurality of sub-light control units at least part of the light control sub-units in the plurality of light control sub-units are configured to modulate the light emitted from the first opening; the second opening of each of the light control sub-units is The orthographic projection on the main surface of the first substrate substantially overlaps the orthographic projection of the corresponding first opening of the sub-pixel on the main surface of the first substrate.
  • the orthographic projection of the second opening of each of the sub-light control units on the main surface of the first substrate includes The area of the part where the orthographic projection of the first opening of the pixel on the main surface of the first substrate overlaps with the area of the corresponding orthographic projection of the first opening of the sub-pixel on the main surface of the first substrate
  • the area ratio is greater than or equal to 80%.
  • the orthographic projection of the second opening of each of the sub-light control units on the main surface of the first substrate and the corresponding sub-pixel completely coincide.
  • the light control panel is a liquid crystal panel, and each of the plurality of sub light control units further includes a pixel electrode, liquid crystal molecules, a common electrode, and a light control transistor;
  • the light control panel also includes light control grid lines and light control data lines.
  • the light control gate line extends along the row direction, and is electrically connected to the gate of the light control transistor to provide the light control gate signal to the light control transistor;
  • the light control data line extends along the column direction, and is connected to the gate of the light control transistor.
  • the first pole of the phototransistor is electrically connected to provide the light control data signal to the phototransistor; the second pole of the phototransistor is electrically connected to the pixel electrode, and the liquid crystal molecules are configured to be able to Under the action of an electric field between the pixel electrode and the common electrode, the light emitted from the first opening is modulated; in each of the sub-light control units, the second opening exposes at least part of the pixel electrodes.
  • each of the plurality of sub-pixels includes a driving transistor and a light emitting element, and the driving transistor is configured to control the magnitude of a driving current flowing through the light emitting element,
  • the light emitting element is configured to receive the driving current and be driven by the driving current to emit light, and includes a first electrode; in each of the sub-pixels, the first opening exposes at least part of the first electrode;
  • the orthographic projection of the pixel electrode on the main surface of the first substrate substantially coincides with the orthographic projection of the corresponding first electrode of the sub-pixel on the main surface of the first substrate.
  • the orthographic projection of the phototransistor of each sub-light control unit on the main surface of the first substrate The orthographic projections of the first openings of the sub-pixels on the main surface of the first substrate do not overlap, and are on the first substrate with the second openings of the plurality of sub-light control units of the light control panel.
  • the orthographic projections on the principal surfaces of the base do not overlap.
  • the orthographic projection of the light control grating lines on the main surface of the first substrate is consistent with the first openings of the plurality of sub-pixels of the display substrate
  • the orthographic projections on the main surface of the first substrate do not overlap, and are identical to the second openings of the plurality of sub-light control units of the light control panel on the main surface of the first substrate Orthographic projections do not overlap.
  • the plurality of sub-light control units are arranged into a light control array;
  • the light control array includes a plurality of light control units arranged in an array, and one light control unit It includes a plurality of sub-light control units arranged continuously;
  • the light control array includes light control rows extending along the row direction and light control columns extending along the column direction, the row direction intersects the column direction, the Both the light control row and the light control column include a plurality of light control units;
  • the light control row includes a first light control row and a second light control row adjacent to each other, and the light control row
  • the orthographic projection of the optical control grid line that provides the optical control gate signal on the main surface of the first substrate, and the optical control transistors of the plurality of sub optical control units of the first optical control row on the first substrate
  • the orthographic projection on the main surface of the substrate is the same as the orthographic projection of the second openings of the plurality of sub-light control units located in the first light control row on the main
  • the plurality of sub-light control units are arranged into a light control array;
  • the light control array includes a plurality of light control units arranged in an array, and one light control unit It includes a plurality of sub-light control units arranged continuously;
  • each of the light control units includes a first edge extending along the column direction, and the plurality of sub-light control units of each light control unit is in the row direction Arranging and including the edge sub-light control unit closest to the first edge;
  • the light control data line that is located at the first edge and provides the light control data signal to the edge sub-light control unit is in the
  • the orthographic projection on the main surface of the first substrate does not overlap with the orthographic projection of the second openings of all sub-light control units of each light control unit on the main surface of the first substrate, and is consistent with the Orthographic projections of the first openings of the sub-pixels corresponding to all the sub-light control units on the main surface of the first substrate do not overlap.
  • each of the plurality of sub-light control units further includes a light-control storage capacitor
  • the light-control storage capacitor includes a first plate and a second plate.
  • the first pole plate is the pixel electrode; the second pole plate is arranged on the same layer as the light control gate line and is electrically connected to the light control gate line that provides the light control gate signal to the sub-light control unit;
  • the second pole plate of the light control storage capacitor protrudes from the light control gate line electrically connected to it along the column direction and protrudes from the light control gate line, at least the second pole plate in the column direction
  • An orthographic projection on the main surface of the first substrate of an end portion of the photogrid line away from the electrical connection thereto overlaps with an orthographic projection of the pixel electrode on the main surface of the first substrate.
  • the plurality of sub-light control units of each of the light control units includes a first sub-light control unit, a second sub-light control unit, and a second light control unit sequentially arranged in the row direction.
  • the light emitting colors of the sub-pixels corresponding to the first sub-light control unit, the second sub-light control unit and the third sub-light control unit are different from each other;
  • the distance between the phototransistor of the first sub-photocontrol unit and the phototransistor of the second sub-photocontrol unit in the row direction is the first distance, and the distance between the phototransistor of the second sub-photocontrol unit and the third phototransistor
  • the distance between the light control transistors of the sub light control units in the row direction is a second distance; the second distance is greater than the first distance.
  • the pixel electrode electrically connected to the second electrode of the phototransistor of the first sub-light control unit is the first pixel electrode
  • the second The pixel electrode electrically connected to the second pole of the phototransistor of the sub-light control unit is the second pixel electrode
  • the pixel electrode electrically connected to the second pole of the phototransistor of the third sub-light control unit is The third pixel electrode; the first pixel electrode and the second pixel electrode are arranged at intervals in the column direction, and the whole formed by the first pixel electrode and the second pixel electrode and the third pixel electrode Arranged in the row direction; the first pixel electrode and the second pixel electrode both cover the phototransistor of the first sub-light control unit and the phototransistor of the second sub-light control unit in the At least part of the interval in the row direction, and at least part of the interval in the row direction between the phototransistor of the second sub-light control unit and the phototransistor of the
  • the second pixel electrode is located in the column direction away from the gate of the first pixel electrode that provides the light control unit with the light control gate signal.
  • the distance between the third pixel electrode in the column direction and the gate line that provides the light control gate signal to the light control unit is greater than that of the first pixel electrode in the column direction
  • the distance between the light control unit and the gate line that provides the light control gate signal; the length of the second plate of the light control storage capacitor of the second sub light control unit in the column direction is longer than the The length of the second plate of the light-controlled storage capacitor of the third sub-light control unit in the column direction, and the second plate of the light-control storage capacitor of the third sub-light control unit is in the column direction
  • the length is greater than the length of the second plate of the light-controlled storage capacitor of the first sub-light control unit in the column direction.
  • the size of the third pixel electrode in the column direction is larger than the size of the second pixel electrode in the column direction, and is larger than the size of the second pixel electrode in the column direction.
  • the size of a pixel electrode in the column direction; and, the orthographic projection of the third pixel electrode in the column direction at least partially overlaps with the orthographic projection of the first pixel electrode in the column direction and is Orthographic projections of the second pixel electrodes in the column direction are at least partially overlapped.
  • the phototransistor of the first sub-light control unit, the phototransistor of the second sub-light control unit, and the phototransistor of the third sub-light control unit are basically arranged on a straight line extending along the row direction, and the size of the second pole of the phototransistor of the second sub-photocontrol unit in the column direction is larger than that of the third sub-photocontrol unit.
  • the size of the second pole of the phototransistor in the column direction is larger than the size of the second pole of the phototransistor of the third sub-light control unit in the column direction.
  • the size of the second pole of the phototransistor in the column direction is arranged on a straight line extending along the row direction, and the size of the second pole of the phototransistor of the second sub-photocontrol unit in the column direction is larger than that of the third sub-photocontrol unit.
  • the second pole of the phototransistor of the second sub-light control unit includes an extension part extending along the column direction, and the extension part
  • An orthographic projection on the main surface of a substrate is located between an orthographic projection of the second opening of the first sub-light control unit on the main surface of the first substrate and the second opening of the third sub-light control unit. Openings are between orthographic projections on the main surface of the first substrate.
  • the pixel electrode electrically connected to the second electrode of the phototransistor of the first sub-light control unit is the first pixel electrode
  • the second The pixel electrode electrically connected to the second pole of the phototransistor of the sub-light control unit is the second pixel electrode
  • the pixel electrode electrically connected to the second pole of the phototransistor of the third sub-light control unit is The third pixel electrode; the first pixel electrode and the second pixel electrode are arranged at intervals in the row direction, and the size of the second pixel electrode in the row direction is larger than that of the first pixel electrode in the row direction an upward dimension
  • the first pixel electrode covers at least part of the space between the phototransistor of the first sub-light control unit and the phototransistor of the second sub-light control unit in the row direction, so
  • the second pixel electrode covers at least part of the space between the phototransistors of the second sub-light control unit and the phototransistors of the third sub-light
  • the whole formed by the first pixel electrode and the second pixel electrode and the third pixel electrode are arranged in the column direction, and the third pixel electrode
  • the pixel electrode is located on the side of the whole formed by the first pixel electrode and the second pixel electrode in the column direction away from the gate line that provides the light control gate signal to the light control unit; the third The length of the second plate of the light-controlled storage capacitor of the sub-light control unit in the column direction is greater than the length of the second plate of the light-control storage capacitor of the first sub-light control unit in the column direction, And longer than the length of the second plate of the light-controlled storage capacitor of the second sub-light control unit in the column direction.
  • the size of the third pixel electrode in the row direction is larger than the size of the second pixel electrode in the row direction, and the third pixel electrode
  • the orthographic projection in the row direction at least partially overlaps with the orthographic projection of the first pixel electrode in the row direction and at least partially overlaps with the orthographic projection of the second pixel electrode in the row direction.
  • the positive side on the main surface of the first substrate of the light control data line that provides the light control data signal to the second sub light control unit The projection is located between the orthographic projection of the first pixel electrode on the main surface of the first substrate and the orthographic projection of the second pixel electrode on the main surface of the first substrate, and with the The orthographic projection of the third pixel electrode on the main surface of the first substrate overlaps; the optical control data line that provides the optical control data signal to the third sub-light control unit an orthographic projection on the main surface overlaps an orthographic projection of the second pixel electrode on the main surface of the first substrate with an orthographic projection of the second pixel electrode on the main surface of the first substrate, and overlap with the orthographic projection of the third pixel electrode on the main surface of the first substrate.
  • the phototransistor of the first sub-light control unit, the phototransistor of the second sub-light control unit, and the phototransistor of the third sub-light control unit The phototransistors are basically arranged on a straight line extending along the row direction, and the size of the second pole of the phototransistor of the third sub photocontrol unit in the column direction is larger than that of the first sub photocontrol unit
  • the orthographic projection of the end of the second electrode of the phototransistor close to the third pixel electrode on the main surface of the first substrate is the same as that of the third pixel electrode on the main surface of the first substrate
  • the orthographic projection on the main surface of the first substrate is overlapped with the orthographic projection of the second pole of the phototransistor of the third sub-optical control unit, and the
  • the area of the orthographic projection of the first pixel electrode on the main surface of the first substrate is smaller than that of the second pixel electrode on the first substrate.
  • the area of the orthographic projection on the main surface of the bottom, and the area of the orthographic projection of the second pixel electrode on the main surface of the first substrate is smaller than the main surface of the third pixel electrode on the first substrate.
  • the sub-pixel corresponding to the first sub-light control unit emits red light
  • the sub-pixel corresponding to the second sub-light control unit emits green light
  • the sub-pixel corresponding to the third sub-light control unit emits blue light.
  • the liquid crystal panel includes a second substrate and a third substrate opposite to the second substrate, the second substrate and the first substrate
  • the three substrates are stacked with the display substrate in a direction perpendicular to the main surface of the first substrate, and the third substrate is located on a side of the second substrate far away from the first substrate. side, the liquid crystal molecules are sandwiched between the second substrate and the third substrate, the phototransistor is located on the second substrate; the pixel electrode is located on the second substrate On the bottom, the common electrode is located on the third substrate; or, the pixel electrode is located on the third substrate, and the common electrode is located on the second substrate.
  • At least one embodiment of the present disclosure further provides a display device including any display panel provided by the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a control method of a display panel, the control method includes: using at least some pairs of sub-light control units in the plurality of sub-light control units of the light control panel The emitted light is modulated, so that the light emitted from the first opening passes through the second openings of at least some of the sub-light control units in the plurality of sub-light control units and then exits the display panel.
  • the display panel includes a first edge display area close to the first edge of the display panel, a second edge display area close to the second edge of the display panel area and an intermediate display area located between the first edge display area and the first edge display area and the second edge display area, the first edge is opposite to the second edge;
  • the distance from the first edge display area to the eye box of the observer of the display panel is smaller than the distance from the second edge display area to the eye box of the observer of the display panel;
  • the control The method includes: controlling the deflection direction of the light emitted from the first opening in the first edge display area after being modulated by the sub-light control unit and the direction of light emitted from the first opening in the second edge display area
  • the deflection direction of the emitted light modulated by the sub-light control unit is opposite, and the light emitted from the first opening in the middle display area is controlled not to be deflected after being modulated by the sub-light control unit
  • FIG. 1A is a partial plan view of a display substrate in a display panel provided by an embodiment of the present disclosure
  • FIG. 1B is a partial plan view of an optical control panel stacked with the display substrate shown in FIG. 1A in a display panel according to an embodiment of the present disclosure
  • FIG. 1C is a partial schematic plan view of a display panel provided by an embodiment of the present disclosure, the display panel includes the display substrate shown in FIG. 1A and the light control panel shown in FIG. 1B stacked on each other;
  • FIG. 2 is a schematic cross-sectional view of a sub-light control unit of the display panel shown in FIG. 1C and its corresponding sub-pixel;
  • FIG. 3 is a circuit diagram of a sub-light control unit of a display panel provided by an embodiment of the present disclosure
  • 4A-4H are schematic diagrams of layers of multiple sub-light control units of the light control panel of the display panel provided by an embodiment of the present disclosure
  • FIG. 4I is the structure after removing the pixel electrode in FIG. 4H;
  • FIG. 5 is a schematic circuit diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 6A to 11A are partial schematic views of various layers of a display substrate provided by an embodiment of the present disclosure, and FIG. 6B is a partial enlarged view of FIG. 6A;
  • 11B is a schematic diagram of partial film layers of multiple pixel groups of a display substrate provided by an embodiment of the present disclosure
  • Fig. 12 is a partial cross-sectional view at a position of a display substrate provided by an embodiment of the present disclosure
  • Fig. 13 is a partial cross-sectional view of another position of the display substrate provided by an embodiment of the present disclosure.
  • 14A-14E are partial schematic diagrams of various layers of a display substrate in another display panel provided by an embodiment of the present disclosure.
  • FIG. 15A is a partial plan view of a display substrate in another display panel provided by an embodiment of the present disclosure.
  • FIG. 15B is a partial plan view of a light control panel stacked with the display substrate shown in FIG. 15A in another display panel according to an embodiment of the present disclosure
  • FIG. 16 is an application schematic diagram of a display device provided by an embodiment of the present disclosure.
  • the component may be one or more, or may be understood as at least one. "At least one” means one or more, and “plurality” means at least two.
  • the “same-layer setting” in the embodiments of the present disclosure refers to the relationship between multiple film layers formed after performing the same step (for example, the same patterning process) on the film layers formed of the same material.
  • the "arranged in the same layer” here does not always mean that the multiple film layers have the same thickness or that the multiple film layers have the same height in the cross-sectional view.
  • substantially overlap and the like include certain errors, taking into account the measurement and the error associated with the measurement of a specific quantity (for example, the limitation of the measurement system), and means that it is determined by one of ordinary skill in the art for a specific value.
  • the value is within the acceptable deviation range.
  • substantially can mean within one or more standard deviations, and may mean within 10% or 5% of the stated value unless otherwise specified.
  • At least one embodiment of the present disclosure provides a display panel, which includes a display substrate and a light control panel.
  • the display substrate includes a first substrate and a plurality of sub-pixels disposed on the main surface of the first substrate, each of the plurality of sub-pixels has a first opening, and light for generating a display image passes through the first substrate.
  • An opening emits light; the light control panel and the display substrate are stacked in a direction perpendicular to the main surface of the first substrate, including a plurality of sub-light control units, each of which has a second opening , the plurality of sub-light control units corresponds to the plurality of sub-pixels one by one, and the light emitted from the first opening passes through the second openings of at least some of the sub-light control units in the plurality of sub-light control units at least part of the light control sub-units in the plurality of light control sub-units are configured to modulate the light emitted from the first opening; the second opening of each of the light control sub-units is The orthographic projection on the main surface of the first substrate substantially overlaps the orthographic projection of the corresponding first opening of the sub-pixel on the main surface of the first substrate.
  • At least one embodiment of the present disclosure further provides a display device including any display panel provided by the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a control method of a display panel, the control method includes: using at least some pairs of sub-light control units in the plurality of sub-light control units of the light control panel The emitted light is modulated, so that the light emitted from the first opening passes through the second openings of at least some of the sub-light control units in the plurality of sub-light control units and then exits the display panel.
  • FIG. 1A is a partial plan view of a display substrate in a display panel provided by an embodiment of the present disclosure
  • FIG. 1B is a display substrate shown in FIG. 1A in a display panel provided by an embodiment of the present disclosure.
  • FIG. 1C is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes the display substrate shown in FIG. 1A and the light control panel shown in FIG. Control panel
  • FIG. 2 is a schematic cross-sectional view of a sub-light control unit of the display panel shown in FIG. 1C and its corresponding sub-pixel. As shown in FIGS. 1A-1C and FIG.
  • the display panel 10 includes a display substrate 01 and a light control panel 02 .
  • the display substrate 01 includes a first substrate 1 a and a plurality of sub-pixels PU1 / PU2 / PU3 disposed on the main surface 11 of the first substrate 1 a.
  • Each of the plurality of sub-pixels PU1/PU2/PU3 has a first opening.
  • a plurality of sub-pixels PU1/PU2/PU3 are arranged into a pixel array;
  • the pixel array includes a plurality of pixel units PU arranged in an array, and one pixel unit PU includes a plurality of sub-pixels PU1/PU2/PU3 arranged continuously;
  • the pixel array includes A pixel row extending in a direction X and a pixel column extending in a column direction Y, where the row direction X intersects the column direction Y, each of the pixel row and the pixel column includes a plurality of pixel units PU.
  • each pixel unit PU includes a first sub-pixel PU1 , a second sub-pixel PU2 and a third sub-pixel PU3 , and light for generating a display image is emitted from the first opening of the display substrate 01 to the light control panel 02 .
  • the first sub-pixel PU1 has a first opening OP1
  • the second sub-pixel PU2 has a first opening OP2
  • the third sub-pixel PU3 has a first opening OP3.
  • the light control panel 02 and the display substrate 01 are stacked in a direction perpendicular to the main surface 11 of the first substrate 1a, and include a plurality of sub-light control units CU1/CU2/CU3, and a plurality of sub-light control units CU1
  • Each of /CU2/CU3 has a second opening.
  • a plurality of sub-light control units CU1/CU2/CU3 are arranged into a light control array; the light control array includes a plurality of light control units CU arranged in an array, and each light control unit CU includes a plurality of sub-light control units CU1/CU3 arranged in succession.
  • each light control unit CU includes a first sub-light control unit CU1, a second sub-light control unit CU2 and a third sub-light control unit CU3; the first sub-light control unit CU1 has a second opening COP1, the second sub-light control unit CU1 The second light control unit CU2 has a second opening COP2, and the third light control unit CU3 has a second opening COP3.
  • the light control array includes light control rows extending along the row direction X and light control columns extending along the column direction Y, both of which include a plurality of light control units CU.
  • the multiple sub-light control units CU1/CU2/CU3 of the light control panel 02 correspond one-to-one to the multiple sub-pixels PU1/PU2/PU3 of the display substrate 01, and the light emitted from the first opening passes through the multiple sub-light control units CU1/CU2/CU3 At least some of the sub-light control units in the second openings are then output from the display panel 10, and at least some of the sub-light control units CU1/CU2/CU3 are configured to modulate the light emitted from the first openings.
  • the orthographic projection of the second opening of each sub-light control unit on the main surface 11 of the first substrate 1 a substantially overlaps the orthographic projection of the first opening of the corresponding sub-pixel on the main surface 11 of the first substrate 1 a.
  • the orthographic projection of the second opening COP1 of the first sub-light control unit CU1 on the main surface 11 of the first substrate 1a is the same as the first opening OP1 of the first sub-pixel PU1 on the main surface 11 of the first substrate 1a
  • the orthographic projection of the second sub-pixel PU2 substantially overlaps; the orthographic projection of the second opening COP2 of the second sub-light control unit CU2 on the main surface 11 of the first substrate 1a and the first opening OP2 of the second sub-pixel PU2 on the first substrate 1a
  • the orthographic projection on the main surface 11 basically overlaps; the orthographic projection of the second opening COP3 of the third sub-light control unit CU3 on the main surface 11 of the first substrate 1a is on the first opening OP3 of the third sub-pixel PU3.
  • the orthographic projections on the main surface 11 of the substrate 1 a substantially overlap. In this way, while adjusting the light emitting direction of the display substrate 01 , the aperture ratio of the entire display panel 10 can be increased to avoid or reduce the reduction of the light emitting rate of the display substrate 01 due to the installation of the light control panel 02 .
  • each light control unit includes three sub-light control units and each pixel includes three sub-pixels is taken as an example.
  • each light control unit includes the number of sub-light control units, and each The number of sub-pixels included in each pixel is not limited to three, and may be less than three or more than three, which can be selected by those skilled in the art according to specific needs.
  • the liquid crystal panel includes a light control driving circuit configured to independently control the modulation of light from the display substrate 01 by multiple areas of the liquid crystal panel, so as to realize independent dimming in different areas.
  • the orthographic projection of the second opening of each of the sub-light control units CU1/CU2/CU3 on the main surface 11 of the first substrate 1a includes The ratio of the area of the overlapping part of the orthographic projection on the main surface 11 of the bottom 1a to the area of the orthographic projection of the first opening of the corresponding sub-pixel on the main surface 11 of the first substrate 1a is greater than or equal to 80%, so as to ensure that While adjusting the light output direction of the display substrate 01 , the entire display panel 10 has a higher aperture ratio, which can better avoid or reduce the reduction of the light output rate of the display substrate 01 due to the installation of the light control panel 02 .
  • the orthographic projection of the second opening of each sub-light control unit on the main surface 11 of the first substrate 1a is the same as the orthographic projection of the first opening of the corresponding sub-pixel on the main surface 11 of the first substrate 1a.
  • the projections are completely coincident.
  • the orthographic projection of the second opening COP1 of the first sub-light control unit CU1 on the main surface 11 of the first substrate 1a is the same as the first opening OP1 of the first sub-pixel PU1 on the main surface 11 of the first substrate 1a
  • the orthographic projection of the second sub-pixel PU2 completely overlaps; the orthographic projection of the second opening COP2 of the second sub-light control unit CU2 on the main surface 11 of the first substrate 1a and the first opening OP2 of the second sub-pixel PU2 on the first substrate 1a
  • the orthographic projection on the main surface 11 completely overlaps; the orthographic projection of the second opening COP3 of the third sub-light control unit CU3 on the main surface 11 of the first substrate 1a is on the first opening OP3 of the third sub-pixel PU3.
  • the orthographic projections on the main surface 11 of the substrate 1a are completely overlapped to ensure that the display panel 10 has a higher aperture ratio, and better modulate the light output of the display panel 10 while increasing the light extraction
  • the light control panel 02 is a liquid crystal panel
  • the liquid crystal panel includes a second substrate 1b, a third substrate 1c disposed opposite to the second substrate 1b, and a third substrate 1c sandwiched between the second substrate 1b.
  • the liquid crystal layer LC includes liquid crystal molecules LCM.
  • Both the second substrate 1b and the third substrate 1c are stacked with the display substrate 01 in a direction perpendicular to the main surface 11 of the first substrate 1a, and the third substrate 1c is located on the side of the second substrate 1b away from the first substrate.
  • each of the plurality of sub light control units CU1/CU2/CU3 further includes a pixel electrode CE1, a common electrode ComE and a light control transistor Tc.
  • FIGS. 4A-4H are schematic diagrams of the layers of multiple light control sub-units of the light control panel of the display panel provided by an embodiment of the present disclosure;
  • FIG. 4I is the structure after removing the pixel electrode in FIG. 4H .
  • the light control panel 02 also includes light control gate lines CGL and light control data lines CDL.
  • the light control gate line CGL extends along the row direction X, and is electrically connected to the gate GATE of the light control transistor Tc to provide the light control gate signal to the light control transistor Tc;
  • the light control data line CDL extends along the column direction Y, and is connected to the light control transistor Tc.
  • the first pole Sc (for example, the source) of the transistor Tc is electrically connected to provide the light control data signal to the light control transistor Tc.
  • the second pole Dc (such as the drain) of the light control transistor Tc is connected to the
  • the pixel electrodes are electrically connected to charge the pixel electrodes when the phototransistor Tc is in the conduction state; the liquid crystal molecules LCM are configured to rotate under the action of the electric field between the pixel electrodes and the common electrode ComE, so as to charge the light emitted from the first opening
  • the light is modulated, where the modulation of the light emitted from the first opening includes the adjustment of the light output direction and/or light intensity;
  • the common electrode ComE, the pixel electrode and the liquid crystal layer LC together form a liquid crystal capacitor C LC , when the pixel electrode is charged , an electric field is formed between the common electrode ComE and the pixel electrode to control the rotation of the liquid crystal molecules LCM in the liquid crystal layer LC.
  • the light control grid line CGL and the light control data line CDL are configured to distribute and provide the light control gate signal and the light control data signal for driving the rotation of the liquid crystal molecules LCM in the light control unit of the light control panel 02, so as to realize light control
  • the panel 02 adjusts the emission angle or intensity of the light emitted from the display substrate 01 .
  • each phototransistor further includes a gate GATE and a semiconductor layer ACTIVE
  • the liquid crystal panel 02 further includes a gate insulating layer GI between the gate GATE and the semiconductor layer ACTIVE.
  • the liquid crystal panel 02 also includes an alignment layer AL for controlling the initial alignment of the liquid crystal molecules.
  • the setting of the alignment layer AL and other components of the liquid crystal panel not mentioned can refer to conventional technologies.
  • the pixel electrode connected to the second pole Dc (D1 in FIG. 4D) of the phototransistor Tc of the first sub-light control unit CU1 is the first pixel electrode CE1, and is connected to the second pole Dc of the phototransistor Tc of the first sub-light control unit CU1.
  • the pixel electrode connected to the second pole Dc (D2 in FIG. 4D ) of the phototransistor Tc of CU2 is the second pixel electrode CE2, which is connected to the second pole Dc (D2 in FIG. 4D ) of the phototransistor Tc of the third sub-light control unit CU3.
  • the electrode D3) in is the third pixel electrode CE3. As shown in FIG.
  • the second opening exposes at least part of the pixel electrode.
  • the second opening COP1 of the first photo-control unit CU1 exposes a part of the first pixel electrode CE1
  • the second opening COP2 of the second photo-control unit CU2 exposes a part of the second pixel electrode CE2
  • the photo-control sub-unit CU2 exposes a part of the second pixel electrode CE2.
  • the second opening COP3 of CU3 exposes a portion of the third pixel electrode CE3.
  • the area of the pixel electrode is larger than the area of the second opening; for example, in each sub-pixel, the area of the first electrode is larger than the area of the first opening.
  • each of the plurality of sub-pixels PU1/PU2/PU3 includes a driving transistor T1 and a light emitting element 220
  • the driving transistor T1 is configured to control the magnitude of the driving current flowing through the light emitting element 220
  • the light emitting element 220 is configured to To receive a driving current and be driven by the driving current to emit light.
  • the light emitting element 220 is an organic light emitting element
  • the sub-pixel includes a pixel circuit for driving the organic light emitting element
  • the pixel circuit includes a driving transistor T1 and the light emitting element 220 .
  • the organic light emitting element includes a first electrode E1 , a second electrode (not shown in FIG. 2 ) and an organic light emitting material 1 b between the first electrode E1 and the second electrode.
  • the first electrode E1 is an anode
  • the second electrode is a cathode such as a common cathode.
  • the first opening exposes at least part of the first electrode.
  • the first opening OP1 of the first sub-pixel PU1 exposes the first electrode E1 of the first sub-pixel PU1
  • the first opening OP2 of the second sub-pixel PU2 exposes the first electrode E2 of the second sub-pixel PU2
  • the third sub-pixel The first opening OP3 of PU3 exposes the first electrode E3 of the third sub-pixel PU3.
  • the orthographic projection of the pixel electrode on the main surface 11 of the first substrate 1a substantially coincides with the orthographic projection of the first electrode of the corresponding sub-pixel on the main surface 11 of the first substrate 1a, for example,
  • the orthographic projection of the first pixel electrode CE2 of the second sub-light control unit CU2 on the main surface 11 of the first substrate 1a basically coincides with that of the first electrode E2 of the corresponding second sub-pixel PU2 on the first substrate 1a.
  • the orthographic projections on the main surface 11 of the substrate 1a are substantially coincident, and the orthographic projections of the first pixel electrode CE3 of the third sub-light control unit CU3 on the main surface 11 of the first substrate 1a are the same as those of the corresponding third sub-pixel PU3.
  • the orthographic projections of the first electrode E3 on the main surface 11 of the first substrate 1a are substantially coincident.
  • the overlapping area of the orthographic projection of the pixel electrode of each sub-light control unit on the main surface 11 of the first substrate 1 a and the orthographic projection of the corresponding first electrode on the main surface 11 of the first substrate 1 a is the same as the The ratio of the area of the orthographic projection of the first electrode on the main surface 11 of the first substrate 1a is greater than or equal to 0.8, for example, 0.9, 0.95.
  • the orthographic projection of the pixel electrode on the main surface 11 of the first substrate 1a completely coincides with the orthographic projection of the first electrode of the corresponding sub-pixel on the main surface 11 of the first substrate 1a, that is, each sub-pixel
  • the overlapping area of the orthographic projection of the pixel electrode of the light control unit on the main surface 11 of the first substrate 1 a and the orthographic projection of the corresponding first electrode on the main surface 11 of the first substrate 1 a is the same as that of the first electrode on the main surface 11 of the first substrate 1 a.
  • the ratio of the area of the orthographic projection on the main surface 11 of the first substrate 1 a is 1, so as to maximize the aperture ratio of the display panel 10 .
  • the pixel electrodes, the common electrodes of the sub-light control units, and the first electrodes of the sub-pixels of the display substrate are all transparent to light.
  • the material of the pixel electrode and the common electrode of the sub-light control unit may be a transparent conductive material, such as ITO, IZO and the like.
  • the material of the first electrode may be a metal material, such as an anode material of a commonly used OLED light emitting device.
  • the embodiment of the present disclosure does not specifically limit the material type of each electrode, and those skilled in the art can select according to requirements.
  • the orthographic projection of the light-control transistor Tc of each sub-light control unit on the main surface 11 of the first substrate 1a is in the same direction as the first openings of the multiple sub-pixels PU1/PU2/PU3 of the display substrate 01.
  • the orthographic projections on the main surface 11 of the first substrate 1a are substantially non-overlapping, and are substantially different from the orthographic projections of the second openings of the plurality of sub-light control units of the light control panel 02 on the main surface 11 of the first substrate 1a.
  • the orthographic projection of the phototransistor Tc of each sub-light control unit on the main surface 11 of the first substrate 1a is the same as that of the first openings of the multiple sub-pixels PU1/PU2/PU3 of the display substrate 01 on the first substrate 1a.
  • the ratio of the overlapping area of the orthographic projection on the main surface 11 to the area of the orthographic projection of the phototransistor Tc on the main surface 11 of the first substrate 1a is less than or equal to 0.2, for example, 0.1, 0.05.
  • the entire orthographic projection of the phototransistor Tc of each sub-light control unit on the main surface 11 of the first substrate 1a is aligned with the first openings of the plurality of sub-pixels PU1/PU2/PU3 of the display substrate 01 in the first
  • the orthographic projections on the main surface 11 of the substrate 1a do not overlap, that is, the orthographic projections of the phototransistor Tc of each sub-light control unit on the main surface 11 of the first substrate 1a and the plurality of sub-pixels PU1/
  • the ratio of the overlapping area of the orthographic projection of the first opening of PU2/PU3 on the main surface 11 of the first substrate 1a to the area of the orthographic projection of the phototransistor Tc on the main surface 11 of the first substrate 1a is 0 , so as to maximize the aperture ratio of the display panel 10 .
  • FIG. 4A shows the first semiconductor layer ACTIE1 , the first semiconductor layer ACTIE1 , the first phototransistor Tc of the first sub-light control unit CU1 , the second sub-light control unit CU2 , and the third sub-light control unit CU3 included in one light control unit.
  • Fig. 4B shows the light control gate line CGL, and the second plates C21/C22/C23 of the light control storage capacitors of the first sub light control unit CU1, the second sub light control unit CU2 and the third sub light control unit CU3 .
  • FIG. 4C shows the superimposed structure of FIG. 4A and FIG. 4B.
  • the light control gate line CGL overlaps with the first semiconductor layer ACTIE1, the first semiconductor layer ACTIE2 and the third semiconductor layer ACTIE3 respectively to form the first sub-light control unit CU1,
  • Fig. 4D shows the light control data line CDL, and the second poles D1/D2/D3 of the light control transistors Tc of the first sub light control unit CU1, the second sub light control unit CU2 and the third sub light control unit CU3;
  • the light control data line CDL and the second pole D1/D2/D3 of the light control transistor Tc are arranged on the same layer.
  • Figure 4E shows the structure of Figure 4C and Figure 4D superimposed.
  • FIG. 4F shows the pixel electrodes CE1 / CE2 / CE3 of the first sub-light control unit CU1 , the second sub-light control unit CU2 and the third sub-light control unit CU3 .
  • Figure 4G shows the structure of Figure 4E superimposed on Figure 4F.
  • FIG. 4H shows a schematic view of FIG. 4G after superimposing the second openings COP1 / COP2 / COP3 of the first sub-light control unit CU1 , the second sub-light control unit CU2 and the third sub-light control unit CU3 .
  • FIG. 4I is the structure after the pixel electrode in FIG. 4H is removed.
  • the orthographic projection of the photogrid lines CGL on the main surface 11 of the first substrate 1a and the first openings of the plurality of sub-pixels PU1/PU2/PU3 of the display substrate 01 are on the first substrate 1a.
  • the optical control row includes the first optical control row R1 and the second optical control row R2 adjacent to each other, and the optical control gate line CGL that provides the optical control gate signal to the first optical control row R1 is The orthographic projection on the main surface 11 of the first substrate 1a, and the orthographic projection of the light control transistors Tc of the plurality of sub-light control units CU1/CU2/CU3 of the first light control row R1 on the main surface 11 of the first substrate 1a Projecting the orthographic projection of the second openings COP1/COP2/COP3 of the plurality of sub-light control units CU1/CU2/CU3 located in the first light control row R1 on the main surface 11 of the first substrate 1a and the second light control row R2 Between the orthographic projections of the second openings of the plurality of sub-light control units COP1/COP2/COP3 on the main surface 11 of the first substrate 1a, to prevent the light control grid line CGL from blocking the first opening and the second opening, further improving The aperture ratio of the
  • each light control unit includes a first edge extending along the column direction Y, and a plurality of sub-light control units CU1/CU2/CU3 of each light control unit are arranged in the row direction X and include The edge sub-light control unit closest to the first edge; the orthographic projection and The orthographic projections of the second openings of all the sub-light control units of each light control unit on the main surface 11 of the first substrate 1a do not overlap, and the first openings of the sub-pixels corresponding to all the sub-light control units are in the first The orthographic projections on the main surface 11 of the substrate 1a do not overlap, so that the light control data line CDL located at the first edge of each light control unit avoids the first opening and the second opening, thereby preventing the light control data line CDL located at the first edge of each light control unit The optical control data line CDL at the first edge of the control unit.
  • each of the plurality of light control sub-units CU1 / CU2 / CU3 further includes a light control storage capacitor C to better buffer signals and optimize the dimming effect.
  • the light-controlled storage capacitor C includes a first plate C1 and a second plate C2.
  • the first plate C1 is the pixel electrode; the second plate C2 is arranged on the same layer as the light control gate line CGL and is electrically connected to the light control gate line CGL that provides the light control gate signal to the sub-light control unit, such as the second plate C2 is set on the same layer as the light control gate line CGL and forms an integral molding structure with the light control gate line CGL that provides the light control gate signal to the sub light control unit, so that the light control gate line and the light control gate line can be formed by performing the same patterning process on the same film layer.
  • the second plate of the light-controlled storage capacitor simplifies the structure and manufacturing process of the display panel.
  • the multiple structures constituting the "integrated structure” means that the multiple structures are continuous and seamless and formed from the same material as a whole.
  • the layers are formed by performing the same patterning process.
  • the second plate C2 of the light-control storage capacitor C protrudes from the light-control gate line CGL electrically connected to the light-control gate line along the column direction Y.
  • CGL at least the orthographic projection of the end of the second plate C2 in the column direction Y away from the light control grid line CGL electrically connected to it on the main surface 11 of the first substrate 1a and the pixel electrode on the first substrate 1a
  • the orthographic projections on the main surface 11 overlap.
  • the orthographic projection of the second plate C21 of the storage capacitor C of the first sub-light control unit CU1 on the main surface 11 of the first substrate 1a is the same as the orthographic projection of the first pixel electrode CE1 on the main surface 11 of the first substrate 1a.
  • the projection overlaps, the orthographic projection of the second plate C22 of the storage capacitor C of the second sub-light control unit CU2 on the main surface 11 of the first substrate 1a is the same as that of the second pixel electrode CE2 on the main surface 11 of the first substrate 1a
  • the orthographic projection of the third sub-light control unit CU3 on the main surface 11 of the first substrate 1a of the second plate C23 of the storage capacitor C of the third sub-light control unit CU3 overlaps with that of the third pixel electrode CE3 on the first substrate 1a.
  • the orthographic projections on the main surface 11 overlap.
  • the plurality of sub-light control units CU1/CU2/CU3 of each light control unit includes a first sub-light control unit CU1, a second sub-light control unit CU2, and a third sub-light control unit CU3 arranged in sequence in the row direction X,
  • the light emitting colors of the sub-pixels corresponding to the first sub-light control unit CU1 , the second sub-light control unit CU2 and the third sub-light control unit CU3 are different from each other.
  • the distance between the phototransistor Tc of the first photocontrol unit CU1 and the phototransistor Tc of the second photocontrol unit CU2 in the row direction X is the first distance d1.
  • the distance between the light control transistor Tc of CU2 and the light control transistor Tc of the third sub light control unit CU3 in the row direction X is the second distance d2; to provide light control data of the light control data signal to the first sub light control unit CU1
  • the distance between the line CDL1 and the opposite sides of the light control data line CDL2 that provides light control data signals to the second light control unit CU2 is used as the first distance d1 to provide light control data to the second light control unit CU2
  • the distance between the optical control data line CDL2 for the signal and the opposite sides of the optical control data line CDL3 for providing the optical control data signal to the third sub-optical control unit CU3 is taken as the second distance d2.
  • the second distance d2 is not equal to the first distance d1.
  • the second distance d2 is greater than the first distance d1, so as to adapt to the arrangement of multiple sub-light control units of one light control unit and the different sizes of the multiple sub-light control units of one light control unit in the row direction.
  • the second plate C22 also overlaps with the second pole D2 of the phototransistor Tc, for example partially overlapped (in In other embodiments, the entire second plate C22 may overlap with the second pole D2 of the phototransistor Tc) to form another storage capacitor to better buffer signals and optimize the dimming effect.
  • the first pixel electrode CE1 and the second pixel electrode CE2 are arranged at intervals in the column direction Y, and the whole formed by the first pixel electrode CE1 and the second pixel electrode CE2 is in the same row as the third pixel electrode CE3.
  • the first pixel electrode CE1 and the second pixel electrode CE2 both cover the distance between the phototransistor Tc of the first sub-light control unit CU1 and the phototransistor Tc of the second sub-light control unit CU2 in the row direction X and at least part of the distance between the phototransistor Tc of the second sub-light control unit CU2 and the phototransistor Tc of the third sub-light control unit CU3 in the row direction X, and the third pixel electrode CE3 covers the second sub-light control unit CU3. At least part of the space in the row direction X between the light control transistor Tc of the light control unit CU2 and the light control transistor Tc of the third sub light control unit CU3 .
  • the area of the orthographic projection of the first pixel electrode CE1 on the main surface 11 of the first substrate 1a is smaller than the area of the orthographic projection of the second pixel electrode CE2 on the main surface 11 of the first substrate 1a, and the second pixel The area of the orthographic projection of the electrode CE2 on the main surface 11 of the first substrate 1a is smaller than the area of the orthographic projection of the third pixel electrode CE3 on the main surface 11 of the first substrate 1a.
  • the first pixel electrode CE1 and the second pixel electrode CE2 arranged in the column direction with a smaller area correspond to a smaller first distance d1
  • the third pixel electrode CE3 with a larger area corresponds to a larger second distance d2, which can minimize the waste of space and facilitate the realization of a high-PPI display panel.
  • the second pixel electrode CE2 is located on the side of the first pixel electrode CE1 in the column direction Y away from the gate line that provides the light control gate signal to the light control unit, and the third pixel electrode CE3 is in the column direction Y.
  • the distance in the direction Y from the gate line that provides the light control unit with the photocontrol gate signal is greater than the distance between the first pixel electrode CE1 in the column direction Y and the distance from the gate line that provides the light control unit with the light control gate signal ;
  • the length of the second plate C22 of the light-controlled storage capacitor C of the second sub-light control unit CU2 in the column direction Y is greater than the length of the second plate C23 of the light-controlled storage capacitor C of the third sub-light control unit CU3 in the column direction
  • the length in Y, and the length of the second pole plate C23 of the light-controlled storage capacitor C of the third sub-light control unit CU3 in the column direction Y is greater than the second pole of the light-control storage capacitor C of the first sub-light control unit CU1
  • the length of the plate C21 in the column direction Y is adapted to the positions of the first pixel electrode CE1 , the second pixel electrode CE2 and the third pixel electrode CE3 .
  • the size of the third pixel electrode CE3 in the column direction Y is larger than the size of the second pixel electrode CE2 in the column direction Y, and larger than the size of the first pixel electrode CE1 in the column direction Y; and
  • the orthographic projection of the third pixel electrode CE3 in the column direction Y at least partially overlaps the orthographic projection of the first pixel electrode CE1 in the column direction Y and at least partially overlaps the orthographic projection of the second pixel electrode CE2 in the column direction Y.
  • the phototransistor Tc of the first sub-light control unit CU1, the phototransistor Tc of the second sub-light control unit CU2, and the phototransistor Tc of the third sub-light control unit CU3 are basically arranged On a straight line extending along the row direction X, the size of the second electrode D2 of the phototransistor Tc of the second sub-photocontrol unit CU2 in the column direction Y is larger than that of the second pole D2 of the phototransistor Tc of the third sub-photocontrol unit CU3 .
  • the size of the pole D3 in the column direction Y, the size of the second pole D3 of the phototransistor Tc of the third sub-light control unit CU3 in the column direction Y is larger than the second pole D3 of the phototransistor Tc of the first sub-light control unit CU1
  • the size of the pole D1 in the column direction Y is adapted to the positions of the first pixel electrode CE1, the second pixel electrode CE2 and the third pixel electrode CE3, and the second pole D1, the second pole D2 and the second pole D3 are respectively used It is electrically connected with the first pixel electrode CE1, the second pixel electrode CE2 and the third pixel electrode CE3.
  • the second pole D1/D2/D3 of the phototransistor of each sub-light control unit includes an extension extending in the column direction, for example, the dimension of the extension of the diode D1 in the column direction Y is larger than that of the second The dimension of the extension of the pole D3 in the column direction Y, and the dimension of the extension of the second pole D3 in the column direction Y is larger than the dimension of the extension of the second pole D1 in the column direction Y.
  • the orthographic projection of the second pole D1/D2/D3 of the phototransistor Tc on the main surface 11 of the first substrate 1a is consistent with the second opening at
  • the orthographic projections on the main surface 11 of the first substrate 1 a do not overlap, so as to increase the aperture ratio of the display panel 10 as much as possible.
  • the "non-overlapping" includes not overlapping at all, or the overlapping area of the two occupies within 5%-10% of the area of the second opening.
  • the orthographic projection of the second pole D1/D2/D3 of the phototransistor Tc on the main surface 11 of the first substrate 1a does not overlap at all with the orthographic projection of the second opening on the main surface 11 of the first substrate 1a.
  • the orthographic projection of the extension portion D2E of the second pole D2 of the phototransistor Tc of the second photocontrol unit CU2 extending along the column direction Y on the main surface 11 of the first substrate 1a is located at
  • the orthographic projection of the second opening of the first sub-light control unit CU1 on the main surface 11 of the first substrate 1a is the same as that of the second opening of the third sub-light control unit CU3 on the main surface 11 of the first substrate 1a.
  • the non-display area between the whole composed of the first pixel electrode CE1 and the second pixel electrode CE2 and the third pixel electrode CE3 is used to set the extension part D2E, which utilizes the positional relationship of a plurality of sub-light control units, which is reasonable A limited space is utilized, thereby preventing the extension portion D2E from covering the first opening and the second opening, and further increasing the aperture ratio of the display panel 10 .
  • the arrangement of the plurality of first electrodes of the display substrate and the arrangement of the plurality of pixel electrodes of the light control panel are not limited to the above-mentioned arrangement, and can be designed as required, as long as the two are positive The projections overlap.
  • the pixel electrode CE1 of the sub-light control unit and the common electrode ComE may be respectively located on different substrates opposite to each other.
  • the pixel electrode CE1 of the sub-light control unit is located on the second substrate 1b, and the common electrode ComE is located on the third substrate 1c.
  • the pixel electrode is located on the third substrate 1c, and the common electrode ComE is located on the second substrate 1b.
  • the pixel electrode CE1 can form a TN type electric field with the common electrode ComE.
  • the arrangement of the pixel electrodes CE1 has a higher degree of freedom, which is more conducive to the second opening of the light control panel 02 and the first opening of the display substrate 01.
  • An opening coincides in the direction perpendicular to the main surface of the first substrate, and it is more conducive to the coincidence of the pixel electrode of the light control panel 02 and the first electrode of the display substrate 01 in the direction perpendicular to the main surface of the first substrate, which is easy
  • a higher overlap ratio is achieved, thereby obtaining a display panel 10 with a higher aperture ratio.
  • the electric field of the light control panel 02 of the present disclosure is not limited to the TN type.
  • the pixel electrode CE1 of the sub light control unit can also be located on the same substrate as the common electrode ComE, for example, both are located on the second substrate 1b
  • the pixel electrode CE1 and the common electrode ComE form an IPS type horizontal electric field.
  • the display substrate 01 may not adopt the arrangement of the first electrodes 11 / 12 / 13 shown in FIG. 7 , but may also adopt the arrangement of the first electrodes shown in FIG. 4H of the present disclosure.
  • the pixel circuit 221 includes a driving circuit 222 .
  • the driving circuit 222 includes a control terminal, a first terminal and a second terminal, and is configured to provide a driving current to the organic light emitting element 220 to drive the organic light emitting element 220 to emit light.
  • the pixel circuit 221 includes a first light emission control circuit 223 and a second light emission control circuit 224 .
  • the first light emission control circuit 223 is connected to the first terminal of the driving circuit 222 and the first voltage terminal VDD, and is configured to enable or disable the connection between the driving circuit 222 and the first voltage terminal VDD
  • the second The light emission control circuit 224 is electrically connected to the second terminal of the driving circuit 222 and the first electrode of the organic light emitting element 220 , and is configured to enable or disable the connection between the driving circuit 222 and the organic light emitting element 220 .
  • the pixel circuit 221 further includes a data writing circuit 226 , a storage circuit 227 , a threshold compensation circuit 228 and a reset circuit 229 .
  • the data writing circuit 226 is electrically connected to the first terminal of the driving circuit 222 and is configured to write data signals into the storage circuit 227 under the control of the scan signal.
  • the storage circuit 227 is electrically connected to the control terminal of the driving circuit 222 and the first voltage terminal VDD, and is configured to store data signals.
  • the threshold compensation circuit 228 is electrically connected to the control terminal and the second terminal of the driving circuit 222 and is configured to perform threshold compensation on the driving circuit 222 .
  • the reset circuit 229 is electrically connected to the control terminal of the driving circuit 222 and the first electrode of the organic light emitting element 220, and is configured to reset the control terminal of the driving circuit 222 and the first electrode of the organic light emitting element 220 under the control of the reset control signal .
  • the driving circuit 222 includes a driving transistor T1
  • the control terminal of the driving circuit 222 includes the gate of the driving transistor T1
  • the first end of the driving circuit 222 includes a first pole of the driving transistor T1
  • the second end of the driving circuit 222 includes a second pole of the driving transistor T1.
  • the data writing circuit 226 includes a data writing transistor T2
  • the storage circuit 227 includes a capacitor Cst
  • the threshold compensation circuit 228 includes a threshold compensation transistor T3
  • the first light emission control circuit 223 includes a first
  • the light emission control transistor T4 the second light emission control circuit 224 includes a second light emission control transistor T5
  • the reset circuit 229 includes a first reset transistor T6 and a second reset transistor T7
  • the reset control signal may include a first sub-reset control signal and a second sub-reset control signal. Reset control signal.
  • the first pole of the data writing transistor T2 is electrically connected to the first pole of the driving transistor T1, and the second pole of the data writing transistor T2 is configured to be electrically connected to the data line Vd
  • the gate of the data writing transistor T2 is configured to be electrically connected to the scanning signal line Ga1 to receive the scanning signal; the first pole of the capacitor Cst is electrically connected to the first power supply terminal VDD, and the second pole of the capacitor Cst is electrically connected to the first power supply terminal VDD.
  • the gate of the driving transistor T1 is electrically connected; the first pole of the threshold compensation transistor T3 is electrically connected to the second pole of the driving transistor T1, the second pole of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the threshold compensation transistor T3
  • the gate of the first reset transistor T6 is configured to be electrically connected to the scanning signal line Ga2 to receive the compensation control signal; the first pole of the first reset transistor T6 is configured to be electrically connected to the reset power supply terminal Vinit1 to receive the first reset signal, and the first reset transistor T6
  • the second pole of the drive transistor T1 is electrically connected to the gate of the first reset transistor T6, and the gate of the first reset transistor T6 is configured to be electrically connected to the reset control signal line Rst1 to receive the first sub-reset control signal; the first sub-reset control signal of the second reset transistor T7
  • the electrode is configured to be electrically connected to the reset power supply terminal Vinit2 to receive the second reset signal, the second electrode of the second reset transistor T7 is
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal.
  • the first power supply terminal VDD is a voltage source to output a constant first voltage, and the first voltage is a positive voltage; and the second power supply terminal VSS can be a voltage source to output a constant second voltage, The second voltage is a negative voltage or the like.
  • the second power supply terminal VSS may be grounded.
  • the scanning signal and the compensation control signal can be the same, that is, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 can be electrically connected to the same signal line, for example, scanning
  • the signal line Ga1 is used to receive the same signal (for example, a scanning signal).
  • the display substrate 1000 may not be provided with the scanning signal line Ga2 to reduce the number of signal lines.
  • the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may also be electrically connected to different signal lines, that is, the gate of the data writing transistor T2 is electrically connected to the scanning signal line Ga1, and the gate of the threshold compensation transistor T3 is electrically connected to the scanning signal line Ga1.
  • the gate of T3 is electrically connected to the scanning signal line Ga2, and the signals transmitted by the scanning signal line Ga1 and the scanning signal line Ga2 are the same.
  • the scanning signal and the compensation control signal may also be different, so that the gate of the data writing transistor T2 and the threshold compensation transistor T3 can be controlled separately, increasing the flexibility of controlling the pixel circuit.
  • the first light emission control signal and the second light emission control signal may be the same, that is, the gate of the first light emission control transistor T4 may be electrically connected to the gate of the second light emission control transistor T5.
  • the display substrate 1000 may not be provided with the light emission control signal line EM2 to reduce the number of signal lines.
  • the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 may also be electrically connected to different signal lines, that is, the gate of the first light emission control transistor T4 is electrically connected to The light emission control signal line EM1 and the gate of the second light emission control transistor T5 are electrically connected to the light emission control signal line EM2, and the light emission control signal line EM1 and the light emission control signal line EM2 transmit the same signal.
  • first light emission control transistor T4 and the second light emission control transistor T5 are transistors of different types, for example, the first light emission control transistor T4 is a P-type transistor, and the second light emission control transistor T5 is an N-type transistor.
  • the first light emission control signal and the second light emission control signal may also be different, which is not limited in this embodiment of the present application.
  • the first sub-reset control signal and the second sub-reset control signal may be the same, that is, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may be electrically connected to the same signal line,
  • the reset control signal line Rst1 receives the same signal (eg, the first sub-reset control signal).
  • the display substrate 1000 may not be provided with the reset control signal line Rst2 to reduce the number of signal lines.
  • the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may also be electrically connected to different signal lines, that is, the gate of the first reset transistor T6 is electrically connected to the reset control signal line Rst1, and the gate of the second reset transistor T7 is electrically connected to the reset control signal line Rst1.
  • the gate of the second reset transistor T7 is electrically connected to the reset control signal line Rst2, and the signals transmitted by the reset control signal line Rst1 and the reset control signal line Rst2 are the same.
  • the first sub-reset control signal and the second sub-reset control signal may also be different.
  • the first sub-reset control signal is different from the second sub-reset control signal
  • the pulse width of the reset control signal line Rst2 is greater than the pulse width of the reset control signal line Rst1
  • the pulse width of the reset control signal line Rst2 is smaller than
  • the pulse width of the light emission control signal line EM2 is controlled when the second light emission control transistor T5 is turned off. This helps to improve the lifetime of the organic light emitting element of the sub-pixel.
  • the second sub-reset control signal may be the same as the scan signal, that is, the gate of the second reset transistor T7 may be electrically connected to the scan signal line Ga1 to receive the scan signal as the second sub-reset control signal.
  • the gate of the first reset transistor T6 and the source of the second reset transistor T7 are respectively connected to the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2, and the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit1
  • the power terminal Vinit2 can be a DC reference voltage terminal to output a constant DC reference voltage.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same, for example, the gate of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the same reset power terminal.
  • the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high-voltage terminals or low-voltage terminals, as long as they can provide the first reset signal and the second reset signal to drive the gate of the transistor T1 and the light-emitting element 220. It only needs to reset the first electrode, which is not limited in the present application.
  • the specific structures of circuits such as 226, storage circuit 227, threshold compensation circuit 228, and reset circuit 229 can be set according to actual application requirements, and are not specifically limited in this embodiment of the present application.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present application take the transistors as P-type transistors (for example, P-type MOS transistors) as an example to elaborate on the technical solutions of the present application. That is to say, in the description of this application, the drive transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T6 Transistors T7 and the like can all be P-type transistors.
  • the transistors in the embodiments of the present application are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) to realize the functions of one or more transistors in the embodiments of the present application according to actual needs. .
  • the transistors used in the embodiments of the present application may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polysilicon thin film transistors, etc. .
  • the source and drain of the transistor can be symmetrical in structure, so there can be no difference in the physical structure of the source and drain.
  • the transistors except for the gate as the control electrode, it is directly described that one of them is the first pole and the other is the second pole, so the first pole of all or part of the transistors in the embodiments of the present application
  • the first and second poles are interchangeable as desired.
  • the pixel circuit of the sub-pixel can also be a structure including other numbers of transistors, such as 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure, which is not limited in this embodiment of the present application.
  • FIGS. 6A-11 are schematic diagrams of layers of a pixel circuit provided by an embodiment of the present application. The following describes the positional relationship of each circuit in the pixel circuit on the backplane with reference to Figs.
  • the positions of the transistors in the pixel circuit of the second color sub-pixel 120 and the third color sub-pixel 130 are roughly the same as the positions of the transistors in the first color sub-pixel.
  • the pixel circuit 221 of the sub-pixel 110 of the first color includes the drive transistor T1 shown in FIG. T5, the first reset transistor T6, the second reset transistor T7 and the capacitor Cst.
  • 6A-11 also shows the scanning signal line Ga1, the reset control signal line Rst1, the reset power signal line Init1, the light emission control signal line EM1, the data line Vd, and the power signal line of the pixel circuit 121 electrically connected to each color sub-pixel. (including the first power signal line VDD1 , the second power signal line VDD3 and the third power signal line VDD2 of the first power terminal VDD) and the shielding line 344 .
  • the first power signal line VDD1 and the second power signal line VDD3 are electrically connected to each other, and the first power signal line VDD1 and the third power signal line VDD2 are electrically connected to each other.
  • the second power supply line VDD3 includes a first sub-power supply line VDD31 extending along the first direction Y and a second sub-power supply line VDD32 extending along the second direction X.
  • the second sub-power line VDD32 intersects.
  • the scanning signal line Ga1 is configured to provide a scanning signal for the pixel group; the reset control signal line Rst1 is configured to provide a reset control signal for the pixel group; the reset power signal line Init1 is configured to provide a reset power signal for the pixel group; the light emission control signal line EM1 is configured to provide light emitting control signals for the pixel groups; the data line Vd is configured to provide light emitting data signals for the pixel groups; the first power signal line VDD1, the second power signal line VDD3 and the third power signal line VDD2 are configured as The pixel group provides the power signal.
  • FIG. 6A shows the active semiconductor layer 310 of the pixel circuit in the display substrate.
  • the active semiconductor layer 310 can be formed by patterning a semiconductor material.
  • the active semiconductor layer 310 can be used to make the above-mentioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6 and second reset transistor T7 channel.
  • the active semiconductor layer 310 includes the channel and the source-drain region of each transistor of each sub-pixel (that is, the source region s and the drain region d shown in the second color sub-pixel), and each transistor in the same pixel circuit The channel and the source and drain regions are integrally arranged.
  • the active semiconductor layer 310 shown in FIG. 6A includes a channel 301 of a subpixel of a first color, a channel 302 of a subpixel of a second color, and a channel 303 of a subpixel of a third color.
  • the active semiconductor layer may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region therein may be conductiveized by doping or the like to realize electrical connection of various structures. That is to say, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed by p-silicon, and each transistor in the same pixel circuit includes a source-drain region (that is, a source region s and a drain region d) and a channel , the channels of different transistors are separated by source and drain regions.
  • the active semiconductor layers in the pixel circuits of sub-pixels of different colors arranged along the first direction are not connected and are disconnected from each other.
  • the active semiconductor layers in the pixel circuits of the sub-pixels of the same color arranged along the second direction may be integrally arranged, or may be disconnected from each other.
  • the active semiconductor layer 310 can be made of amorphous silicon, polysilicon, oxide semiconductor materials and the like. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the gate metal layer of the pixel circuit may include a first conductive layer and a second conductive layer.
  • a gate insulating layer 103 (as shown in FIG. 12 and FIG. 13 ) is formed on the above-mentioned active semiconductor layer 310 for protecting the above-mentioned active semiconductor layer 310 , and the active semiconductor layer 310 is located on the base substrate 100 .
  • FIG. 7 shows the first conductive layer 320 included in the display substrate, and the first conductive layer 320 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 310 .
  • the first conductive layer 320 may include the second plate CC2 of the capacitor Cst, the scanning signal line Ga1, the reset control signal line Rst1, the light emission control signal line EM1, the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first Gates of the light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7.
  • the scanning signal line Ga1 includes a scanning signal line body portion Ga11 and a protruding portion P protruding from one side of the scanning signal line body portion Ga11 .
  • the gate of the data writing transistor T2 can be the overlapping part of the scanning signal line Ga1 and the active semiconductor layer 310;
  • the first part where the active semiconductor layer 310 overlaps, the gate of the second light emission control transistor T5 can be the second part where the light emission control signal line EM1 overlaps the active semiconductor layer 310;
  • the gate of the first reset transistor T6 is the reset control
  • the first part where the signal line Rst1 overlaps with the active semiconductor layer 310, the gate of the second reset transistor T7 is the second part where the reset control signal line Rst1 overlaps with the active semiconductor layer 310;
  • the threshold compensation transistor T3 can be a double-gate structure
  • the first gate of the threshold compensation transistor T3 can be the overlapping part of the scanning signal line Ga1 and the active semiconductor layer 310, and the second gate of the threshold compensation transistor T3 can be the protruding part of the scanning signal line Ga1 P overlaps the active semiconductor layer 310 .
  • the gate of the driving transistor T1 can be the overlapping part of the scanning
  • each dotted rectangular box in FIG. 6A shows each portion where the first conductive layer 320 overlaps with the active semiconductor layer 310 .
  • the scanning signal line Ga1 , the reset control signal line Rst1 and the emission control signal line EM1 are arranged along the second direction X.
  • the scan signal line Ga1 is located between the reset control signal line Rst1 and the light emission control signal line EM1 .
  • the extension of the signal line along the first direction means that the entire row of signal lines extends along the first direction, and the area of the part of the signal line extending in the first direction is much larger than the area of the part extending in the second direction; Extending in the second direction means that the entire row of signal lines extends along the second direction, and the area of the portion of the signal line extending in the second direction is much larger than the area of the portion extending in the first direction.
  • the second plate CC2 of the capacitor Cst (ie, the gate of the driving transistor T1 ) is located between the scanning signal line Ga1 and the light emission control signal line EM1 .
  • the protrusion P of the scanning signal line Ga1 is located on the side of the scanning signal line Ga1 away from the emission control signal line EM1 .
  • the gate of the data write transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6, and the gate of the second reset transistor T7 are all Located on the first side of the gate of the driving transistor T1, the gates of the first light emitting control transistor T4 and the second light emitting control transistor T5 are both located on the second side of the gate of the driving transistor T1.
  • the first side and the second side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel are opposite to each other in the second direction X of the gate of the driving transistor T1. opposite sides.
  • the first side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel may be the upper side of the gate of the driving transistor T1, and the first color sub-pixel
  • the second side of the gate of the driving transistor T1 of the pixel circuit of the pixel may be the lower side of the gate of the driving transistor T1.
  • the lower side for example, the side of the display substrate for binding the driving chip is the lower side of the display substrate, and the lower side of the gate of the driving transistor T1 is the side closer to the driving chip of the gate of the driving transistor T1 .
  • the upper side is the side opposite to the lower side, for example, the side of the gate of the driving transistor T1 that is farther away from the driving chip.
  • the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located at the gate of the driving transistor T1.
  • the first gate of the threshold compensation transistor T3, the gate of the second light emission control transistor T5 and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1.
  • the third side and the fourth side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel are opposite to each other in the first direction Y of the gate of the driving transistor T1. opposite sides.
  • opposite sides for example, as shown in FIG.
  • the third side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel may be the left side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel
  • the fourth side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel may be the right side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel.
  • the left side and the right side for example, in the same pixel circuit, the data line is on the left side of the first power signal line VDD1, and the first power signal line VDD1 is on the right side of the data line.
  • a first insulating layer 104 (as shown in FIG. 12 and FIG. 13 ) is formed on the above-mentioned first conductive layer 320 to protect the above-mentioned first conductive layer 320 .
  • FIG. 8 shows the second conductive layer 330 of the pixel circuit.
  • the second conductive layer 330 includes the first plate CC1 of the capacitor Cst, the reset power signal line Init1 , the third power signal line VDD2 and the light shielding portion S.
  • the third power signal line VDD2 is integrally formed with the first plate CC1 of the capacitor Cst.
  • the first plate CC1 of the capacitor Cst and the second plate CC2 of the capacitor Cst at least partially overlap to form the capacitor Cst.
  • FIG. 9 shows the source-drain metal layer 340 of the pixel circuit.
  • the source-drain metal layer 340 includes a data line Vd, a first power signal line VDD1 and a shielding line 344 .
  • the data line Vd, the first power signal line VDD1 and the shielding line 344 all extend along the second direction X.
  • the source-drain metal layer 340 further includes a connection structure 341 , a connection portion 342 and a first sub-electrode connection structure 343 of the electrode connection structure.
  • One end of the connection structure 341 is connected to the gate of the driving transistor T1, and the other end of the connection structure 341 is connected to the source and drain regions of the threshold compensation transistor T3.
  • FIG. 9 also shows exemplary positions of a plurality of via holes, through which the source-drain metal layer 340 is connected to a plurality of film layers located between the source-drain metal layer 340 and the substrate.
  • the source-drain metal layer 340 is connected to the active semiconductor layer 310 shown in FIG.
  • the via 386 , the via 385 , the via 331 and the via 332 are connected to the second conductive layer 330 shown in FIG. 8 .
  • a third insulating layer 106 and a fourth insulating layer 107 are formed on the above-mentioned source-drain metal layer 340 to protect the above-mentioned source-drain metal layer 340 .
  • the organic light emitting element of each sub-pixel can be disposed on a side of the third insulating layer and the fourth insulating layer away from the base substrate.
  • Figure 10 shows the third conductive layer 350 of the pixel circuit, the third conductive layer 350 includes the second sub-electrode connection structure 353 of the electrode connection structure and the second power supply signal distributed along the second direction X and the first direction Y crosswise line VDD3.
  • FIG. 10 also shows exemplary locations of a plurality of via holes 351 and via holes 354 , through which the third conductive layer 350 is connected to the source-drain metal layer 340 .
  • FIG. 11A is a schematic diagram of the stacking positional relationship of the above-mentioned active semiconductor layer 310 , the first conductive layer 320 , the second conductive layer 330 , the source-drain metal layer 340 and the third conductive layer 350 .
  • the data line Vd communicates with the data writing in the active semiconductor layer 310 through at least one via hole (for example, the via hole 381) in the gate insulating layer, the first insulating layer, and the second insulating layer.
  • the source regions of transistor T2 are connected.
  • the first power signal line VDD1 is connected to the corresponding first light emission control transistor T4 in the active semiconductor layer 310 through at least one via hole (for example, the via hole 382) in the gate insulating layer, the first insulating layer, and the second insulating layer.
  • the source region is connected.
  • connection structure 341 is connected to the corresponding hole in the active semiconductor layer 310 through at least one via hole (for example, via hole 384) in the gate insulating layer, the first insulating layer, and the second insulating layer.
  • the drain region of the threshold compensation transistor T3 is connected, and the other end of the connection structure 341 is connected to the driving transistor T1 in the first conductive layer 320 through at least one via hole (for example, the via hole 385) in the first insulating layer and the second insulating layer.
  • the gate that is, the second plate CC2 of the capacitor Cst) is connected.
  • One end of the connecting part 342 is connected to the reset power signal line Init1 through a via hole (for example, via hole 386) in the second insulating layer, and the other end of the connecting part 342 is connected through the gate insulating layer, the first insulating layer and the second insulating layer.
  • At least one via in the layer (for example, the via 387 ) is connected to the drain region of the second reset transistor T7 in the active semiconductor layer 310 .
  • the first sub-electrode connection structure 343 is connected to the second light emission control transistor T5 in the active semiconductor layer 310 through at least one via hole (for example, the via hole 352) in the gate insulating layer, the first insulating layer, and the second insulating layer. connected to the drain region.
  • the source region and the drain region of the transistors used in the embodiments of the present disclosure may be structurally the same, so there may be no structural difference between the source region and the drain region. Therefore, as required The two are interchangeable.
  • the first power signal line VDD1 connects with at least one via hole (for example, via hole 3832) in the second insulating layer between the second conductive layer 330 and the source-drain metal layer 340.
  • the first plate CC1 of the capacitor Cst in the second conductive layer 330 is connected.
  • the shielding line 344 extends along the second direction X, and its orthographic projection on the substrate is located between the orthographic projection of the driving transistor on the substrate and the orthographic projection of the data line on the substrate. between orthographic projections.
  • the shielding line in the pixel circuit of the sub-pixel of the first color can reduce the influence of the signal transmitted on the data line in the pixel circuit of the sub-pixel of the second color on the performance of the threshold compensation transistor T3 of the sub-pixel of the first color, Furthermore, the influence of the coupling between the gate of the driving transistor of the sub-pixel of the first color and the data line of the sub-pixel of the second color is reduced, and the problem of crosstalk is weakened.
  • the shielding wire 344 is connected to the reset power signal line Init1 through at least one via hole (such as the via hole 332) in the second insulating layer.
  • the shielding wire In addition to making the shielding wire have a fixed potential, it also makes the The voltage of the initialization signal transmitted on the reset power signal line is more stable, which is more conducive to the working performance of the pixel driving circuit.
  • the shielding line 344 is electrically connected to the reset power signal line so that the shielding line has a fixed potential.
  • the shielding line 344 can be respectively electrically connected to two reset power signal lines Init1 extending along the Y direction, and the two reset power signal lines Init1 are respectively located on both sides of the shielding line 344 along the X direction.
  • the two reset power signal lines correspond to the nth row of pixel circuits and the n+1th row of pixel circuits respectively.
  • the shielding line 344 in the same column can be a whole shielding line, and the whole shielding line includes a plurality of sub-parts located between two adjacent reset power signal lines, and each sub-part is respectively located in each row of the column. within the pixel circuit area.
  • the shielding line 344 can also be coupled to the first power signal line, so that the shielding line 344 has the same fixed potential as the power signal transmitted by the first power signal line .
  • the orthographic projection of the shielding line 344 on the substrate is located between the orthographic projection of the threshold compensation transistor T3 on the substrate and the orthographic projection of the data line Vd on the substrate, so that the shielding line 344 can reduce the The influence of the signal transmission on the line on the performance of the threshold compensation transistor T3, thereby reducing the influence of the coupling between the gate of the drive transistor and the data signal line Vd(n+1), solving the problem of vertical crosstalk, making the display When the substrate is used for display, better display effect can be obtained.
  • the orthographic projection of the shielding line 344 on the base substrate may be located between the orthographic projection of the connection structure 341 on the base substrate and the orthographic projection of the data line on the base substrate; the orthographic projection of the shielding line 344 on the base substrate The projection is located between the orthographic projection of the driving transistor T1 on the base substrate and the orthographic projection of the data line on the base substrate.
  • the above setting method can well reduce the first crosstalk generated between the data line and the threshold compensation transistor, and the second crosstalk generated between the data line and the connection structure, thereby reducing the noise caused by the above first crosstalk and the second crosstalk. Indirect crosstalk to drive transistors. In addition, the above arrangement also reduces the direct crosstalk between the data line and the driving transistor, thereby better ensuring the working performance of the display substrate.
  • the shielding line 344 is not limited to the above arrangement, and the shielding line 344 can also be coupled only to the reset power signal line corresponding to the nth row of pixel circuits, or only to the reset power signal line corresponding to the n+1th row of pixel circuits coupling.
  • the extension length of the shielding wire 344 in the second direction X can also be set according to actual needs.
  • the pixel circuit of each color sub-pixel further includes a light-shielding part S, and the light-shielding part S and the shielding line 344 are arranged in different layers, and the orthographic projection of the light-shielding part S on the base substrate and the orthographic projection of the shielding line 344 on the base substrate There are overlaps.
  • the shielding line 344 is connected to the light-shielding portion S in the second conductive layer 330 through the via hole 331 in the second insulating layer, so that the light-shielding portion S has a fixed potential, thereby better reducing the threshold compensation transistor T3 and other conductive elements in its vicinity.
  • the coupling effect between graphics makes the working performance of the display substrate more stable.
  • the light-shielding part S overlaps the active semiconductor layer 310 between the two gates of the threshold compensation transistor T3 to prevent the active semiconductor layer 310 between the two gates from being illuminated and changing its characteristics, for example, preventing this part
  • the voltage of the active semiconductor layer is changed to prevent crosstalk.
  • This example schematically shows that the light shielding part is connected to the shielding wire, but it is not limited thereto, and the two may not be connected.
  • the second power signal line VDD3 is connected to the first power signal line VDD1 through at least one via 351 in the third insulation layer and the fourth insulation layer, and the second sub-electrode connection structure 353 is connected to the first power signal line VDD1 through The via holes 354 in the third insulating layer and the fourth insulating layer are connected to the first sub-electrode connection structure 343 .
  • the third insulating layer may be a passivation layer
  • the fourth insulating layer may be a planarization layer
  • the third insulating layer is located between the fourth insulating layer and the base substrate.
  • the fourth insulating layer may be an organic layer, and the organic layer is thicker than the passivation layer and other inorganic layers.
  • both the via hole 351 and the via hole 354 are nested via holes, that is, the via hole 351 includes a first via hole in the third insulating layer and a second via hole in the fourth insulating layer, and the second via hole in the third insulating layer A via hole is opposite to the position of the second via hole in the fourth insulating layer, and the orthographic projection of the second via hole in the fourth insulating layer on the base substrate is located on the substrate of the first via hole in the third insulating layer. Inside the orthographic projection on the base substrate.
  • the second power signal line VDD3 is distributed in a grid shape, and the orthographic projection of the second sub-power line VDD32 extending along the X direction on the substrate is the same as that of the first power signal line VDD1 on the substrate.
  • the orthographic projections on the substrate roughly overlap or the orthographic projection of the first power signal line VDD1 on the base substrate is located within the orthographic projection of the second sub-power supply line VDD32 on the base substrate, and the second power signal line VDD3 and the first power supply signal line VDD3
  • the electrical connection of the signal line VDD1 can reduce the voltage drop of the first power signal line VDD1, thereby improving the uniformity of the display device.
  • the second power signal line VDD3 can be made of the same material as the source-drain metal layer.
  • the first sub-electrode connection structures 343 of the sub-pixels of the first color, the sub-pixels of the second color and the sub-pixels of the third color are all block structures.
  • the first electrode of each color sub-pixel formed subsequently will be connected to the corresponding second sub-electrode connection structure 353 through a via hole so as to be connected to the drain region of the second light emission control transistor T5.
  • This embodiment includes but is not limited thereto.
  • the position of the second sub-electrode connection structure in each color sub-pixel is determined according to the arrangement rule of the organic light-emitting elements and the position of the light-emitting region.
  • FIG. 12 is a schematic diagram of a partial cross-sectional structure of the display substrate shown in FIG. 11A , and FIG. 11A only shows part of the film layers in FIG. 12 .
  • the second pole for example, the drain T5d
  • the second light emission control transistor T5 in the active semiconductor layer is set away from the side of the base substrate 100
  • There is a gate insulating layer 103 and the side of the gate insulating layer 103 away from the base substrate 100 is provided with a light emission control signal line EM1, and the side of the light emission control signal line EM1 far away from the base substrate 100 is provided with a first insulating layer 104, the second The side of an insulating layer 104 away from the base substrate 100 is provided with a third power signal line VDD2, and the side of the third power signal line VDD2 away from the base substrate 100 is provided with a second insulating layer 105, and the
  • One side of the base substrate 100 is provided with a first sub-electrode connection structure 343 .
  • the first sub-electrode connection structure 343 of the second-color sub-pixel 120 is connected to the second light emission control transistor T5 in the active semiconductor layer 310 through the via hole 352 of the gate insulating layer 103, the first insulating layer 104, and the second insulating layer 105.
  • the second pole T5d is connected.
  • the first sub-electrode connection structure 343 overlaps both the third power signal line VDD2 and the light emission control signal line EM1 .
  • the side of the first sub-electrode connection structure 343 away from the base substrate 100 is provided with the third insulating layer 106 and the fourth insulating layer 107 in sequence, and the side of the fourth insulating layer 107 away from the base substrate 100 is provided with the second sub-electrode connection. structure 353 and the second power signal line VDD3.
  • the second power signal line VDD3 overlaps with the third power signal line VDD2 .
  • the second sub-electrode connection structure 353 is connected to the first sub-electrode connection structure 343 through the nested via hole 354 located in the third insulating layer 106 and the fourth insulating layer 107 , thereby realizing connection with the second light emission control transistor.
  • the data line Vd is connected to the source electrode T2s of the data writing transistor T2 through the via hole 381 in the gate insulating layer 103, the first insulating layer 104 and the second insulating layer 105;
  • One end is connected to the drain T3d of the threshold compensation transistor T3 through the via hole 384 in the gate insulating layer 103, the first insulating layer 104 and the second insulating layer 105, and the other end of the connection structure 341 is connected through the first insulating layer 104 and the second insulating layer 105.
  • the via hole 385 in the insulating layer 105 is connected to the gate of the driving transistor T1 (that is, the second plate CC2 of the capacitor Cst); the channel T1c of the driving transistor T1 is located on the side of the gate facing the substrate 100, and is connected to The via hole 385 does not overlap, and the source T1d of the driving transistor T1 overlaps with its gate and the first plate CC1 of the capacitor Cst.
  • FIG. 13 is a schematic diagram of a partial cross-sectional structure of the display substrate shown in FIG. 11A , and FIG. 11A only shows part of the film layers in FIG. 13 .
  • the difference between the first-color sub-pixel 110 and the second-color sub-pixel 120 is that the orthographic projection of the second sub-electrode connection structure 353 in the second-color sub-pixel 120 on the base substrate 100 is different from that of the second color sub-pixel 120.
  • the orthographic projection of the second pole T5d of the second light emission control transistor T5 on the base substrate 100 does not overlap, while the orthographic projection of the second sub-electrode connection structure 353 in the first color sub-pixel 130 on the base substrate 100 does not overlap with The orthographic projections of the second pole T5d of the second light emission control transistor T5 on the base substrate 100 overlap.
  • the first sub-electrode connection structure 343 does not overlap with the third power signal line VDD2 and the light emission control signal line EM1 .
  • the channel T1c of the driving transistor T1 is located on the side of the gate facing the base substrate 100 , and overlaps with the via hole 385 . It can be seen from this that the channel width of the driving transistor of the first color sub-pixel is greater than the channel width of the second color sub-pixel.
  • the scanning signal line Ga1 the reset control signal line Rst1 and the reset power signal line Init1 are all located at the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel.
  • the light emitting control signal line EM1 is located at the second side of the driving transistor T1 of the pixel circuit of the first color sub-pixel.
  • the scanning signal line Ga1 , the reset control signal line Rst1 , the emission control signal line EM1 , and the reset power signal line Init1 all extend along the first direction Y, and the data line Vd extends along the second direction X.
  • the arrangement relationship of the drive circuit, the first light emission control circuit, the second light emission control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit and the reset circuit in each pixel circuit is not limited to that shown in Fig. 6A In the example shown in -11, according to actual application requirements, the positions of the drive circuit, the first light emission control circuit, the second light emission control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit and the reset circuit can be specifically set.
  • the first electrode 11 of the first color sub-pixel is connected to the second sub-electrode connection structure 353 through a via hole (not shown) in the fifth insulating layer, so as to realize the connection with the second light emission control.
  • the drain regions of transistor T5 are connected.
  • the first electrode 13 of the organic light-emitting element of the third color sub-pixel is connected to the second sub-electrode connection structure 353 through the via hole (not shown) in the fifth insulating layer, so as to realize the connection with the second light emission control transistor T5. connected to the drain region.
  • the first electrode 12 of the second color sub-pixel is connected to the second sub-electrode connection structure 353 through the via hole in the fifth insulating layer, and then connected to the second sub-electrode connection structure 343, so as to realize the connection with the drain of the second light emission control transistor T5.
  • the polar regions are connected.
  • FIGS. 14A-14E are partial schematic views of various layers of a display substrate in another display panel provided by an embodiment of the present disclosure.
  • the display substrate is stacked with the light control panel shown in FIGS. 8A-8I to form the display shown in FIG. 1C.
  • the pixel circuit of the display substrate is the same as that shown in FIG. 5 , and the sub-pixel structure of the display substrate is mainly different from the embodiment shown in FIGS. 6A-13 in the following points. 14A-14D only show a few sub-pixels located in the same pixel row as an example.
  • FIG. 14A shows a superimposed schematic diagram of the active semiconductor layer 310 and the first conductive layer 320 of the pixel circuit in the display substrate.
  • the active semiconductor layer 310 can be used to make the above-mentioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6 and second reset transistor T7 channel.
  • the first conductive layer 320 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 310 .
  • the first conductive layer 320 may include the second plate CC2 of the capacitor Cst, the scanning signal line Ga1, the reset control signal line Rst1, and the light emission control signal line EM1/EM2 (for example, for the first light emission control transistor T4, the second light emission control transistor T4, and the second light emission control transistor T4).
  • the light emission control signal line that the transistor T5 provides the light emission control signal is shared as the same signal line), the drive transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first light emission control transistor T5, and the first light emission control transistor T5.
  • Figure 14B shows the second conductive layer 330 of the pixel circuit
  • the second conductive layer 330 includes the first plate CC1 of the storage capacitor, the first reset power signal line Init1, the second reset power signal line Init2, the third power signal line VDD2 and light-shielding part S2.
  • the third power signal line VDD2 is integrally formed with the first plate CC1 of the capacitor C.
  • the first plate CC1 of the capacitor Cst and the second plate CC2 of the capacitor C at least partially overlap to form the capacitor Cst.
  • FIG. 14C shows the source-drain metal layer 340 of the pixel circuit.
  • the source-drain metal layer 340 includes the data line Vd, the first power signal line VDD1 and so on.
  • FIG. 14D shows a schematic diagram of the stacking of the active semiconductor layer 310 , the second conductive layer 330 and the source-drain metal layer 340 .
  • the second reset power signal line Init2 is electrically connected to the connection structure CP1 through the via hole V2
  • the connection structure CP1 is electrically connected to the source (or drain) of the second reset transistor T7 through the via hole V3 .
  • the connection between the first reset power signal line Init1 and the first reset transistor T6 is similar to that in the previous embodiments, and other similar or identical structures will not be repeated here.
  • FIG. 14E shows a schematic diagram including the first electrode E1 of the first sub-pixel PU1 , the first electrode E2 of the second sub-pixel PU2 and the first electrode E3 of the third sub-pixel PU3 .
  • the arrangement of the first electrode E1, the first electrode E2 and the first electrode E3 shown in FIG. 14E is the same as the arrangement of the first electrodes of the three sub-pixels of the display panel shown in FIG. Among them, the orthographic projections of the first electrode E1, the first electrode E2 and the first electrode E3 on the main surface of the first substrate are respectively the same as the first pixel electrode CE1 and the second pixel electrode CE1 of the light control panel 02 shown in FIG. 8H
  • the orthographic projections of the electrode CE2 and the third pixel electrode CE3 on the main surface of the first substrate are correspondingly overlapped, and for the specific arrangement, please refer to the previous description.
  • the above-mentioned sub-pixel structures of the display substrate 01 are exemplary, and are not limited to the cases of the above-mentioned embodiments, and may also be other types of sub-pixel structures, as long as the requirements for matching with the light control panel 02 in the embodiments of the present application are met.
  • Those skilled in the art can design according to specific requirements.
  • FIG. 15A is a partial plan view of a display substrate in another display panel provided by an embodiment of the present disclosure
  • FIG. 15B is a stacked display substrate shown in FIG. 15A in another display panel provided by an embodiment of the present disclosure. Partial plan view of the light control panel.
  • the embodiment shown in Figures 15A-15B differs from Figures 1A-1C in the following ways.
  • the first pixel electrode CE1 and the second pixel electrode CE2 are arranged at intervals in the row direction X, and the size of the second pixel electrode CE2 in the row direction X is larger than that of the first pixel electrode.
  • the second pixel electrode CE2 covers at least part of the space between the phototransistor Tc of the second sub-light control unit CU2 and the phototransistor Tc of the third sub-light control unit CU3 in the row direction X.
  • the whole composed of the first pixel electrode CE1 and the second pixel electrode CE2 is arranged in the column direction Y with the third pixel electrode CE3, and the third pixel electrode CE3 is located in the column direction Y of the first pixel electrode.
  • the side of the whole composed of CE1 and the second pixel electrode CE2 is away from the gate line that provides the light control gate signal to the light control unit; the second plate C23 of the light control storage capacitor C of the third sub light control unit CU3 is in the column
  • the length in the direction Y is greater than the length of the second plate C21 of the light-controlled storage capacitor C of the first sub-light control unit CU1 in the column direction Y, and is greater than the length of the second plate C21 of the light-controlled storage capacitor C of the second sub-light control unit CU2.
  • the length of the dipole plate C22 in the column direction Y is adapted to the arrangement of the whole formed by the first pixel electrode CE1 and the second pixel electrode CE2 and the third pixel electrode CE3 .
  • the length of the second plate C22 of the light-controlled storage capacitor C of the second sub-light control unit CU2 in the column direction Y is in the same column as the second plate C21 of the light-controlled storage capacitor C of the first sub-light control unit CU1
  • the lengths in the direction Y are substantially equal.
  • the end portion CT of the second plate C23 of the light-controlled storage capacitor C of the third sub-light control unit CU3 in the column direction Y overlaps with the third pixel electrode CE3, and the connecting portion CEP (the part indicated by the smaller white elliptical dotted line frame) connecting the end portion CT and the photogate line CGL extends in the column direction Y, and the connecting portion CEP is at the Orthographic projection on the main surface 11 of a substrate 1a with the second opening COP1 of the first sub-light control unit CU1, the second opening COP2 of the second sub-light control unit CU2 and the second opening of the third sub-light control unit CU3
  • the orthographic projections of COP3 on the main surface 11 of the first substrate 1a do not overlap, so as to rationally use the non-display area in a limited space to set a longer connection part CEP, and avoid the connection part CEP from blocking each second opening,
  • the size of the third pixel electrode CE3 in the row direction X is larger than the size of the second pixel electrode CE2 in the row direction X, and the orthographic projection of the third pixel electrode CE3 in the row direction X is the same as that of the second pixel electrode CE3 in the row direction X.
  • the orthographic projection of a pixel electrode CE1 in the row direction X at least partially overlaps with the orthographic projection of the second pixel electrode CE2 in the row direction X at least partially.
  • the orthographic projection of the first part of the light control data line CDL2 that provides the light control data signal to the second sub light control unit CU2 on the main surface 11 of the first substrate 1a is located on the first pixel electrode CE1
  • the orthographic projections of the pixel electrodes CE3 on the main surface 11 of the first substrate 1a overlap;
  • the orthographic projections on the main surface 11 of the first substrate 1a are overlapped, so as to avoid the signal line from blocking the second
  • the phototransistor Tc of the first photocontrol unit CU1, the phototransistor Tc of the second photocontrol unit CU2, and the phototransistor Tc of the third photocontrol unit CU3 are basically arranged in a row extending along the row direction X.
  • the size of the second pole D3 of the phototransistor Tc of the third sub-photocontrol unit CU3 in the column direction Y is larger than that of the second pole D1 of the phototransistor Tc of the first sub-photocontrol unit CU1 in the column direction Y and the size of the second pole D2 of the phototransistor Tc of the second photocontrol unit CU2 in the column direction Y; the second pole D3 of the phototransistor Tc of the third photocontrol unit CU3 is close to the third pixel
  • the orthographic projection of the end of the electrode CE3 on the main surface 11 of the first substrate 1a overlaps with the orthographic projection of the third pixel electrode CE3 on the main surface 11 of the first substrate 1a, and the light of the third sub-light control unit CU3
  • the part extending along the column direction Y of the orthographic projection of the second pole D3 of the control transistor Tc on the main surface 11 of the first substrate 1a is also the same as the orthographic projection of the second pixel electrode CE2
  • the part extending along the column direction Y of the orthographic projection of the second electrode of the phototransistor of the third sub-photocontrol unit on the main surface of the first substrate is connected with the first pixel electrode, the second The orthographic projections of the pixel electrode and the third pixel electrode on the main surface 11 of the first substrate do not overlap, so as to obtain a display panel with a larger aperture ratio.
  • the area of the orthographic projection of the first pixel electrode CE1 on the main surface 11 of the first substrate 1a is smaller than that of the second pixel electrode CE2 on the main surface of the first substrate 1a.
  • the area of the orthographic projection of the second pixel electrode CE2 on the main surface 11 of the first substrate 1a is smaller than the orthographic projection of the third pixel electrode CE3 on the main surface 11 of the first substrate 1a area.
  • the sub-pixel corresponding to the first sub-light control unit CU1 emits red light
  • the sub-pixel corresponding to the second sub-light control unit CU2 emits green light
  • the sub-pixel corresponding to the third sub-light control unit CU3 emits blue light to balance different colors.
  • the luminous intensity and lifetime of the luminescent material are organic light-emitting diode devices, and may also be other types of electroluminescent devices.
  • At least one embodiment of the present disclosure further provides a display device, which includes any display panel 10 provided by the embodiments of the present disclosure.
  • the display device has the technical effects of the display panel 10, which will not be repeated here.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a vehicle display device such as a navigator, and the embodiments of the present disclosure are not limited thereto.
  • At least one embodiment of the present disclosure further provides a method for controlling any display panel 10 provided by the embodiments of the present disclosure, including: using at least some of the sub-lights in the plurality of sub-light control units CU1/CU2/CU3 of the light control panel 02
  • the control unit modulates the light emitted from the first opening, so that the light emitted from the first opening passes through the second openings of at least some of the sub-light control units CU1/CU2/CU3 and passes through the second openings of at least some of the sub-light control units CU1/CU2/CU3 from the display panel 10. shoot.
  • FIG. 16 is an application schematic diagram of a display device provided by an embodiment of the present disclosure.
  • the display panel 10 includes a first edge display area A1 near the first edge of the display panel 10, a second edge display area A2 near the second edge of the display panel 10, and a first edge display area A1 and a first edge display area A1.
  • the distance of the eye box AE of the second edge display area A2 is less than the distance of the eye box AE of the observer of the display panel 10;
  • the control method includes: controlling the light emitted from the first opening in the first edge display area A1 to pass through The deflection direction after modulation by the sub-light control unit is opposite to the deflection direction of the light emitted from the first opening in the second edge display area A2 after being modulated by the sub-light control unit, and is controlled to exit from the first opening in the middle display area AM The light is not deflected after being modulated by the sub-light control unit.
  • the display panel 10 is applied to a driving scene as a navigator or an entertainment display device.
  • the first edge display area A1 is farther from the ground than the second edge display area A2 and is farther away from the driver's eye box.
  • the deflection of the liquid crystal molecules in the first edge display area A1 can be controlled to prevent the light emitted from the first edge display area A1 from propagating to the windshield, and more light emitted from the first edge display area A1
  • the light propagates to the eye box, preventing the light emitted from the display panel 10 from being imaged on the windshield and disturbing the driver's driving field of view;
  • the light emitted from the second edge display area A2 propagates to the eye box, so that the driver can watch the image of the second edge display area A2 more comprehensively.
  • the display panel 10 is a curved screen, and the surface of the curved screen is a curved surface that protrudes toward the viewer.

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Abstract

显示面板、显示装置以及显示面板的控制方法，显示面板包括显示基板和光控面板；显示基板包括第一衬底和设置于第一衬底的主表面上的多个子像素，每个子像素具有第一开口，用于生成显示图像的光从第一开口出射；光控面板与显示基板在垂直于第一衬底主表面的方向上层叠设置，包括多个子光控单元，每个子光控单元具有第二开口，多个子光控单元与多个子像素一一对应，从第一开口出射的光经过多个子光控单元中的至少部分子光控单元的第二开口之后从显示面板出射，多个子光控单元配置为对从第一开口出射的光进行调制；每个子光控单元的第二开口在第一衬底的主表面上的正投影与对应的子像素的第一开口在第一衬底的主表面上的正投影基本重叠。

Description

显示面板、显示装置以及显示面板的控制方法
本申请要求于2021年7月20日递交的PCT专利申请第PCT/CN2021107421号的优先权，在此全文引用上述PCT专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一实施例涉及一种显示面板、显示装置以及显示面板的控制方法。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示产品与传统的液晶显示器(LCD)相比，具有自发光、广色域、高对比度、轻薄等优点，使其广泛应用于手机、平板电脑等领域。
发明内容
本公开至少一实施例提供一种显示面板，该显示面板包括显示基板和光控面板。显示基板包括第一衬底和设置于所述第一衬底的主表面上的多个子像素，所述多个子像素中的每个具有第一开口，用于生成显示图像的光从所述第一开口出射；光控面板与所述显示基板在垂直于所述第一衬底主表面的方向上层叠设置，包括多个子光控单元，所述多个子光控单元的每个具有第二开口，所述多个子光控单元与所述多个子像素一一对应，从所述第一开口出射的光经过所述多个子光控单元中的至少部分子光控单元的第二开口之后从所述显示面板出射，所述多个子光控单元中的至少部分子光控单元配置为对从所述第一开口出射的光进行调制；所述子光控单元中的每个的第二开口在所述第一衬底的主表面上的正投影与对应的所述子像素的第一开口在所述第一衬底的主表面上的正投影基本重叠。
例如，在本公开至少一实施例提供的显示面板中，所述子光控单元中的 每个的第二开口在所述第一衬底的主表面上的正投影包括与对应的所述子像素的第一开口在所述第一衬底的主表面上的正投影重叠的部分的面积与对应的所述子像素的第一开口在所述第一衬底的主表面上的正投影的面积的比值大于等于80％。
例如，在本公开至少一实施例提供的显示面板中，所述子光控单元中的每个的第二开口在所述第一衬底的主表面上的正投影与对应的所述子像素的第一开口在所述第一衬底的主表面上的正投影完全重合。
例如，在本公开至少一实施例提供的显示面板中，所述光控面板为液晶面板，所述多个子光控单元的每个还包括像素电极、液晶分子、公共电极和光控晶体管；所述光控面板还包括光控栅线和光控数据线。光控栅线沿所述行方向延伸，且与所述光控晶体管的栅极电连接以给所述光控晶体管提供光控栅信号；光控数据线沿所述列方向延伸，且与所述光控晶体管的第一极电连接以给所述光控晶体管提供光控数据信号；所述光控晶体管的第二极与所述像素电极电连接，所述液晶分子配置为可在所述像素电极和所述公共电极之间的电场作用下旋转，以对从所述第一开口出射的光进行调制；在每个所述子光控单元中，所述第二开口暴露至少部分所述像素电极。
例如，在本公开至少一实施例提供的显示面板中，所述多个子像素中的每个包括驱动晶体管和发光元件，所述驱动晶体管配置为控制流经所述发光元件的驱动电流的大小，所述发光元件配置为接收所述驱动电流且被所述驱动电流驱动而发光，且包括第一电极；在每个所述子像素中，所述第一开口暴露至少部分所述第一电极；所述像素电极在所述第一衬底的主表面上的正投影与对应的所述子像素的第一电极在所述第一衬底的主表面上的正投影基本重合。
例如，在本公开至少一实施例提供的显示面板中，每个所述子光控单元的光控晶体管在所述第一衬底的主表面上的正投影与所述显示基板的所述多个子像素的第一开口在所述第一衬底的主表面上的正投影均不重叠，且与所述光控面板的多个所述子光控单元的第二开口在所述第一衬底的主表面上的正投影不重叠。
例如，在本公开至少一实施例提供的显示面板中，所述光控栅线在所述 第一衬底的主表面上的正投影与所述显示基板的所述多个子像素的第一开口在所述第一衬底的主表面上的正投影均不重叠，且与所述光控面板的多个所述子光控单元的第二开口在所述第一衬底的主表面上的正投影不重叠。
例如，在本公开至少一实施例提供的显示面板中，所述多个子光控单元排列成光控阵列；所述光控阵列包括呈阵列排列的多个光控单元，一个所述光控单元包括连续排列的多个所述子光控单元；所述光控阵列包括沿行方向延伸的光控行和沿列方向延伸的光控列，所述行方向与所述列方向相交，所述光控行和所述光控列均包括多个所述光控单元；所述光控行包括彼此相邻的第一光控行和第二光控行，给所述与第一光控行提供所述光控栅信号的光控栅线在所述第一衬底的主表面上的正投影、和所述第一光控行的多个子光控单元的光控晶体管在所述第一衬底的主表面上的正投影均位于所述第一光控行的多个子光控单元的第二开口在所述第一衬底的主表面上的正投影与所述第二光控行的多个子光控单元的第二开口在所述第一衬底的主表面上的正投影之间。
例如，在本公开至少一实施例提供的显示面板中，所述多个子光控单元排列成光控阵列；所述光控阵列包括呈阵列排列的多个光控单元，一个所述光控单元包括连续排列的多个所述子光控单元；每个所述光控单元包括沿所述列方向延伸的第一边缘，所述每个光控单元的多个子光控单元在所述行方向上排列且包括最靠近所述第一边缘的边缘子光控单元；位于所述第一边缘处且给所述边缘子光控单元提供所述光控数据信号的所述光控数据线在所述第一衬底的主表面上的正投影与所述每个光控单元的全部子光控单元的第二开口在所述第一衬底的主表面上的正投影不重叠，且与所述全部子光控单元对应的所述子像素的第一开口在所述第一衬底的主表面上的正投影不重叠。
例如，在本公开至少一实施例提供的显示面板中，所述多个子光控单元的每个还包括光控存储电容，所述光控存储电容包括第一极板和第二极板。第一极板为所述像素电极；第二极板与所述光控栅线同层设置且与给该子光控单元提供所述光控栅信号的所述光控栅线电连接；所述光控存储电容的第二极板从与其电连接的所述光控栅线上沿所述列方向突出于所述光控栅线，至少所述第二极板的在所述列方向上远离与其电连接的所述光控栅线的端部 在所述第一衬底的主表面上的正投影与所述像素电极在所述第一衬底的主表面上的正投影重叠。
例如，在本公开至少一实施例提供的显示面板中，每个所述光控单元的所述多个子光控单元包括在所述行方向依次排列的第一子光控单元、第二子光控单元和第三子光控单元，所述第一子光控单元、所述第二子光控单元和所述第三子光控单元对应的所述子像素的发光颜色彼此不同；所述第一子光控单元的光控晶体管与所述第二子光控单元的光控晶体管在所述行方向上的距离为第一距离，所述第二子光控单元的光控晶体管与第三子光控单元的光控晶体管在所述行方向上的距离为第二距离；所述第二距离大于所述第一距离。
例如，在本公开至少一实施例提供的显示面板中，与所述第一子光控单元的光控晶体管的第二极电连接的所述像素电极为第一像素电极，与所述第二子光控单元的光控晶体管的第二极电连接的所述像素电极为第二像素电极，与所述第三子光控单元的光控晶体管的第二极电连接的所述像素电极为第三像素电极；所述第一像素电极与所述第二像素电极在所述列方向上间隔排列，所述第一像素电极和所述第二像素电极构成的整体与所述第三像素电极在所述行方向上排列；所述第一像素电极和所述第二像素电极均覆盖所述第一子光控单元的光控晶体管与所述第二子光控单元的光控晶体管在所述行方向上的间隔的至少部分、以及所述第二子光控单元的光控晶体管与所述第三子光控单元的光控晶体管在所述行方向上的间隔的至少部分，所述第三像素电极覆盖所述第二子光控单元的光控晶体管与所述第三子光控单元的光控晶体管在所述之间行方向上的间隔的至少部分。
例如，在本公开至少一实施例提供的显示面板中，所述第二像素电极在所述列方向上位于所述第一像素电极的远离给该光控单元提供所述光控栅信号的栅线的一侧，所述第三像素电极在所述列方向上与给该光控单元提供所述光控栅信号的栅线之间的距离大于所述第一像素电极在所述列方向上与给该光控单元提供所述光控栅信号的栅线之间的距离；所述第二子光控单元的光控存储电容的第二极板在所述列方向上的长度大于所述第三子光控单元的光控存储电容的第二极板在所述列方向上的长度，且所述第三子光控单元的 光控存储电容的第二极板在所述列方向上的长度大于所述第一子光控单元的光控存储电容的第二极板在所述列方向上的长度。
例如，在本公开至少一实施例提供的显示面板中，所述第三像素电极在所述列方向上的尺寸大于所述第二像素电极在所述列方向上的尺寸，且大于所述第一像素电极在所述列方向上的尺寸；并且，所述第三像素电极在所述列方向上的正投影与所述第一像素电极在所述列方向上的正投影至少部分重叠且与所述第二像素电极在所述列方向上的正投影至少部分重叠。
例如，在本公开至少一实施例提供的显示面板中，所述第一子光控单元的光控晶体管、所述第二子光控单元的光控晶体管和所述第三子光控单元的光控晶体管基本上排列于沿所述行方向延伸的直线上，所述第二子光控单元的光控晶体管的第二极在所述列方向上的尺寸大于所述第三子光控单元的光控晶体管的第二极在所述列方向上的尺寸，所述第三子光控单元的光控晶体管的第二极在所述列方向上的尺寸大于所述第一子光控单元的光控晶体管的第二极在所述列方向上的尺寸。
例如，在本公开至少一实施例提供的显示面板中，所述第二子光控单元的光控晶体管的第二极包括沿所述列方向延伸的延伸部分，所述延伸部分在所述第一衬底的主表面上的正投影位于所述第一子光控单元的第二开口在在所述第一衬底的主表面上的正投影与所述第三子光控单元的第二开口在在所述第一衬底的主表面上的正投影之间。
例如，在本公开至少一实施例提供的显示面板中，与所述第一子光控单元的光控晶体管的第二极电连接的所述像素电极为第一像素电极，与所述第二子光控单元的光控晶体管的第二极电连接的所述像素电极为第二像素电极，与所述第三子光控单元的光控晶体管的第二极电连接的所述像素电极为第三像素电极；所述第一像素电极与所述第二像素电极在所述行方向上间隔排列，所述第二像素电极在所述行方向上的尺寸大于所述第一像素电极在所述行方向上的尺寸，并且，所述第一像素电极覆盖所述第一子光控单元的光控晶体管与所述第二子光控单元的光控晶体管在所述行方向上的间隔的至少部分，所述第二像素电极覆盖所述第二子光控单元的光控晶体管与所述第三子光控单元的光控晶体管在所述之间行方向上的间隔的至少部分。
例如，在本公开至少一实施例提供的显示面板中，所述第一像素电极和所述第二像素电极构成的整体与所述第三像素电极在所述列方向上排列，所述第三像素电极在所述列方向上位于所述第一像素电极和所述第二像素电极构成的整体的远离给该光控单元提供所述光控栅信号的栅线的一侧；所述第三子光控单元的光控存储电容的第二极板在所述列方向上的长度大于所述第一子光控单元的光控存储电容的第二极板在所述列方向上的长度，且大于所述第二子光控单元的光控存储电容的第二极板在所述列方向上的长度。
例如，在本公开至少一实施例提供的显示面板中，所述第三像素电极在所述行方向上的尺寸大于所述第二像素电极在所述行方向上的尺寸，且所述第三像素电极在所述行方向上的正投影与所述第一像素电极在所述行方向上的正投影至少部分重叠且与所述第二像素电极在所述行方向上的正投影至少部分重叠。
例如，在本公开至少一实施例提供的显示面板中，给所述第二子光控单元提供所述光控数据信号的所述光控数据线所述第一衬底的主表面上的正投影位于所述第一像素电极在所述第一衬底的主表面上的正投影与所述第二像素电极在所述第一衬底的主表面上的正投影之间，且与所述第三像素电极在所述第一衬底的主表面上的正投影重叠；给所述第三子光控单元提供所述光控数据信号的所述光控数据线所述第一衬底的主表面上的正投影与所述第二像素电极在所述第一衬底的主表面上的正投影与所述第二像素电极在所述第一衬底的主表面上的正投影重叠，且与所述第三像素电极在所述第一衬底的主表面上的正投影重叠。
例如，在本公开至少一实施例提供的显示面板中，所述第一子光控单元的光控晶体管、所述第二子光控单元的光控晶体管和所述第三子光控单元的光控晶体管基本上排列于沿所述行方向延伸的直线上，所述第三子光控单元的光控晶体管的第二极在所述列方向上的尺寸大于所述第一子光控单元的光控晶体管的第二极在所述列方向上的尺寸和所述第二子光控单元的光控晶体管的第二极在所述列方向上的尺寸；所述第三子光控单元的光控晶体管的第二极的靠近所述第三像素电极的端部在所述第一衬底的主表面上的正投影与所述第三像素电极在所述第一衬底的主表面上的正投影重叠，所述第三子光 控单元的光控晶体管的第二极在所述第一衬底的主表面上的正投影的沿所述列方向延伸的部分还与所述第二像素电极在所述第一衬底的主表面上的正投影重叠。
例如，在本公开至少一实施例提供的显示面板中，所述第一像素电极在所述第一衬底的主表面上的正投影的面积小于所述第二像素电极在所述第一衬底的主表面上的正投影的面积，且所述第二像素电极在所述第一衬底的主表面上的正投影的面积小于所述第三像素电极在所述第一衬底的主表面上的正投影的面积。
例如，在本公开至少一实施例提供的显示面板中，所述第一子光控单元对应的所述子像素发红光，所述第二子光控单元对应的所述子像素发绿光，所述第三子光控单元对应的所述子像素发蓝光。
例如，在本公开至少一实施例提供的显示面板中，所述液晶面板包括第二衬底和与所述第二衬底相对设置的第三衬底，所述第二衬底和所述第三衬底均与所述显示基板在垂直于所述第一衬底的主表面的方向上层叠设置，所述第三衬底位于所述第二衬底的远离所述第一衬底的一侧，所述液晶分子被夹置于所述第二衬底与所述第三衬底之间，所述光控晶体管位于所述第二衬底上；所述像素电极位于所述第二衬底上，所述公共电极位于所述第三衬底上；或者，所述像素电极位于所述第三衬底上，所述公共电极位于所述第二衬底上。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的任意一种显示面板。
本公开至少一实施例还提供一种显示面板的控制方法，该控制方法包括：利用所述光控面板的所述多个子光控单元中的至少部分子光控单元对从所述第一开口出射的光进行调制，以使得从所述第一开口出射的光经过所述多个子光控单元中的至少部分子光控单元的第二开口之后从所述显示面板出射。
例如，在本公开至少一实施例提供的显示面板中，所述显示面板包括靠近所述显示面板的第一边缘的第一边缘显示区、靠近所述显示面板的第二边缘的第二边缘显示区和位于所述第一边缘显示区和位于所述第一边缘显示区和所述第二边缘显示区之间的中间显示区，所述第一边缘与所述第二边缘相 对；在垂直于地面的方向上，所述第一边缘显示区到所示显示面板的观察者的眼盒的距离小于所述第二边缘显示区到所示显示面板的观察者的眼盒的距离；所述控制方法包括：控制在所述第一边缘显示区中从所述第一开口出射的光经所述子光控单元调制后的偏转方向与在所述第二边缘显示区中从所述第一开口出射的光经所述子光控单元调制后的偏转方向相反，以及控制在所述中间显示区中从所述第一开口出射的光经所述子光控单元调制后不发生偏转。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开一实施例提供的一种显示面板中的显示基板的局部平面示意图；
图1B为本公开一实施例提供的一种显示面板中与图1A所示的显示基板堆叠的的光控面板的局部平面示意图；
图1C为本公开一实施例提供的显示面板的局部平面示意图，该显示面板包括彼此堆叠设置的图1A所示的显示基板与图1B所示的光控面板；
图2是图1C所示的显示面板的一个子光控单元与其对应的子像素的截面示意图；
图3是本公开一实施例提供的显示面板的子光控单元的电路图；
图4A-4H是本公开一实施例提供的显示面板的光控面板的多个子光控单元的图层示意图；
图4I是将图4H中的像素电极去掉之后的结构；
图5是本公开一实施例提供的像素电路的电路示意图；
图6A至图11A是本公开一实施例提供的显示基板的各层的局部示意图，图6B为图6A的局部放大图；
图11B是本公开一实施例提供的显示基板的多个像素组的部分膜层的示意图；
图12是本公开一实施例提供的显示基板的一个位置处的局部剖视图；
图13是本公开一实施例提供的显示基板的另一位置处的局部剖视图；
图14A-14E是本公开一实施例提供的另一种显示面板中的显示基板的各层的局部示意图；
图15A是本公开一实施例提供的另一种显示面板中的显示基板的局部平面示意图；
图15B为本公开一实施例提供的另一种显示面板中与图15A所示的显示基板堆叠的光控面板的局部平面示意图；
图16为本公开一实施例提供的一种显示装置的应用示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。以下所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现在该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开实施例的下文中没有特别指出一个成分的数量时，意味着该成分可以是一个也可以是多个，或可理解为至少一个。“至少一个”指一个或多个，“多个”指至少两个。
本公开实施例中的“同层设置”指对同一材料形成的膜层执行同一步骤 (例如同一图案化工艺)后形成的多个膜层之间的关系。这里的“同层设置”并不总是指多个膜层的厚度相同或者多个膜层在截面图中的高度相同。
本公开中使用的“基本重叠”等包含一定误差的情况，考虑到测量和与特定量的测量相关的误差(例如，测量***的限制)，表示在本领域的普通技术人员所确定的对于特定值的可接受的偏差范围内。例如，“基本”能够表示在一个或多个标准偏差内，如无特别说明，可表示在所述值的10％或者5％偏差范围内。
本公开至少一实施例提供一种显示面板，该显示面板包括显示基板和光控面板。显示基板包括第一衬底和设置于所述第一衬底的主表面上的多个子像素，所述多个子像素中的每个具有第一开口，用于生成显示图像的光从所述第一开口出射；光控面板与所述显示基板在垂直于所述第一衬底主表面的方向上层叠设置，包括多个子光控单元，所述多个子光控单元的每个具有第二开口，所述多个子光控单元与所述多个子像素一一对应，从所述第一开口出射的光经过所述多个子光控单元中的至少部分子光控单元的第二开口之后从所述显示面板出射，所述多个子光控单元中的至少部分子光控单元配置为对从所述第一开口出射的光进行调制；所述子光控单元中的每个的第二开口在所述第一衬底的主表面上的正投影与对应的所述子像素的第一开口在所述第一衬底的主表面上的正投影基本重叠。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的任意一种显示面板。
本公开至少一实施例还提供一种显示面板的控制方法，该控制方法包括：利用所述光控面板的所述多个子光控单元中的至少部分子光控单元对从所述第一开口出射的光进行调制，以使得从所述第一开口出射的光经过所述多个子光控单元中的至少部分子光控单元的第二开口之后从所述显示面板出射。
示例性地，图1A为本公开一实施例提供的一种显示面板中的显示基板的局部平面示意图，图1B为本公开一实施例提供的一种显示面板中与图1A所示的显示基板堆叠的的光控面板的局部平面示意图，图1C为本公开一实施例提供的显示面板的局部平面示意图，该显示面板包括彼此堆叠设置的图1A所示的显示基板与图1B所示的光控面板，图2是图1C所示的显示面板 的一个子光控单元与其对应的子像素的截面示意图。如图1A-1C和图2所示，该显示面板10包括显示基板01和光控面板02。显示基板01包括第一衬底1a和设置于第一衬底1a的主表面11上的多个子像素PU1/PU2/PU3。多个子像素PU1/PU2/PU3中的每个具有第一开口。例如，多个子像素PU1/PU2/PU3排列成像素阵列；像素阵列包括呈阵列排列的多个像素单元PU，一个像素单元PU包括连续排列的多个子像素PU1/PU2/PU3；像素阵列包括沿行方向X延伸的像素行和沿列方向Y延伸的像素列，行方向X与列方向Y相交，像素行和像素列均包括多个像素单元PU。例如，每个像素单元PU包括第一子像素PU1、第二子像素PU2和第三子像素PU3，用于生成显示图像的光从显示基板01的第一开口出射至光控面板02。例如，第一子像素PU1具有第一开口OP1，第二子像素PU2具有第一开口OP2，第三子像素PU3具有第一开口OP3。
如图2所示，光控面板02与显示基板01在垂直于第一衬底1a主表面11的方向上层叠设置，且包括多个子光控单元CU1/CU2/CU3，多个子光控单元CU1/CU2/CU3的每个具有第二开口。例如，多个子光控单元CU1/CU2/CU3排列成光控阵列；光控阵列包括呈阵列排列的多个光控单元CU，每个光控单元CU包括连续排列的多个子光控单元CU1/CU2/CU3；例如每个光控单元CU包括第一子光控单元CU1、第二子光控单元CU2和第三子光控单元CU3；第一子光控单元CU1具有第二开口COP1，第二子光控单元CU2具有第二开口COP2，第三子光控单元CU3具有第二开口COP3。光控阵列包括沿行方向X延伸的光控行和沿列方向Y延伸的光控列，光控行和光控列均包括多个光控单元CU。光控面板02的多个子光控单元CU1/CU2/CU3与显示基板01的多个子像素PU1/PU2/PU3一一对应，从第一开口出射的光经过多个子光控单元CU1/CU2/CU3中的至少部分子光控单元的第二开口之后从显示面板10出射，多个子光控单元CU1/CU2/CU3中的至少部分子光控单元配置为对从第一开口出射的光进行调制。每个子光控单元的第二开口在第一衬底1a的主表面11上的正投影与对应的子像素的第一开口在第一衬底1a的主表面11上的正投影基本重叠。例如，第一子光控单元CU1的第二开口COP1在第一衬底1a的主表面11上的正投影与第一子像素PU1的第一开口OP1在第一衬底1a的主表面11上的正投影基本重叠；第二 子光控单元CU2的第二开口COP2在第一衬底1a的主表面11上的正投影与第二子像素PU2的第一开口OP2在第一衬底1a的主表面11上的正投影基本重叠；第三子光控单元CU3的第二开口COP3在第一衬底1a的主表面11上的正投影与第三子像素PU3的第一开口OP3在第一衬底1a的主表面11上的正投影基本重叠。如此，在实现对显示基板01的出光方向进行调节的同时，可以提高整个显示面板10的开口率，避免或降低因设置光控面板02而降低显示基板01的出光率。
当然，这里以每个光控单元包括三个子光控单元、每个像素包括三个子像素的情况为例，在其他实施例中，每个光控单元包括的子光控单元的数量、以及每个像素包括的子像素的数量不限于3个，也可以少于三个或多于三个，本领域技术人员可根据具体需要进行选择。
例如，液晶面板包括光控驱动电路，该光控驱动电路配置为可独立控制液晶面板的多个区域对来自显示基板01的光的调制，从而可实现分区域独立调光。
例如，子光控单元CU1/CU2/CU3中的每个光控单元的第二开口在第一衬底1a的主表面11上的正投影包括与对应的子像素的第一开口在第一衬底1a的主表面11上的正投影重叠的部分的面积与对应的子像素的第一开口在第一衬底1a的主表面11上的正投影的面积的比值大于等于80％，以保证在实现对显示基板01的出光方向进行调节的同时，整个显示面板10具有较高的开口率，较好地避免或降低因设置光控面板02而降低显示基板01的出光率。
例如，子光控单元中的每个的第二开口在第一衬底1a的主表面11上的正投影与对应的子像素的第一开口在第一衬底1a的主表面11上的正投影完全重合。例如，第一子光控单元CU1的第二开口COP1在第一衬底1a的主表面11上的正投影与第一子像素PU1的第一开口OP1在第一衬底1a的主表面11上的正投影完全重合；第二子光控单元CU2的第二开口COP2在第一衬底1a的主表面11上的正投影与第二子像素PU2的第一开口OP2在第一衬底1a的主表面11上的正投影完全重合；第三子光控单元CU3的第二开口COP3在第一衬底1a的主表面11上的正投影与第三子像素PU3的第一开口OP3在第一衬底1a的主表面11上的正投影完全重合，以保证显示面板10 具有更高的开口率，更好地在对显示面板10的出光进行调制的同时，提高显示基板10的出光率。
例如，如图2所示，光控面板02为液晶面板，液晶面板包括第二衬底1b、与第二衬底1b相对设置的第三衬底1c、以及被夹置于第二衬底1b与第三衬底1c之间的液晶层LC，液晶层LC包括液晶分子LCM。第二衬底1b和第三衬底1c均与显示基板01在垂直于第一衬底1a的主表面11的方向上层叠设置，第三衬底1c位于第二衬底1b的远离第一衬底1a的一侧，光控晶体管Tc位于第二衬底1b上；多个子光控单元CU1/CU2/CU3的每个还包括像素电极CE1、公共电极ComE和光控晶体管Tc。
图4A-4H是本公开一实施例提供的显示面板的光控面板的多个子光控单元的图层示意图；图4I是将图4H中的像素电极去掉之后的结构。如图4A-4H所示，光控面板02还包括光控栅线CGL和光控数据线CDL。光控栅线CGL沿行方向X延伸，且与光控晶体管Tc的栅极GATE电连接以给光控晶体管Tc提供光控栅信号；光控数据线CDL沿列方向Y延伸，且与光控晶体管Tc的第一极Sc(例如源极)电连接以给光控晶体管Tc提供光控数据信号。
结合图3所示的光控单元的光控驱动电路图和图2，以一个子光控单元例如第一子光控单元CU1为例，光控晶体管Tc的第二极Dc(例如漏极)与像素电极电连接，以在光控晶体管Tc处于导通状态时对像素电极充电；液晶分子LCM配置为可在像素电极和公共电极ComE之间的电场作用下旋转，以对从第一开口出射的光进行调制，这里的从第一开口出射的对光进行调制包括对出光方向和/或出光强度的调节；公共电极ComE和像素电极与液晶层LC共同构成液晶电容C LC，当像素电极充电之后，则在公共电极ComE和像素电极之间形成电场从而控制液晶层LC中的液晶分子LCM的旋转。即，光控栅线CGL和光控数据线CDL配置为分布提供用于驱动光控面板02的光控单元中的液晶分子LCM的旋转的光控栅信号和光控数据信号，以实现光控面板02对从显示基板01出射的光的出射角角度或强度的调整。
如图2所示，每个光控晶体管还包括栅极GATE，半导体层ACTIVE，液晶面板02还包括位于栅极GATE与半导体层ACTIVE之间的栅绝缘层GI。这些结构可参考本领域常规技术进行设计。
例如，如图2所示，液晶面板02还包括配向层AL，以用于控制液晶分子的初始取向一致，配向层AL的设置以及没有提及的液晶面板的其他部件均可参考常规技术。
参考图1B和图2，与第一子光控单元CU1的光控晶体管Tc的第二极Dc(图4D中的D1)连接的像素电极为第一像素电极CE1，与第二子光控单元CU2的光控晶体管Tc的第二极Dc(图4D中的D2)连接的像素电极为第二像素电极CE2，与第三子光控单元CU3的光控晶体管Tc的第二极Dc(图4D中的D3)电极为第三像素电极CE3。如图1B所示，在每个子光控单元中，第二开口暴露至少部分像素电极。例如，第一子光控单元CU1的第二开口COP1暴露第一像素电极CE1的一部分，第二子光控单元CU2的第二开口COP2暴露第二像素电极CE2的一部分，第三子光控单元CU3的第二开口COP3暴露第三像素电极CE3的一部分。例如，在每个子光控单元中，像素电极的面积大于第二开口的面积；例如，在每个子像素中，第一电极的面积大于第一开口的面积。
例如，如图5所示，多个子像素PU1/PU2/PU3中的每个包括驱动晶体管T1和发光元件220，驱动晶体管T1配置为控制流经发光元件220的驱动电流的大小，发光元件220配置为接收驱动电流且被驱动电流驱动而发光。例如，发光元件220是有机发光元件，子像素包括驱动有机发光元件的像素电路，像素电路包括驱动晶体管T1和发光元件220。例如，如图2所示，有机发光元件包括第一电极E1、第二电极(图2未示出)及位于第一电极E1与第二电极之间的有机发光材料1b。例如，第一电极E1是阳极，第二电极是阴极例如为公共阴极。
例如，如图1A所示，在每个子像素中，第一开口暴露至少部分第一电极。例如，第一子像素PU1的第一开口OP1暴露第一子像素PU1的第一电极E1，第二子像素PU2的第一开口OP2暴露第二子像素PU2的第一电极E2，第三子像素PU3的第一开口OP3暴露第三子像素PU3的第一电极E3。如图1C所示，像素电极在第一衬底1a的主表面11上的正投影与对应的子像素的第一电极在第一衬底1a的主表面11上的正投影基本重合，例如，第一子光控单元CU1的第一像素电极CE1在第一衬底1a的主表面11上的正投影与对应的第一子像素PU1的第一电极E1在第一衬底1a的主表面11上 的正投影基本重合，第二子光控单元CU2的第一像素电极CE2在第一衬底1a的主表面11上的正投影与对应的第二子像素PU2的第一电极E2在第一衬底1a的主表面11上的正投影基本重合，第三子光控单元CU3的第一像素电极CE3在第一衬底1a的主表面11上的正投影与对应的第三子像素PU3的第一电极E3在第一衬底1a的主表面11上的正投影基本重合。例如，每个子光控单元的像素电极在第一衬底1a的主表面11上的正投影与对应的第一电极在第一衬底1a的主表面11上的正投影的重叠的面积与该第一电极在第一衬底1a的主表面11上的正投影的面积的比值大于等于0.8，例如为0.9、0.95。例如，优选地，像素电极在第一衬底1a的主表面11上的正投影与对应的子像素的第一电极在第一衬底1a的主表面11上的正投影完全重合，即每个子光控单元的像素电极在第一衬底1a的主表面11上的正投影与对应的第一电极在第一衬底1a的主表面11上的正投影的重叠的面积与该第一电极在第一衬底1a的主表面11上的正投影的面积的比值为1，以最大程度地提高显示面板10的开口率。
例如，子光控单元的像素电极、公共电极、以及显示基板的子像素的第一电极均是透光的。例如，子光控单元的像素电极、公共电极的材料可以为透明导电材料，例如ITO、IZO等。例如，第一电极的材料可以为金属材料，例如为常用的OLED发光器件的阳极材料。本公开实施例对各个电极的材料种类不作具体限定，本领域技术人员可以根据需求进行选择。
例如，如图2所示，每个子光控单元的光控晶体管Tc在第一衬底1a的主表面11上的正投影与显示基板01的多个子像素PU1/PU2/PU3的第一开口在第一衬底1a的主表面11上的正投影均基本不重叠，且与光控面板02的多个子光控单元的第二开口在第一衬底1a的主表面11上的正投影基本不重叠，即，每个子光控单元的光控晶体管Tc在第一衬底1a的主表面11上的正投影与该光控晶体管Tc所在的子光控单元的第二开口在第一衬底1a的主表面11上的正投影不重叠，且与该子光控单元对应的子像素的第一开口在第一衬底1a的主表面11上的正投影不重叠，以防止光控晶体管遮挡第一开口和第二开口，进一步提高显示面板10的开口率。例如，每个子光控单元的光控晶体管Tc在第一衬底1a的主表面11上的正投影与显示基板01的多个子像素PU1/PU2/PU3的第一开口在第一衬底1a的主表面11上的正投影的重叠的面 积与光控晶体管Tc在第一衬底1a的主表面11上的正投影的面积的比值小于等于0.2，例如为0.1、0.05。例如，优选地，每个子光控单元的光控晶体管Tc在第一衬底1a的主表面11上的整个正投影与显示基板01的多个子像素PU1/PU2/PU3的第一开口在第一衬底1a的主表面11上的正投影均不重叠，即每个子光控单元的光控晶体管Tc在第一衬底1a的主表面11上的正投影与显示基板01的多个子像素PU1/PU2/PU3的第一开口在第一衬底1a的主表面11上的正投影的重叠的面积与光控晶体管Tc在第一衬底1a的主表面11上的正投影的面积的比值为0，以最大程度地提高显示面板10的开口率。
图4A示出了一个光控单元包括的第一子光控单元CU1、第二子光控单元CU2和第三子光控单元CU3的光控晶体管Tc分别包括的第一半导体层ACTIE1、第一半导体层ACTIE2和第三半导体层ACTIE3。
图4B示出了光控栅线CGL、以及第一子光控单元CU1、第二子光控单元CU2和第三子光控单元CU3的光控存储电容的第二极板C21/C22/C23。
图4C示出了图4A与图4B叠加的结构，光控栅线CGL分别与第一半导体层ACTIE1、第一半导体层ACTIE2和第三半导体层ACTIE3重叠而分别构成第一子光控单元CU1、第二子光控单元CU2和第三子光控单元CU3的光控晶体管Tc的沟道区A1/A2/A3。
图4D示出了光控数据线CDL、以及第一子光控单元CU1、第二子光控单元CU2和第三子光控单元CU3的光控晶体管Tc的第二极D1/D2/D3；例如光控数据线CDL与光控晶体管Tc的第二极D1/D2/D3同层设置。
图4E示出了图4C与图4D叠加的结构。
图4F示出了第一子光控单元CU1、第二子光控单元CU2和第三子光控单元CU3的像素电极CE1/CE2/CE3。
图4G示出了图4E与图4F叠加的结构。
图4H示出了图4G叠加第一子光控单元CU1、第二子光控单元CU2和第三子光控单元CU3的第二开口COP1/COP2/COP3之后的示意图。
图4I是将图4H中的像素电极去掉之后的结构。
例如，如图4I所示，光控栅线CGL在第一衬底1a的主表面11上的正投影与显示基板01的多个子像素PU1/PU2/PU3的第一开口在第一衬底1a的主表面11上的正投影均不重叠，且与光控面板02的多个子光控单元 CU1/CU2/CU3的第二开口在第一衬底1a的主表面11上的正投影不重叠，即，每条光控栅线CGL在第一衬底1a的主表面11上的正投影与该光控栅线CGL提供光控栅信号的全部子光控单元的第二开口在第一衬底1a的主表面11上的正投影不重叠，且与该全部子光控单元对应的子像素的第一开口在第一衬底1a的主表面11上的正投影不重叠，以防止光控栅线CGL遮挡第一开口和第二开口，进一步提高显示面板10的开口率。
例如，如图4I所示，光控行包括彼此相邻的第一光控行R1和第二光控行R2，给与第一光控行R1提供光控栅信号的光控栅线CGL在第一衬底1a的主表面11上的正投影、和第一光控行R1的多个子光控单元CU1/CU2/CU3的光控晶体管Tc在第一衬底1a的主表面11上的正投影均位于第一光控行R1的多个子光控单元CU1/CU2/CU3的第二开口COP1/COP2/COP3在第一衬底1a的主表面11上的正投影与第二光控行R2的多个子光控单元COP1/COP2/COP3的第二开口在第一衬底1a的主表面11上的正投影之间，以防止光控栅线CGL遮挡第一开口和第二开口，进一步提高显示面板10的开口率，并合理利用空间来设置光控栅线CGL，能够与显示基板01的多个第一开口的位置相配合，利用显示基板01的非开口区和光控面板02的非开口区设置光控栅线CGL。
例如，如图4H-4I所示，每个光控单元包括沿列方向Y延伸的第一边缘，每个光控单元的多个子光控单元CU1/CU2/CU3在行方向X上排列且包括最靠近第一边缘的边缘子光控单元；位于第一边缘处且给边缘子光控单元提供光控数据信号的光控数据线CDL1在第一衬底1a的主表面11上的正投影与每个光控单元的全部子光控单元的第二开口在第一衬底1a的主表面11上的正投影不重叠，且与全部子光控单元对应的子像素的第一开口在第一衬底1a的主表面11上的正投影不重叠，以使得位于每个光控单元的第一边缘处的光控数据线CDL避开第一开口和第二开口，从而防止该位于每个光控单元的第一边缘处的光控数据线CDL。
例如，结合图2和图3，多个子光控单元CU1/CU2/CU3的每个还包括光控存储电容C，以更好地缓存信号，优化调光效果。光控存储电容C包括第一极板C1和第二极板C2。第一极板C1为像素电极；第二极板C2与光控栅线CGL同层设置且与给该子光控单元提供光控栅信号的光控栅线CGL电连 接，例如第二极板C2与光控栅线CGL同层设置且与给该子光控单元提供光控栅信号的光控栅线CGL构成一体成型结构，以通过对同一膜层执行同一构图工艺形成光控栅线和光控存储电容的第二极板，简化显示面板的结构和制作工艺。
需要说明的是，本公开中，构成“一体成型结构”的多个结构是指该多个结构为连续的、无接缝的采用同一材料形成的整体，该多个结构可以是通过对同一膜层执行同一次构图工艺而形成的。
例如，如图4B和4G所示，对于每个子光控单元，光控存储电容C的第二极板C2从与其电连接的光控栅线CGL上沿列方向Y突出于该光控栅线CGL，至少第二极板C2的在列方向Y上远离与其电连接的光控栅线CGL的端部在第一衬底1a的主表面11上的正投影与像素电极在第一衬底1a的主表面11上的正投影重叠。第一子光控单元CU1的存储电容C的第二极板C21在第一衬底1a的主表面11上的正投影与第一像素电极CE1在第一衬底1a的主表面11上的正投影重叠，第二子光控单元CU2的存储电容C的第二极板C22在第一衬底1a的主表面11上的正投影与第二像素电极CE2在第一衬底1a的主表面11上的正投影重叠，第三子光控单元CU3的存储电容C的第二极板C23在第一衬底1a的主表面11上的正投影与第三像素电极CE3在第一衬底1a的主表面11上的正投影重叠。
例如，每个光控单元的多个子光控单元CU1/CU2/CU3包括在行方向X依次排列的第一子光控单元CU1、第二子光控单元CU2和第三子光控单元CU3，第一子光控单元CU1、第二子光控单元CU2和第三子光控单元CU3对应的子像素的发光颜色彼此不同。如图4E所示，第一子光控单元CU1的光控晶体管Tc与第二子光控单元CU2的光控晶体管Tc在行方向X上的距离为第一距离d1，第二子光控单元CU2的光控晶体管Tc与第三子光控单元CU3的光控晶体管Tc在行方向X上的距离为第二距离d2；以给第一子光控单元CU1提供光控数据信号的光控数据线CDL1与给第二子光控单元CU2提供光控数据信号的光控数据线CDL2的彼此相对的边之间的距离作为第一距离d1，以给第二子光控单元CU2提供光控数据信号的光控数据线CDL2与给第三子光控单元CU3提供光控数据信号的光控数据线CDL3的彼此相对的边之间的距离作为第二距离d2。第二距离d2与第一距离d1不相等。例如， 第二距离d2大于第一距离d1，以适应一个光控单元的多个子光控单元的排布和一个光控单元的多个子光控单元在行方向上不同的尺寸。
如图4E所示，在至少部分子光控单元中，例如在第二子光控单元中，第二极板C22还与光控晶体管Tc的第二极D2交叠，例如部分交叠(在其他实施例中也可以整个第二极板C22与光控晶体管Tc的第二极D2交叠)，以构成另一存储电容，以更好地缓存信号，优化调光效果。
例如，结合图4H和图4E，第一像素电极CE1与第二像素电极CE2在列方向Y上间隔排列，第一像素电极CE1和第二像素电极CE2构成的整体与第三像素电极CE3在行方向X上排列；第一像素电极CE1和第二像素电极CE2均覆盖第一子光控单元CU1的光控晶体管Tc与第二子光控单元CU2的光控晶体管Tc在行方向X上的间隔的至少部分、以及第二子光控单元CU2的光控晶体管Tc与第三子光控单元CU3的光控晶体管Tc在行方向X上的间隔的至少部分，第三像素电极CE3覆盖第二子光控单元CU2的光控晶体管Tc与第三子光控单元CU3的光控晶体管Tc在之间行方向X上的间隔的至少部分。例如，第一像素电极CE1在第一衬底1a的主表面11上的正投影的面积小于第二像素电极CE2在第一衬底1a的主表面11上的正投影的面积，且第二像素电极CE2在第一衬底1a的主表面11上的正投影的面积小于第三像素电极CE3在第一衬底1a的主表面11上的正投影的面积。如此，面积较小的在列方向上排列的第一像素电极CE1和第二像素电极CE2对应于较小的第一距离d1，面积较大的第三像素电极CE3对应于较大的第二距离d2，可以尽量减少空间的浪费，利于实现高PPI显示面板。
例如，如图4D所示，第二像素电极CE2在列方向Y上位于第一像素电极CE1的远离给该光控单元提供光控栅信号的栅线的一侧，第三像素电极CE3在列方向Y上与给该光控单元提供光控栅信号的栅线之间的距离大于第一像素电极CE1在列方向Y上与给该光控单元提供光控栅信号的栅线之间的距离；第二子光控单元CU2的光控存储电容C的第二极板C22在列方向Y上的长度大于第三子光控单元CU3的光控存储电容C的第二极板C23在列方向Y上的长度，且第三子光控单元CU3的光控存储电容C的第二极板C23在列方向Y上的长度大于第一子光控单元CU1的光控存储电容C的第二极板C21在列方向Y上的长度，以与第一像素电极CE1、第二像素电极 CE2和第三像素电极CE3的位置相适应。
例如，如图4G所示，第三像素电极CE3在列方向Y上的尺寸大于第二像素电极CE2在列方向Y上的尺寸，且大于第一像素电极CE1在列方向Y上的尺寸；并且，第三像素电极CE3在列方向Y上的正投影与第一像素电极CE1在列方向Y上的正投影至少部分重叠且与第二像素电极CE2在列方向Y上的正投影至少部分重叠。
例如，结合图4D和图4G，第一子光控单元CU1的光控晶体管Tc、第二子光控单元CU2的光控晶体管Tc和第三子光控单元CU3的光控晶体管Tc基本上排列于沿行方向X延伸的直线上，第二子光控单元CU2的光控晶体管Tc的第二极D2在列方向Y上的尺寸大于第三子光控单元CU3的光控晶体管Tc的第二极D3在列方向Y上的尺寸，第三子光控单元CU3的光控晶体管Tc的第二极D3在列方向Y上的尺寸大于第一子光控单元CU1的光控晶体管Tc的第二极D1在列方向Y上的尺寸，以与第一像素电极CE1、第二像素电极CE2和第三像素电极CE3的位置相适应，第二极D1、第二极D2和第二极D3分别用于与第一像素电极CE1、第二像素电极CE2和第三像素电极CE3电连接。例如通过贯穿图2所示的第一绝缘层L1的第一过孔V1电连接。并且，每个子光控单元的光控晶体管的第二极D1/D2/D3均包括沿列方向延伸的延伸部，例如二极D1的延伸部在列方向在列方向Y上的尺寸大于第二极D3的延伸部在列方向Y上的尺寸，且第二极D3的延伸部在列方向Y上的尺寸大于第二极D1的延伸部在列方向Y上的尺寸。
例如，结合图4E和图4H所示，对于每个子光控单元，光控晶体管Tc的第二极D1/D2/D3在第一衬底1a的主表面11上的正投影与第二开口在第一衬底1a的主表面11上的正投影不重叠，以尽可能地提高显示面板10的开口率。该“不重叠”包括完全不重叠，或者两者重叠的面积占第二开口的面积的5％～10％内。优选光控晶体管Tc的第二极D1/D2/D3在第一衬底1a的主表面11上的正投影与第二开口在第一衬底1a的主表面11上的正投影完全不重叠。
例如，如图4H所示，第二子光控单元CU2的光控晶体管Tc的第二极D2的沿列方向Y延伸的延伸部分D2E在第一衬底1a的主表面11上的正投影位于第一子光控单元CU1的第二开口在在第一衬底1a的主表面11上的正 投影与第三子光控单元CU3的第二开口在第一衬底1a的主表面11上的正投影之间，以利用第一像素电极CE1和第二像素电极CE2构成的整体与第三像素电极CE3之间的非显示区设置延伸部分D2E，利用了多个子光控单元的位置关系，合理利用了有限的空间，从而防止延伸部分D2E遮挡第一开口和第二开口，进一步增加显示面板10的开口率。
需要说明的是，本公开实施例中，显示基板的多个第一电极的排列方式和光控面板的多个像素电极的排列方式不限于上述方式，可根据需要进行设计，只要两者的正投影重叠即可。
例如，如图2所示，在光控面板02是液晶面板的情况下，子光控单元的像素电极CE1可以与公共电极ComE分别位于彼此相对的不同的衬底上。例如，子光控单元的像素电极CE1位于第二衬底1b上，公共电极ComE位于第三衬底1c上。或者，在其他一些实施例中，像素电极位于第三衬底1c上，公共电极ComE位于第二衬底1b上。这种情况下，像素电极CE1可以与公共电极ComE形成TN型电场。这种实施例中，可以有更大的空间来设计像素电极CE1的排布方式，像素电极CE1的排布自由度较高，更有利于光控面板02的第二开口与显示基板01的第一开口在垂直于第一衬底的主表面方向上重合，以及更有利于光控面板02的像素电极与显示基板01的第一电极在垂直于第一衬底的主表面方向上重合，容易实现较高的重合率，从而获得具有较高开口率的显示面板10。
当然，本公开的光控面板02的电场不限于TN型，在其他实施例中，子光控单元的像素电极CE1也可以与公共电极ComE位于同一衬底上，例如均位于第二衬底1b上，例如像素电极CE1与公共电极ComE形成IPS型水平电场。
显示基板01也可以不采用图7所示的第一电极11/12/13的排列方式，也可以采用本公开的图4H所示的第一电极的排列方式。
示例性地，下面对显示基板01的一种子像素的结构进行介绍。在一个实施例中，如图5所示，像素电路221包括驱动电路222。驱动电路222包括控制端、第一端和第二端，且被配置为对有机发光元件220提供驱动有机发光元件220发光的驱动电流。
在一个实施例中，如图5所示，像素电路221包括第一发光控制电路223 和第二发光控制电路224。例如，第一发光控制电路223与驱动电路222的第一端和第一电压端VDD连接，且被配置为实现驱动电路222和第一电压端VDD之间的连接导通或断开，第二发光控制电路224与驱动电路222的第二端和有机发光元件220的第一电极电连接，且被配置为实现驱动电路222和有机发光元件220之间的连接导通或断开。
在一个实施例中，如图5所示，像素电路221还包括数据写入电路226、存储电路227、阈值补偿电路228和复位电路229。数据写入电路226与驱动电路222的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储电路227。存储电路227与驱动电路222的控制端和第一电压端VDD电连接，且被配置为存储数据信号。阈值补偿电路228与驱动电路222的控制端和第二端电连接，且被配置为对驱动电路222进行阈值补偿。复位电路229与驱动电路222的控制端和有机发光元件220的第一电极电连接，且配置为在复位控制信号的控制下对驱动电路222的控制端和有机发光元件220的第一电极进行复位。
在一个实施例中，如图5所示，驱动电路222包括驱动晶体管T1，驱动电路222的控制端包括驱动晶体管T1的栅极，驱动电路222的第一端包括驱动晶体管T1的第一极，驱动电路222的第二端包括驱动晶体管T1的第二极。
在一个实施例中，如图5所示，数据写入电路226包括数据写入晶体管T2，存储电路227包括电容Cst，阈值补偿电路228包括阈值补偿晶体管T3，第一发光控制电路223包括第一发光控制晶体管T4，第二发光控制电路224包括第二发光控制晶体管T5，复位电路229包括第一复位晶体管T6和第二复位晶体管T7，复位控制信号可以包括第一子复位控制信号和第二子复位控制信号。
在一个实施例中，如图5所示，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线Vd电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与扫描信号线Ga1电连接以接收扫描信号；电容Cst的第一极与第一电源端VDD电连接，电容Cst的第二极与驱动晶体管T1的栅极电连接；阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与 驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与扫描信号线Ga2电连接以接收补偿控制信号；第一复位晶体管T6的第一极被配置为与复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的栅极电连接，第一复位晶体管T6的栅极被配置为与复位控制信号线Rst1电连接以接收第一子复位控制信号；第二复位晶体管T7的第一极被配置为与复位电源端Vinit2电连接以接收第二复位信号，第二复位晶体管T7的第二极与有机发光元件220的第一电极电连接，第二复位晶体管T7的栅极被配置为与复位控制信号线Rst2电连接以接收第二子复位控制信号；第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶体管T4的栅极被配置为与发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与有机发光元件220的第二电极电连接，第二发光控制晶体管T5的栅极被配置为与发光控制信号线EM2电连接以接收第二发光控制信号；有机发光元件220的第一电极与第二电源端VSS电连接。
在一个实施例中，第一电源端VDD和第二电源端VSS中的其中一个为高压端，另一个为低压端。图5所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。在一些示例性实施例中，第二电源端VSS可以接地。
在一个实施例中，如图5所示，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极可以电连接到同一条信号线，例如扫描信号线Ga1，以接收相同的信号(例如，扫描信号)，此时，显示基板1000可以不设置扫描信号线Ga2，减少信号线的数量。又例如，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T2的栅极电连接到扫描信号线Ga1，阈值补偿晶体管T3的栅极电连接到扫描信号线Ga2，而扫描信号线Ga1和扫描信号线Ga2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得数据 写入晶体管T2的栅极和阈值补偿晶体管T3可以被分开单独控制，增加控制像素电路的灵活性。
在一个实施例中，如图5所示，第一发光控制信号和第二发光控制信号可以相同，即，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极可以电连接到同一条信号线，例如发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板1000可以不设置发光控制信号线EM2，减少信号线的数量。在其他实施例中，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T4的栅极电连接到发光控制信号线EM1，第二发光控制晶体管T5的栅极电连接到发光控制信号线EM2，而发光控制信号线EM1和发光控制信号线EM2传输的信号相同。
需要说明的是，当第一发光控制晶体管T4和第二发光控制晶体管T5为不同类型的晶体管，例如，第一发光控制晶体管T4为P型晶体管，而第二发光控制晶体管T5为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本申请的实施例对此不作限制。
在一个实施例中，第一子复位控制信号和第二子复位控制信号可以相同，即，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极可以电连接到同一条信号线，例如复位控制信号线Rst1，以接收相同的信号(例如，第一子复位控制信号)，此时，显示基板1000可以不设置复位控制信号线Rst2，减少信号线的数量。又例如，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极也可以分别电连接至不同的信号线，即第一复位晶体管T6的栅极电连接到复位控制信号线Rst1，第二复位晶体管T7的栅极电连接到复位控制信号线Rst2，而复位控制信号线Rst1和复位控制信号线Rst2传输的信号相同。需要说明的是，第一子复位控制信号和第二子复位控制信号也可以不相同。在另一实施例中，第一子复位控制信号与第二子复位控制信号不同，复位控制信号线Rst2的脉冲宽度大于复位控制信号线Rst1的脉冲宽度，且复位控制信号线Rst2的脉冲宽度小于第二发光控制晶体管T5在截止时发光控制信号线EM2的脉冲宽度。如此有助于提升子像素的有机发光元件的寿命。
在一个实施例中，第二子复位控制信号可以与扫描信号相同，即第二复位晶体管T7的栅极可以电连接到扫描信号线Ga1以接收扫描信号作为第二 子复位控制信号。
在一个实施例中，第一复位晶体管T6的栅极和第二复位晶体管T7的源极分别连接到第一复位电源端Vinit1和第二复位电源端Vinit2，第一复位电源端Vinit1和第二复位电源端Vinit2可以为直流参考电压端，以输出恒定的直流参考电压。第一复位电源端Vinit1和第二复位电源端Vinit2可以相同，例如第一复位晶体管T6的栅极和第二复位晶体管T7的源极连接到同一复位电源端。第一复位电源端Vinit1和第二复位电源端Vinit2可以为高压端，也可以为低压端，只要其能够提供第一复位信号和第二复位信号以对驱动晶体管T1的栅极和发光元件220的第一电极进行复位即可，本申请对此不作限制。
需要说明的是，图5所示的像素电路中的驱动电路222、数据写入电路226、存储电路227、阈值补偿电路228和复位电路229仅为示意性的，驱动电路222、数据写入电路226、存储电路227、阈值补偿电路228和复位电路229等电路的具体结构可以根据实际应用需求进行设定，本申请的实施例对此不作具体限定。
按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本申请的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本申请的技术方案，也就是说，在本申请的描述中，驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7等均可以为P型晶体管。当然本申请的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本申请的实施例中的一个或多个晶体管的功能。
需要说明的是，本申请的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本申请的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本申请的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
需要说明的是，在本申请实施例中，子像素的像素电路除了可以为图5所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本申请实施例对此不作限定。
图6A-11为本申请一实施例提供的一种像素电路的各层的示意图。下面结合附图6A-11描述像素电路中的各个电路在背板上的位置关系，图6A-11所示的示例以一个像素组的像素电路221为例，且以第一颜色子像素110包括的像素电路的各晶体管的位置进行示意，第二颜色子像素120与第三颜色子像素130中像素电路包括的部件与第一颜色子像素包括的各晶体管的位置大致相同。如图6A所示，该第一颜色子像素110的像素电路221包括图5所示的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7及电容Cst。
图6A-11还示出了电连接到各个颜色子像素的像素电路121的扫描信号线Ga1、复位控制信号线Rst1、复位电源信号线Init1、发光控制信号线EM1、数据线Vd、电源信号线(包括第一电源端VDD的第一电源信号线VDD1、第二电源信号线VDD3和第三电源信号线VDD2)及屏蔽线344。第一电源信号线VDD1和第二电源信号线VDD3彼此电连接，第一电源信号线VDD1和第三电源信号线VDD2彼此电连接。所述第二电源线VDD3包括沿所述第一方向Y延伸的第一子电源线VDD31及沿所述第二方向X延伸的第二子电源线VDD32，所述第一子电源线VDD31与所述第二子电源线VDD32相交。
扫描信号线Ga1被配置为为像素组提供扫描信号；复位控制信号线Rst1被配置为为像素组提供复位控制信号；复位电源信号线Init1被配置为为像素组提供复位电源信号；发光控制信号线EM1被配置为为像素组提供发光控制信号；数据线Vd被配置为为像素组提供发光数据信号；第一电源信号线VDD1、第二电源信号线VDD3及第三电源信号线VDD2被配置为为像素组提供电源信号。
例如，图6A示出了该显示基板中像素电路的有源半导体层310。有源半导体层310可采用半导体材料图案化形成。有源半导体层310可用于制作上述的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控 制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的沟道。有源半导体层310包括各子像素的各晶体管的沟道和源漏区(即第二颜色子像素中示出的源极区域s和漏极区域d)，且同一像素电路中的各晶体管的沟道和源漏区一体设置。图6A中示出的有源半导体层310包括第一颜色子像素的沟道301、第二颜色子像素的沟道302和第三颜色子像素的沟道303。
需要说明的是，有源半导体层可以包括一体形成的低温多晶硅层，其中的源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个子像素的各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素电路中的各晶体管包括源漏区(即源极区域s和漏极区域d)和沟道，不同晶体管的沟道之间由源漏区隔开。
在一个实施例中，沿第一方向排列的不同颜色子像素的像素电路中的有源半导体层没有连接关系，彼此断开。沿第二方向排列的相同颜色子像素的像素电路中的有源半导体层可以为一体设置，也可以彼此断开。
在一个实施例中，有源半导体层310可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
例如，像素电路的栅极金属层可以包括第一导电层和第二导电层。在上述的有源半导体层310上形成有栅极绝缘层103(如图12和图13所示)，用于保护上述的有源半导体层310，有源半导体层310位于衬底基板100上。图7示出了该显示基板包括的第一导电层320，第一导电层320设置在栅极绝缘层上，从而与有源半导体层310绝缘。第一导电层320可以包括电容Cst的第二极板CC2、扫描信号线Ga1、复位控制信号线Rst1、发光控制信号线EM1以及驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的栅极。扫描信号线Ga1包括扫描信号线主体部Ga11及由由所述扫描信号线主体部Ga11的一侧凸出的凸出部P。
例如，如图7所示，数据写入晶体管T2的栅极可以为扫描信号线Ga1与有源半导体层310交叠的部分；第一发光控制晶体管T4的栅极可以为发光控制信号线EM1与有源半导体层310交叠的第一部分，第二发光控制晶 体管T5的栅极可以为发光控制信号线EM1与有源半导体层310交叠的第二部分；第一复位晶体管T6的栅极为复位控制信号线Rst1与有源半导体层310交叠的第一部分，第二复位晶体管T7的栅极为复位控制信号线Rst1与有源半导体层310交叠的第二部分；阈值补偿晶体管T3可为双栅结构的薄膜晶体管，阈值补偿晶体管T3的第一个栅极可为扫描信号线Ga1与有源半导体层310交叠的部分，阈值补偿晶体管T3的第二个栅极可为扫描信号线Ga1的突出部P与有源半导体层310交叠的部分。如图5和3所示，驱动晶体管T1的栅极可为电容Cst的第二极板CC2。
需要说明的是，图6A中的各虚线矩形框示出了第一导电层320与有源半导体层310交叠的各个部分。
例如，如图7所示，扫描信号线Ga1、复位控制信号线Rst1和发光控制信号线EM1沿第二方向X排布。扫描信号线Ga1位于复位控制信号线Rst1和发光控制信号线EM1之间。其中信号线沿第一方向延伸指的是，信号线整体行沿第一方向延伸，信号线在第一方向上延伸的部分的面积远大于在第二方向上延伸的部分的面积；信号线沿第二方向延伸指的是，信号线整体行沿第二方向延伸，信号线在第二方向上延伸的部分的面积远大于在第一方向上延伸的部分的面积。
例如，在第二方向X上，电容Cst的第二极板CC2(即驱动晶体管T1的栅极)位于扫描信号线Ga1和发光控制信号线EM1之间。扫描信号线Ga1的突出部P位于扫描信号线Ga1的远离发光控制信号线EM1的一侧。
例如，如图6A所示，在第二方向X上，数据写入晶体管T2的栅极、阈值补偿晶体管T3的栅极、第一复位晶体管T6的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第一侧，第一发光控制晶体管T4的栅极、第二发光控制晶体管T5的栅极均位于驱动晶体管T1的栅极的第二侧。例如，图6A-11所示的示例中，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第一侧和第二侧为在第二方向X上驱动晶体管T1的栅极的彼此相对的两侧。例如，如图6A-11所示，在XY面内，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第一侧可以为驱动晶体管T1的栅极的上侧，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第二侧可以为驱动晶体管T1的栅极的下侧。所述下侧，例如显示基板的用于绑定驱动芯片 的一侧为显示基板的下侧，驱动晶体管T1的栅极的下侧，为驱动晶体管T1的栅极的更靠近驱动芯片的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管T1的栅极的更远离驱动芯片的一侧。
例如，在一些实施例中，如图6A-11所示，在第一方向Y上，数据写入晶体管T2的栅极和第一发光控制晶体管T4的栅极均位于驱动晶体管T1的栅极的第三侧，阈值补偿晶体管T3的第一个栅极、第二发光控制晶体管T5的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第四侧。例如，图6A-11所示的示例中，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第三侧和第四侧为在第一方向Y上驱动晶体管T1的栅极的彼此相对的两侧。例如，如图6A-11所示，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第三侧可以为第一颜色子像素的像素电路的驱动晶体管T1的栅极的左侧，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第四侧可以为第一颜色子像素的像素电路的驱动晶体管T1的栅极的右侧。所述左侧和右侧，例如在同一像素电路中，数据线在第一电源信号线VDD1左侧，第一电源信号线VDD1在数据线右侧。
例如，在上述的第一导电层320上形成有第一绝缘层104(如图12和图13所示)，用于保护上述的第一导电层320。图8示出了该像素电路的第二导电层330，第二导电层330包括电容Cst的第一极板CC1、复位电源信号线Init1、第三电源信号线VDD2以及遮光部S。第三电源信号线VDD2与电容Cst的第一极板CC1一体形成。电容Cst的第一极板CC1与电容Cst的第二极板CC2至少部分重叠以形成电容Cst。
例如，在上述的第二导电层330上形成有第二绝缘层105(如图12和图13所示)，用于保护上述的第二导电层330。图9示出了该像素电路的源漏极金属层340，源漏极金属层340包括数据线Vd、第一电源信号线VDD1以及屏蔽线344。上述数据线Vd、第一电源信号线VDD1以及屏蔽线344均沿第二方向X延伸。屏蔽线344与数据线Vd同层同材料设置，使得屏蔽线可与数据线在同一次构图工艺中同时形成，避免为了制作屏蔽线而增加额外的构图工艺，从而简化了显示基板的制作流程，节约了制作成本。例如，源漏极金属层340还包括连接结构341、连接部342和电极连接结构的第一子电极连接结构343。所述连接结构341的一端与所述驱动晶体管T1的栅极连接， 所述连接结构341的另一端与所述阈值补偿晶体管T3的源漏区连接。
图9还示出了多个过孔的示例性位置，源漏金属层340通过所示的多个过孔与位于该源漏金属层340与衬底基板之间的多个膜层连接。例如，源漏金属层340通过过孔381、过孔382、过孔384、过孔387及过孔352连接至图6A所示的有源半导体层310，源漏金属层340通过过孔3832、过孔386、过孔385、过孔331及过孔332连接至图8所示的第二导电层330。
例如，在上述的源漏极金属层340上形成有第三绝缘层106和第四绝缘层107(如图12和图13所示)，用于保护上述的源漏极金属层340。各个子像素的有机发光元件可设置在第三绝缘层和第四绝缘层远离衬底基板的一侧。
图10示出了该像素电路的第三导电层350，第三导电层350包括电极连接结构的第二子电极连接结构353以及沿第二方向X和第一方向Y交叉分布的第二电源信号线VDD3。图10还示出了多个过孔351和过孔354的示例性位置，第三导电层350通过所示的多个过孔351和过孔354与源漏金属层340连接。
图11A为上述的有源半导体层310、第一导电层320、第二导电层330、源漏极金属层340以及第三导电层350的层叠位置关系的示意图。如图6A-11所示，数据线Vd通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔381)与有源半导体层310中的数据写入晶体管T2的源极区域相连。第一电源信号线VDD1通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔382)与有源半导体层310中对应的第一发光控制晶体管T4的源极区域相连。
如图6A-11所示，连接结构341的一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔384)与有源半导体层310中对应的阈值补偿晶体管T3的漏极区域相连，连接结构341的另一端通过第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔385)与第一导电层320中的驱动晶体管T1的栅极(即电容Cst的第二极板CC2)相连。连接部342的一端通过第二绝缘层中的一个过孔(例如，过孔386)与复位电源信号线Init1相连，连接部342的另一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔387)与有源半导体层310中的第二复位晶 体管T7的漏极区域相连。第一子电极连接结构343通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔352)与有源半导体层310中的第二发光控制晶体管T5的漏极区域相连。需要说明的是，本公开实施例中采用的晶体管的源极区域和漏极区域在结构上可以是相同的，所以其源极区域和漏极区域在结构上可以是没有区别的，因此根据需要二者是可以互换的。
例如，如图6A-11所示，第一电源信号线VDD1通过位于第二导电层330和源漏金属层340之间的第二绝缘层中的至少一个过孔(例如，过孔3832)与第二导电层330中的电容Cst的第一极板CC1相连。
例如，如图6A-11所示，屏蔽线344沿第二方向X延伸，且其在衬底基板上的正投影位于驱动晶体管在衬底基板上的正投影与数据线在衬底基板上的正投影之间。例如，第一颜色子像素的像素电路中的屏蔽线能够减小第二颜色子像素的像素电路中的数据线上传输的信号对第一颜色子像素的阈值补偿晶体管T3的性能产生的影响，进而减小第一颜色子像素的驱动晶体管的栅极和第二颜色子像素的数据线之间的耦合的影响，减弱串扰问题。
例如，如图6A-11所示，屏蔽线344通过第二绝缘层中的至少一个过孔(例如过孔332)与复位电源信号线Init1相连，除了使得屏蔽线具有固定电位之外，还使得复位电源信号线上传输的初始化信号的电压更稳定，从而更有利于像素驱动电路的工作性能。
例如，如图6A-11所示，屏蔽线344与复位电源信号线电连接，以使屏蔽线具有固定电位。屏蔽线344可分别与沿Y方向延伸的两条复位电源信号线Init1电连接，且这两条复位电源信号线Init1分别位于屏蔽线344沿X方向的两侧。例如，这两条复位电源信号线分别与第n行像素电路和第n+1行像素电路对应。
例如，同一列屏蔽线344可以为一整条屏蔽线，该整条屏蔽线包括多个位于相邻两条复位电源信号线之间的子部分，且每一子部分分别位于该列的每个像素电路区域内。
例如，除了将屏蔽线344与复位电源信号线耦接外，还可以将屏蔽线344与第一电源信号线耦接，使得屏蔽线344具有与第一电源信号线传输的电源信号相同的固定电位。
例如，屏蔽线344在衬底基板上的正投影位于阈值补偿晶体管T3在衬底基板上的正投影与数据线Vd在衬底基板上的正投影之间，使得屏蔽线344能够减小由于数据线上传输的信号变化对阈值补偿晶体管T3的性能产生的影响，进而减小驱动晶体管的栅极和数据信号线Vd(n+1)之间的耦合的影响，解决垂直串扰的问题，使得显示基板在用于显示时能够获得更好的显示效果。
例如，屏蔽线344在衬底基板上的正投影可以位于连接结构341在衬底基板上的正投影与数据线在衬底基板上的正投影之间；屏蔽线344在衬底基板上的正投影位于驱动晶体管T1在衬底基板上的正投影与数据线在衬底基板上的正投影之间。
上述设置方式很好的降低了数据线与阈值补偿晶体管之间产生的第一串扰，以及数据线与连接结构之间产生的第二串扰，从而降低了由于上述第一串扰和第二串扰导致的对驱动晶体管产生的间接串扰。另外，上述设置方式还降低了数据线与驱动晶体管之间产生的直接串扰，从而更好的保证了显示基板的工作性能。
例如，屏蔽线344不仅限于上述设置方式，屏蔽线344还可以仅与对应于第n行像素电路的复位电源信号线耦接，或者仅与对应于第n+1行像素电路的复位电源信号线耦接。而且，屏蔽线344在第二方向X的延伸长度也可根据实际需要设置。
例如，各颜色子像素的像素电路还包括遮光部S，遮光部S与屏蔽线344异层设置，且遮光部S在衬底基板上的正投影与屏蔽线344在衬底基板上的正投影有交叠。屏蔽线344通过第二绝缘层中的过孔331与第二导电层330中的遮光部S相连，使遮光部S具有固定电位，从而更好的减小了阈值补偿晶体管T3与其附近的其他导电图形之间的耦合作用，使得显示基板的工作性能更稳定。
例如，遮光部S与阈值补偿晶体管T3的两个栅极之间的有源半导体层310有交叠以防止两个栅极之间的有源半导体层310被光照而改变特性，例如防止该部分有源半导体层的电压发生变化，以防止产生串扰。
本示例示意性的示出遮光部与屏蔽线相连，但不限于此，两者也可以不连接。
例如，如图6A-11所示，第二电源信号线VDD3通过第三绝缘层和第四绝缘层中的至少一个过孔351与第一电源信号线VDD1相连，第二子电极连接结构353通过第三绝缘层和第四绝缘层中的过孔354与第一子电极连接结构343相连。
例如，第三绝缘层可以为钝化层，第四绝缘层可以为平坦化层，第三绝缘层位于第四绝缘层与衬底基板之间。第四绝缘层可以为有机层，且有机层的厚度较钝化层等无机层厚。
例如，过孔351和过孔354均为嵌套过孔，即过孔351包括第三绝缘层中的第一过孔和第四绝缘层中的第二过孔，第三绝缘层中的第一过孔与第四绝缘层中的第二过孔的位置相对，且第四绝缘层中的第二过孔在衬底基板上的正投影位于第三绝缘层中的第一过孔在衬底基板上的正投影内。
例如，第二电源信号线VDD3呈网格状分布，第二电源信号线VDD3的沿X方向延伸的第二子电源线VDD32在衬底基板上的正投影与第一电源信号线VDD1在衬底基板上的正投影大致重合或者第一电源信号线VDD1在衬底基板上的正投影位于第二子电源线VDD32在衬底基板上的正投影内，且第二电源信号线VDD3与第一电源信号线VDD1电连接可以降低第一电源信号线VDD1的电压降，从而改善显示器件的均一性。
例如，第二电源信号线VDD3可以与源漏金属层采用相同的材料。
例如，如图9所示，第一颜色子像素、第二颜色子像素和第三颜色子像素的第一子电极连接结构343均为块状结构。后续形成的各颜色子像素的第一电极会通过过孔与相应的第二子电极连接结构353连接以实现与第二发光控制晶体管T5的漏极区域相连。
本实施例包括但不限于此，各颜色子像素中的第二子电极连接结构的位置根据有机发光元件的排列规律以及发光区域的位置而定。
例如，图12为图11A所在的显示基板的局部截面结构示意图，图11A仅示意了图12中的部分膜层。如图11A和8所示，第二颜色子像素120的像素电路中有源半导体层中的第二发光控制晶体管T5的第二极(例如为漏极T5d)远离衬底基板100的一侧设置有栅极绝缘层103，栅极绝缘层103远离衬底基板100的一侧设置有发光控制信号线EM1，发光控制信号线EM1远离衬底基板100的一侧设置有第一绝缘层104，第一绝缘层104远离衬底 基板100的一侧设置有第三电源信号线VDD2，第三电源信号线VDD2远离衬底基板100的一侧设置有第二绝缘层105，第二绝缘层105远离衬底基板100的一侧设置有第一子电极连接结构343。第二颜色子像素120的第一子电极连接结构343通过栅极绝缘层103、第一绝缘层104以及第二绝缘层105的过孔352与有源半导体层310中的第二发光控制晶体管T5的第二极T5d相连。第一子电极连接结构343与第三电源信号线VDD2和发光控制信号线EM1均有交叠。第一子电极连接结构343远离衬底基板100的一侧依次设置有第三绝缘层106和第四绝缘层107，第四绝缘层107远离衬底基板100的一侧设置有第二子电极连接结构353以及第二电源信号线VDD3。第二电源信号线VDD3与第三电源信号线VDD2有交叠。第二子电极连接结构353通过位于第三绝缘层106和第四绝缘层107中的嵌套过孔354与第一子电极连接结构343相连，进而实现与第二发光控制晶体管相连。
例如，如图12所示，数据线Vd通过栅极绝缘层103、第一绝缘层104和第二绝缘层105中的过孔381与数据写入晶体管T2的源极T2s相连；连接结构341的一端通过栅极绝缘层103、第一绝缘层104和第二绝缘层105中的过孔384与阈值补偿晶体管T3的漏极T3d相连，连接结构341的另一端通过第一绝缘层104和第二绝缘层105中的过孔385与驱动晶体管T1的栅极(即电容Cst的第二极板CC2)相连；驱动晶体管T1的沟道T1c位于其栅极面向衬底基板100的一侧，且与过孔385没有交叠，驱动晶体管T1的源极T1d与其栅极以及电容Cst的第一极板CC1均有交叠。
例如，图13为图11A所在的显示基板的局部截面结构示意图，图11A仅示意出了图13中的部分膜层。如图11A-13所示，第一颜色子像素110与第二颜色子像素120不同之处在于第二颜色子像素120中的第二子电极连接结构353在衬底基板100上的正投影与其第二发光控制晶体管T5的第二极T5d在衬底基板100上的正投影没有交叠，而第一颜色子像素130中的第二子电极连接结构353在衬底基板100上的正投影与其第二发光控制晶体管T5的第二极T5d在衬底基板100上的正投影有交叠。第一颜色子像素110中，第一子电极连接结构343与第三电源信号线VDD2和发光控制信号线EM1均没有交叠。第一颜色子像素110中，驱动晶体管T1的沟道T1c位于其栅极面向衬底基板100的一侧，且与过孔385有交叠。由此可以看出第一颜色 子像素的驱动晶体管的沟道宽度大于第二颜色子像素的沟道宽度。
例如，如图6A-11所示，在第二方向X上，扫描信号线Ga1、复位控制信号线Rst1和复位电源信号线Init1均位于第一颜色子像素的像素电路的驱动晶体管T1的栅极的第一侧，发光控制信号线EM1位于第一颜色子像素的像素电路的驱动晶体管T1的第二侧。
例如，扫描信号线Ga1、复位控制信号线Rst1、发光控制信号线EM1、和复位电源信号线Init1均沿第一方向Y延伸，数据线Vd沿第二方向X延伸。
需要说明的是，每个像素电路中的驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、存储电路、阈值补偿电路和复位电路等的位置排布关系不限于图6A-11所示的示例，根据实际应用需求，可以具体设置驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、存储电路、阈值补偿电路和复位电路的位置。
例如，如图6A-13所示，第一颜色子像素的第一电极11通过第五绝缘层的过孔(未示出)与第二子电极连接结构353相连，从而实现与第二发光控制晶体管T5的漏极区域相连。同理，第三颜色子像素的有机发光元件的第一电极13通过第五绝缘层的过孔(未示出)与第二子电极连接结构353相连，从而实现与第二发光控制晶体管T5的漏极区域相连。第二颜色子像素的第一电极12通过第五绝缘层的过孔与第二子电极连接结构353相连，进而与第二子电极连接结构343相连，以实现与第二发光控制晶体管T5的漏极区域相连。
例如，图14A-14E是本公开一实施例提供的另一种显示面板中的显示基板的各层的局部示意图，该显示基板与图8A-8I所示的光控面板堆叠而构成图1C所示的显示面板10。
该显示基板的像素电路与图5所示的相同，该显示基板的子像素的结构与图6A-13所示的实施例主要存在以下不同之处。图14A-14D仅示出了位于同一像素行的几个子像素作为示例。
图14A示出了该显示基板中像素电路的有源半导体层310和第一导电层320的叠加示意图。有源半导体层310可用于制作上述的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光 控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的沟道。第一导电层320设置在栅极绝缘层上，从而与有源半导体层310绝缘。第一导电层320可以包括电容Cst的第二极板CC2、扫描信号线Ga1、复位控制信号线Rst1、发光控制信号线EM1/EM2(例如用于给第一发光控制晶体管T4、第二发光控制晶体管T5提供发光控制信号的发光控制信号线共用为同一条信号线)以及驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的栅极。
图14B示出了像素电路的第二导电层330，第二导电层330包括存储电容的第一极板CC1、第一复位电源信号线Init1、第二复位电源信号线Init2、第三电源信号线VDD2以及遮光部S2。第三电源信号线VDD2与电容C的第一极板CC1一体形成。电容Cst的第一极板CC1与电容C的第二极板CC2至少部分重叠以形成电容Cst。
图14C示出了该像素电路的源漏极金属层340，源漏极金属层340包括数据线Vd、第一电源信号线VDD1等。图14D示出了有源半导体层310、第二导电层330和源漏极金属层340叠加的示意图。如图14D所示，第二复位电源信号线Init2通过过孔V2与连接结构CP1电连接，连接结构CP1通过过孔V3与第二复位晶体管T7的源极(或漏极)电连接。第一复位电源信号线Init1与第一复位晶体管T6的连接方式与之前的实施例中的类似，其他相似或相同的结构在此不再重复。
图14E示出了包括第一子像素PU1的第一电极E1、第二子像素PU2的第一电极E2和第三子像素PU3的第一电极E3的示意图。图14E所示的第一电极E1、第一电极E2和第一电极E3的排布方式与图1A所示的显示面板的三个子像素的第一电极的排布方式相同，且在显示面板10中，该第一电极E1、第一电极E2和第一电极E3在第一衬底的主表面上的正投影分别与图8H所示的光控面板02的第一像素电极CE1、第二像素电极CE2和第三像素电极CE3在第一衬底的主表面上的正投影对应重叠，具体的排布方式请见之前的描述。
当然，上述显示基板01的子像素结构都是示例性的，不限于上述实施例的情况，也可以是其他种类的子像素结构，只要满足本申请实施例中对于与 光控面板02的匹配的要求即可，本领域技术人员可根据具体需要进行设计。
图15A是本公开一实施例提供的另一种显示面板中的显示基板的局部平面示意图，图15B为本公开一实施例提供的另一种显示面板中与图15A所示的显示基板堆叠的光控面板的局部平面示意图。图15A-15B所示的实施例与图1A-1C具有以下区别。例如，在图15A-15B所示的实施例中，第一像素电极CE1与第二像素电极CE2在行方向X上间隔排列，第二像素电极CE2在行方向X上的尺寸大于第一像素电极CE1在行方向X上的尺寸，并且，第一像素电极CE1覆盖第一子光控单元CU1的光控晶体管Tc与第二子光控单元CU2的光控晶体管Tc在行方向X上的间隔的至少部分，第二像素电极CE2覆盖第二子光控单元CU2的光控晶体管Tc与第三子光控单元CU3的光控晶体管Tc在之间行方向X上的间隔的至少部分。
例如，如图15B所示，第一像素电极CE1和第二像素电极CE2构成的整体与第三像素电极CE3在列方向Y上排列，第三像素电极CE3在列方向Y上位于第一像素电极CE1和第二像素电极CE2构成的整体的远离给该光控单元提供光控栅信号的栅线的一侧；第三子光控单元CU3的光控存储电容C的第二极板C23在列方向Y上的长度大于第一子光控单元CU1的光控存储电容C的第二极板C21在列方向Y上的长度，且大于第二子光控单元CU2的光控存储电容C的第二极板C22在列方向Y上的长度，以适应于第一像素电极CE1和第二像素电极CE2构成的整体与第三像素电极CE3的排布方式。例如，第二子光控单元CU2的光控存储电容C的第二极板C22在列方向Y上的长度与第一子光控单元CU1的光控存储电容C的第二极板C21在列方向Y上的长度基本相等。
并且，如图15B所示，第三子光控单元CU3的光控存储电容C的第二极板C23的在列方向Y上的端部CT(较小的白色椭圆形虚线框所示的部分)与第三像素电极CE3重叠，连接端部CT与光控栅线CGL的连接部CEP(较小的白色椭圆形虚线框所示的部分)在列方向Y上延伸，且连接部CEP在第一衬底1a的主表面11上的正投影与第一子光控单元CU1的第二开口COP1、第二子光控单元CU2的第二开口COP2和第三子光控单元CU3的第二开口COP3在第一衬底1a的主表面11上的正投影均不重叠，以合理在有限的空间中利用非显示区来设置较长的连接部CEP，避免连接部CEP遮挡各 个第二开口，从而尽可能地提高整个显示面板10的开口率。
例如，如图15B所示，第三像素电极CE3在行方向X上的尺寸大于第二像素电极CE2在行方向X上的尺寸，且第三像素电极CE3在行方向X上的正投影与第一像素电极CE1在行方向X上的正投影至少部分重叠且与第二像素电极CE2在行方向X上的正投影至少部分重叠。
例如，如图15B所示，给第二子光控单元CU2提供光控数据信号的光控数据线CDL2的第一部分在第一衬底1a的主表面11上的正投影位于第一像素电极CE1在第一衬底1a的主表面11上的正投影与第二像素电极CE2在第一衬底1a的主表面11上的正投影之间，且光控数据线CDL2的第二部分与第三像素电极CE3在第一衬底1a的主表面11上的正投影重叠；给第三子光控单元CU3提供光控数据信号的光控数据线CDL第一衬底1a的主表面11上的正投影与第二像素电极CE2在第一衬底1a的主表面11上的正投影与第二像素电极CE2在第一衬底1a的主表面11上的正投影重叠，且与第三像素电极CE3在第一衬底1a的主表面11上的正投影重叠，以尽可能地避免信号线遮挡第二开口，提高显示面板10的开口率。
例如，第一子光控单元CU1的光控晶体管Tc、第二子光控单元CU2的光控晶体管Tc和第三子光控单元CU3的光控晶体管Tc基本上排列于沿行方向X延伸的直线上，第三子光控单元CU3的光控晶体管Tc的第二极D3在列方向Y上的尺寸大于第一子光控单元CU1的光控晶体管Tc的第二极D1在列方向Y上的尺寸和第二子光控单元CU2的光控晶体管Tc的第二极D2在列方向Y上的尺寸；第三子光控单元CU3的光控晶体管Tc的第二极D3的靠近第三像素电极CE3的端部在第一衬底1a的主表面11上的正投影与第三像素电极CE3在第一衬底1a的主表面11上的正投影重叠，第三子光控单元CU3的光控晶体管Tc的第二极D3在第一衬底1a的主表面11上的正投影的沿列方向Y延伸的部分还与第二像素电极CE2在第一衬底1a的主表面11上的正投影重叠，以兼顾PPI和开口率。例如三子光控单元CU3的光控晶体管Tc的第二极Dc为沿列方向Y延伸的条形结构。
或者，在其他实施例中，第三子光控单元的光控晶体管的第二极在第一衬底的主表面上的正投影的沿列方向Y延伸的部分与第一像素电极、第二像素电极和第三像素电极在第一衬底的主表面11上的正投影不存在重叠，以获 具有更大的开口率的显示面板。
例如，在图15A-15B所示的实施例中，第一像素电极CE1在第一衬底1a的主表面11上的正投影的面积小于第二像素电极CE2在第一衬底1a的主表面11上的正投影的面积，且第二像素电极CE2在第一衬底1a的主表面11上的正投影的面积小于第三像素电极CE3在第一衬底1a的主表面11上的正投影的面积。例如，第一子光控单元CU1对应的子像素发红光，第二子光控单元CU2对应的子像素发绿光，第三子光控单元CU3对应的子像素发蓝光，以平衡不同颜色的发光材料的发光强度和寿命。例如，显示基板01的子像素的发光元件为有机发光二极管器件，当然也可以是其他类型的电致发光器件。
图15A-15B所示的实施例的其他未提及的结构可参考图1A-4I所示的实施例中的描述。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的任意一种显示面板10。该显示装置具有显示面板10所具有的技术效果，在此不再重复。例如，该显示装置可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、车载显示装置例如导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
本公开至少一实施例还提供一种本公开实施例提供的任意一种显示面板10的控制方法，包括：利用光控面板02的多个子光控单元CU1/CU2/CU3中的至少部分子光控单元对从第一开口出射的光进行调制，以使得从第一开口出射的光经过多个子光控单元CU1/CU2/CU3中的至少部分子光控单元的第二开口之后从显示面板10出射。
图16为本公开一实施例提供的一种显示装置的应用示意图。例如，显示面板10包括靠近显示面板10的第一边缘的第一边缘显示区A1、靠近显示面板10的第二边缘的第二边缘显示区A2和位于第一边缘显示区A1和位于第一边缘显示区A1和第二边缘显示区A2之间的中间显示区AM，第一边缘与第二边缘相对；在垂直于地面的方向上，第一边缘显示区A1到所示显示面板10的观察者的眼盒AE的距离小于第二边缘显示区A2到所示显示面板10的观察者的眼盒AE的距离；控制方法包括：控制在第一边缘显示区A1中从第一开口出射的光经子光控单元调制后的偏转方向与在第二边缘显示区A2中从第一开口出射的光经子光控单元调制后的偏转方向相反，以及控制在 中间显示区AM中从第一开口出射的光经子光控单元调制后不发生偏转。例如，显示面板10被应用于驾驶场景，作为导航仪或娱乐显示设备，这种情况下，例如，第一边缘显示区A1相对于第二边缘显示区A2距离地面较远且距离司机的眼盒较近；一方面，可以控制第一边缘显示区A1中的液晶分子偏转以避免从第一边缘显示区A1出射的光传播到挡风玻璃，更多地使从第一边缘显示区A1出射的光传播到眼盒，防止从显示面板10出射的光在挡风玻璃上成像而干扰司机的驾驶视野；另一方面，可以控制第二边缘显示区A2中的液晶分子偏转以更多地使从第二边缘显示区A2出射的光传播到眼盒，使司机更全面地观看到第二边缘显示区A2的图像。例如，显示面板10为曲面屏，曲面屏的表面为朝向观察者凸出的曲面。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围根据权利要求书所界定的范围确定。

Claims (27)

  1. 一种显示面板，包括：
    显示基板，包括第一衬底和设置于所述第一衬底的主表面上的多个子像素，其中，所述多个子像素中的每个具有第一开口，用于生成显示图像的光从所述第一开口出射；以及
    光控面板，与所述显示基板在垂直于所述第一衬底主表面的方向上层叠设置，包括多个子光控单元，其中，所述多个子光控单元的每个具有第二开口，所述多个子光控单元与所述多个子像素一一对应，从所述第一开口出射的光经过所述多个子光控单元中的至少部分子光控单元的第二开口之后从所述显示面板出射，所述多个子光控单元中的至少部分子光控单元配置为对从所述第一开口出射的光进行调制；
    所述子光控单元中的每个的第二开口在所述第一衬底的主表面上的正投影与对应的所述子像素的第一开口在所述第一衬底的主表面上的正投影基本重叠。
  2. 根据权利要求1所述的显示面板，其中，所述子光控单元中的每个的第二开口在所述第一衬底的主表面上的正投影包括与对应的所述子像素的第一开口在所述第一衬底的主表面上的正投影重叠的部分的面积与对应的所述子像素的第一开口在所述第一衬底的主表面上的正投影的面积的比值大于等于80％。
  3. 根据权利要求2所述的显示面板，其中，所述子光控单元中的每个的第二开口在所述第一衬底的主表面上的正投影与对应的所述子像素的第一开口在所述第一衬底的主表面上的正投影完全重合。
  4. 根据权利要求1-3任一所述的显示面板，其中，所述光控面板为液晶面板，所述多个子光控单元的每个还包括像素电极、液晶分子、公共电极和光控晶体管；
    所述光控面板还包括：
    光控栅线，沿所述行方向延伸，且与所述光控晶体管的栅极电连接以给所述光控晶体管提供光控栅信号；以及
    光控数据线，沿所述列方向延伸，且与所述光控晶体管的第一极电连接以给所述光控晶体管提供光控数据信号，其中，
    所述光控晶体管的第二极与所述像素电极电连接，所述液晶分子配置为可在所述像素电极和所述公共电极之间的电场作用下旋转，以对从所述第一开口出射的光进行调制；在每个所述子光控单元中，所述第二开口暴露至少部分所述像素电极。
  5. 根据权利要求4所述的显示面板，其中，所述多个子像素中的每个包括驱动晶体管和发光元件，所述驱动晶体管配置为控制流经所述发光元件的驱动电流的大小，所述发光元件配置为接收所述驱动电流且被所述驱动电流驱动而发光，且包括第一电极；在每个所述子像素中，所述第一开口暴露至少部分所述第一电极；
    所述像素电极在所述第一衬底的主表面上的正投影与对应的所述子像素的第一电极在所述第一衬底的主表面上的正投影基本重合。
  6. 根据权利要求4或5所述的显示面板，其中，
    每个所述子光控单元的光控晶体管在所述第一衬底的主表面上的正投影与所述显示基板的所述多个子像素的第一开口在所述第一衬底的主表面上的正投影均不重叠，且与所述光控面板的多个所述子光控单元的第二开口在所述第一衬底的主表面上的正投影不重叠。
  7. 根据权利要求4-6任一所述的显示面板，其中，
    所述光控栅线在所述第一衬底的主表面上的正投影与所述显示基板的所述多个子像素的第一开口在所述第一衬底的主表面上的正投影均不重叠，且与所述光控面板的多个所述子光控单元的第二开口在所述第一衬底的主表面上的正投影不重叠。
  8. 根据权利要求7所述的显示面板，其中，所述多个子光控单元排列成光控阵列；所述光控阵列包括呈阵列排列的多个光控单元，一个所述光控单元包括连续排列的多个所述子光控单元；所述光控阵列包括沿行方向延伸的光控行和沿列方向延伸的光控列，所述行方向与所述列方向相交，所述光控行和所述光控列均包括多个所述光控单元；
    所述光控行包括彼此相邻的第一光控行和第二光控行，给所述与第一光 控行提供所述光控栅信号的光控栅线在所述第一衬底的主表面上的正投影、和所述第一光控行的多个子光控单元的光控晶体管在所述第一衬底的主表面上的正投影均位于所述第一光控行的多个子光控单元的第二开口在所述第一衬底的主表面上的正投影与所述第二光控行的多个子光控单元的第二开口在所述第一衬底的主表面上的正投影之间。
  9. 根据权利要求4-8任一所述的显示面板，其中，所述多个子光控单元排列成光控阵列；所述光控阵列包括呈阵列排列的多个光控单元，一个所述光控单元包括连续排列的多个所述子光控单元；
    每个所述光控单元包括沿所述列方向延伸的第一边缘，所述每个光控单元的多个子光控单元在所述行方向上排列且包括最靠近所述第一边缘的边缘子光控单元；
    位于所述第一边缘处且给所述边缘子光控单元提供所述光控数据信号的所述光控数据线在所述第一衬底的主表面上的正投影与所述每个光控单元的全部子光控单元的第二开口在所述第一衬底的主表面上的正投影不重叠，且与所述全部子光控单元对应的所述子像素的第一开口在所述第一衬底的主表面上的正投影不重叠。
  10. 根据权利要求5所述的显示面板，其中，所述多个子光控单元的每个还包括光控存储电容，所述光控存储电容包括：
    第一极板，为所述像素电极；
    第二极板，与所述光控栅线同层设置且与给该子光控单元提供所述光控栅信号的所述光控栅线电连接，其中，
    所述光控存储电容的第二极板从与其电连接的所述光控栅线上沿所述列方向突出于所述光控栅线，至少所述第二极板的在所述列方向上远离与其电连接的所述光控栅线的端部在所述第一衬底的主表面上的正投影与所述像素电极在所述第一衬底的主表面上的正投影重叠。
  11. 根据权利要求10所述的显示面板，其中，每个所述光控单元的所述多个子光控单元包括在所述行方向依次排列的第一子光控单元、第二子光控单元和第三子光控单元，所述第一子光控单元、所述第二子光控单元和所述第三子光控单元对应的所述子像素的发光颜色彼此不同；
    所述第一子光控单元的光控晶体管与所述第二子光控单元的光控晶体管在所述行方向上的距离为第一距离，所述第二子光控单元的光控晶体管与第三子光控单元的光控晶体管在所述行方向上的距离为第二距离；
    所述第二距离大于所述第一距离。
  12. 根据权利要求11所述的显示面板，其中，与所述第一子光控单元的光控晶体管的第二极电连接的所述像素电极为第一像素电极，与所述第二子光控单元的光控晶体管的第二极电连接的所述像素电极为第二像素电极，与所述第三子光控单元的光控晶体管的第二极电连接的所述像素电极为第三像素电极；
    所述第一像素电极与所述第二像素电极在所述列方向上间隔排列，所述第一像素电极和所述第二像素电极构成的整体与所述第三像素电极在所述行方向上排列；
    所述第一像素电极和所述第二像素电极均覆盖所述第一子光控单元的光控晶体管与所述第二子光控单元的光控晶体管在所述行方向上的间隔的至少部分、以及所述第二子光控单元的光控晶体管与所述第三子光控单元的光控晶体管在所述行方向上的间隔的至少部分，所述第三像素电极覆盖所述第二子光控单元的光控晶体管与所述第三子光控单元的光控晶体管在所述之间行方向上的间隔的至少部分。
  13. 根据权利要求12所述的显示面板，其中，
    所述第二像素电极在所述列方向上位于所述第一像素电极的远离给该光控单元提供所述光控栅信号的栅线的一侧，所述第三像素电极在所述列方向上与给该光控单元提供所述光控栅信号的栅线之间的距离大于所述第一像素电极在所述列方向上与给该光控单元提供所述光控栅信号的栅线之间的距离；
    所述第二子光控单元的光控存储电容的第二极板在所述列方向上的长度大于所述第三子光控单元的光控存储电容的第二极板在所述列方向上的长度，且所述第三子光控单元的光控存储电容的第二极板在所述列方向上的长度大于所述第一子光控单元的光控存储电容的第二极板在所述列方向上的长度。
  14. 根据权利要求13所述的显示面板，其中，所述第三像素电极在所述列方向上的尺寸大于所述第二像素电极在所述列方向上的尺寸，且大于所述第一像素电极在所述列方向上的尺寸；并且，所述第三像素电极在所述列方向上的正投影与所述第一像素电极在所述列方向上的正投影至少部分重叠且与所述第二像素电极在所述列方向上的正投影至少部分重叠。
  15. 根据权利要求13或14所述的显示面板，其中，所述第一子光控单元的光控晶体管、所述第二子光控单元的光控晶体管和所述第三子光控单元的光控晶体管基本上排列于沿所述行方向延伸的直线上，所述第二子光控单元的光控晶体管的第二极在所述列方向上的尺寸大于所述第三子光控单元的光控晶体管的第二极在所述列方向上的尺寸，所述第三子光控单元的光控晶体管的第二极在所述列方向上的尺寸大于所述第一子光控单元的光控晶体管的第二极在所述列方向上的尺寸。
  16. 根据权利要求12-15任一所述的显示面板，其中，所述第二子光控单元的光控晶体管的第二极包括沿所述列方向延伸的延伸部分，所述延伸部分在所述第一衬底的主表面上的正投影位于所述第一子光控单元的第二开口在在所述第一衬底的主表面上的正投影与所述第三子光控单元的第二开口在在所述第一衬底的主表面上的正投影之间。
  17. 根据权利要求11所述的显示面板，其中，与所述第一子光控单元的光控晶体管的第二极电连接的所述像素电极为第一像素电极，与所述第二子光控单元的光控晶体管的第二极电连接的所述像素电极为第二像素电极，与所述第三子光控单元的光控晶体管的第二极电连接的所述像素电极为第三像素电极；
    所述第一像素电极与所述第二像素电极在所述行方向上间隔排列，所述第二像素电极在所述行方向上的尺寸大于所述第一像素电极在所述行方向上的尺寸，并且，
    所述第一像素电极覆盖所述第一子光控单元的光控晶体管与所述第二子光控单元的光控晶体管在所述行方向上的间隔的至少部分，所述第二像素电极覆盖所述第二子光控单元的光控晶体管与所述第三子光控单元的光控晶体管在所述之间行方向上的间隔的至少部分。
  18. 根据权利要求17所述的显示面板，其中，所述第一像素电极和所述第二像素电极构成的整体与所述第三像素电极在所述列方向上排列，所述第三像素电极在所述列方向上位于所述第一像素电极和所述第二像素电极构成的整体的远离给该光控单元提供所述光控栅信号的栅线的一侧；
    所述第三子光控单元的光控存储电容的第二极板在所述列方向上的长度大于所述第一子光控单元的光控存储电容的第二极板在所述列方向上的长度，且大于所述第二子光控单元的光控存储电容的第二极板在所述列方向上的长度。
  19. 根据权利要求18所述的显示面板，其中，所述第三像素电极在所述行方向上的尺寸大于所述第二像素电极在所述行方向上的尺寸，且所述第三像素电极在所述行方向上的正投影与所述第一像素电极在所述行方向上的正投影至少部分重叠且与所述第二像素电极在所述行方向上的正投影至少部分重叠。
  20. 根据权利要求18或19所述的显示面板，其中，给所述第二子光控单元提供所述光控数据信号的所述光控数据线所述第一衬底的主表面上的正投影位于所述第一像素电极在所述第一衬底的主表面上的正投影与所述第二像素电极在所述第一衬底的主表面上的正投影之间，且与所述第三像素电极在所述第一衬底的主表面上的正投影重叠；
    给所述第三子光控单元提供所述光控数据信号的所述光控数据线所述第一衬底的主表面上的正投影与所述第二像素电极在所述第一衬底的主表面上的正投影与所述第二像素电极在所述第一衬底的主表面上的正投影重叠，且与所述第三像素电极在所述第一衬底的主表面上的正投影重叠。
  21. 根据权利要求18-20任一所述的显示面板，其中，所述第一子光控单元的光控晶体管、所述第二子光控单元的光控晶体管和所述第三子光控单元的光控晶体管基本上排列于沿所述行方向延伸的直线上，所述第三子光控单元的光控晶体管的第二极在所述列方向上的尺寸大于所述第一子光控单元的光控晶体管的第二极在所述列方向上的尺寸和所述第二子光控单元的光控晶体管的第二极在所述列方向上的尺寸；
    所述第三子光控单元的光控晶体管的第二极的靠近所述第三像素电极的 端部在所述第一衬底的主表面上的正投影与所述第三像素电极在所述第一衬底的主表面上的正投影重叠，所述第三子光控单元的光控晶体管的第二极在所述第一衬底的主表面上的正投影的沿所述列方向延伸的部分还与所述第二像素电极在所述第一衬底的主表面上的正投影重叠。
  22. 根据权利要求11-21任一所述的显示面板，其中，所述第一像素电极在所述第一衬底的主表面上的正投影的面积小于所述第二像素电极在所述第一衬底的主表面上的正投影的面积，且所述第二像素电极在所述第一衬底的主表面上的正投影的面积小于所述第三像素电极在所述第一衬底的主表面上的正投影的面积。
  23. 根据权利要求11-22任一所述的显示面板，其中，所述第一子光控单元对应的所述子像素发红光，所述第二子光控单元对应的所述子像素发绿光，所述第三子光控单元对应的所述子像素发蓝光。
  24. 根据权利要求4-23任一所述的显示面板，其中，所述液晶面板包括第二衬底和与所述第二衬底相对设置的第三衬底，所述第二衬底和所述第三衬底均与所述显示基板在垂直于所述第一衬底的主表面的方向上层叠设置，所述第三衬底位于所述第二衬底的远离所述第一衬底的一侧，所述液晶分子被夹置于所述第二衬底与所述第三衬底之间，所述光控晶体管位于所述第二衬底上；
    所述像素电极位于所述第二衬底上，所述公共电极位于所述第三衬底上；或者，
    所述像素电极位于所述第三衬底上，所述公共电极位于所述第二衬底上。
  25. 一种显示装置，包括根据权利要求1-24任一所述的显示面板。
  26. 一种根据权利要求1-24任一所述的显示面板的控制方法，包括：
    利用所述光控面板的所述多个子光控单元中的至少部分子光控单元对从所述第一开口出射的光进行调制，以使得从所述第一开口出射的光经过所述多个子光控单元中的至少部分子光控单元的第二开口之后从所述显示面板出射。
  27. 根据权利要求26所述的显示面板的控制方法，其中，
    所述显示面板包括靠近所述显示面板的第一边缘的第一边缘显示区、靠 近所述显示面板的第二边缘的第二边缘显示区和位于所述第一边缘显示区和位于所述第一边缘显示区和所述第二边缘显示区之间的中间显示区，所述第一边缘与所述第二边缘相对；
    在垂直于地面的方向上，所述第一边缘显示区到所示显示面板的观察者的眼盒的距离小于所述第二边缘显示区到所示显示面板的观察者的眼盒的距离；
    所述控制方法包括：
    控制在所述第一边缘显示区中从所述第一开口出射的光经所述子光控单元调制后的偏转方向与在所述第二边缘显示区中从所述第一开口出射的光经所述子光控单元调制后的偏转方向相反，以及
    控制在所述中间显示区中从所述第一开口出射的光经所述子光控单元调制后不发生偏转。
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WO2023000174A1 (zh) 2023-01-26
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