WO2024113163A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

Info

Publication number
WO2024113163A1
WO2024113163A1 PCT/CN2022/135049 CN2022135049W WO2024113163A1 WO 2024113163 A1 WO2024113163 A1 WO 2024113163A1 CN 2022135049 W CN2022135049 W CN 2022135049W WO 2024113163 A1 WO2024113163 A1 WO 2024113163A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
transistor
layer
gate
orthographic projection
Prior art date
Application number
PCT/CN2022/135049
Other languages
English (en)
French (fr)
Inventor
李硕
石领
陈友春
尚延阳
刘畅畅
闫政龙
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/135049 priority Critical patent/WO2024113163A1/zh
Publication of WO2024113163A1 publication Critical patent/WO2024113163A1/zh

Links

Images

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • the electrode portion of the light-emitting unit in the display panel has poor flatness.
  • a display panel includes: a base substrate, a first source-drain layer, a second source-drain layer, an electrode layer, and a pixel definition layer, wherein the first source-drain layer is located on one side of the base substrate, and the first source-drain layer includes a data line; the second source-drain layer is located on a side of the first source-drain layer away from the base substrate, and the second source-drain layer includes a power line; the electrode layer is located on a side of the second source-drain layer away from the base substrate, and the electrode layer includes a plurality of electrode portions; the pixel definition layer is located on a side of the electrode layer away from the base substrate, and a plurality of pixel openings are formed on the pixel definition layer, the pixel openings are arranged corresponding to the electrode portions, and the orthographic projection of the pixel openings on the base substrate coincides with the orthographic projection of the electrode portions on the base substrate;
  • the display panel further includes: a first planar layer and a second planar layer, wherein the first planar layer is located between the first source-drain layer and the second source-drain layer; and the second planar layer is located between the second source-drain layer and the electrode layer.
  • the display panel also includes a green light-emitting unit; the plurality of electrode portions include a first electrode portion, and the first electrode portion is used to form a first electrode of the green light-emitting unit; the orthographic projection of the first electrode portion on the base substrate and the orthographic projection of the data line on the base substrate at least partially overlap.
  • the display panel also includes a blue light-emitting unit and a red light-emitting unit;
  • the electrode layer also includes: a second electrode portion and a third electrode portion, the second electrode portion is used to form a first electrode of the blue light-emitting unit, and the orthographic projection of the second electrode portion on the base substrate is located on the orthographic projection of the power line on the base substrate;
  • the third electrode portion is used to form the first electrode of the red light-emitting unit, and the orthographic projection of the third electrode portion on the base substrate is located on the orthographic projection of the power line on the base substrate.
  • the display panel also includes a green light-emitting unit, a blue light-emitting unit, and a red light-emitting unit;
  • the multiple electrode portions include: a first electrode portion, a second electrode portion, and a third electrode portion, the first electrode portion is used to form a first electrode of the green light-emitting unit, and the orthographic projection of the first electrode portion on the substrate is located on the orthographic projection of the power line on the substrate;
  • the second electrode portion is used to form a first electrode of the blue light-emitting unit, and the orthographic projection of the second electrode portion on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate;
  • the third electrode portion is used to form a first electrode of the red light-emitting unit, and the orthographic projection of the third electrode portion on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.
  • the display panel includes a plurality of repeating units, and the plurality of repeating units are arranged in an array in a first direction and a second direction, and the first direction and the second direction intersect;
  • the repeating unit includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same repeating unit are arranged in mirror symmetry.
  • the pixel driving circuit includes a driving transistor and a fifth transistor, the second electrode of the fifth transistor is connected to the first electrode of the driving transistor; the first source and drain layer also includes: a first bridge portion, the first bridge portion is connected to the first electrode of the fifth transistor, and the first bridge portion is connected to the power line through a via; in the pixel driving circuits located in different repetition units and adjacent in the first direction, the orthographic projection of the data line on the substrate is located between the orthographic projections of two adjacent first bridge portions on the substrate.
  • the orthographic projection of the data line on the substrate extends along the second direction, and the data line includes a first extension portion, a second extension portion, and a third extension portion, and the second extension portion is connected between the first extension portion and the third extension portion; in the pixel driving circuits located in different repeating units and adjacent to each other in the first direction, the first extension portions in two adjacent data lines are arranged relative to each other in the first direction, the second extension portions in two adjacent data lines are arranged relative to each other in the first direction, and the third extension portions in two adjacent data lines are arranged relative to each other in the first direction; the distance between the orthographic projections of two adjacent second extension portions on the substrate in the first direction is greater than the distance between the orthographic projections of two adjacent first extension portions on the substrate in the first direction; the distance between the orthographic projections of two adjacent second extension portions on the substrate in the first direction is greater than the distance between the orthographic projections of two adjacent third extension portions on the substrate in the first direction.
  • the pixel driving circuit further includes a driving transistor, a second transistor, and a fourth transistor, wherein a first electrode of the second transistor is connected to a gate electrode of the driving transistor, a second electrode of the second transistor is connected to a second electrode of the driving transistor, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;
  • the display panel further includes: a first gate line and a second gate line, wherein an orthographic projection of the first gate line on the substrate extends along the first direction, and a partial structure of the first gate line is used to form a gate electrode of the second transistor; an orthographic projection of the second gate line on the substrate extends along the first direction, and a partial structure of the second gate line is used to form a gate electrode of the fourth transistor; an orthographic projection of at least a partial structure of the second extension portion on the substrate is located between an orthographic projection of the first gate line on the substrate and an orthographic projection of the
  • the pixel definition layer is a black pixel definition layer; a light-transmitting hole is also formed on the pixel definition layer, the light-transmitting hole is located in the light-transmitting area of the display panel, and is located in pixel driving circuits that are in different repeating units and adjacent in the first direction, the orthographic projection of at least part of the structure of the light-transmitting hole on the substrate is between the orthographic projections of two adjacent second extensions on the substrate, and the orthographic projection of at least part of the structure of the light-transmitting hole on the substrate is between the orthographic projection of the first gate line on the substrate and the orthographic projection of the second gate line on the substrate.
  • the first direction is the row direction
  • the second direction is the column direction
  • one power line is correspondingly arranged for each column of the pixel driving circuit
  • the orthographic projection of the power line on the substrate extends along the column direction
  • the power line comprises: a fourth extension portion, a fifth extension portion, and a sixth extension portion, and the fifth extension portion is connected between the fourth extension portion and the sixth extension portion
  • the size of the orthographic projection of the fifth extension portion on the substrate in the row direction is larger than the size of the orthographic projection of the fourth extension portion on the substrate in the row direction
  • the size of the orthographic projection of the fifth extension portion on the substrate in the row direction is larger than the size of the orthographic projection of the sixth extension portion on the substrate in the row direction
  • the fifth extension portions in two adjacent power lines are connected, and the two connected fifth extension portions form a conductive block
  • the orthographic projection of at least some of the plurality of electrode portions on the substrate overlaps with the orthographic projection of the power
  • the display panel also includes a pixel driving circuit and a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light;
  • the pixel driving circuit includes a driving transistor and a capacitor, the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode of the capacitor is connected to the power line;
  • the light-emitting unit includes a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit;
  • the capacitance of the capacitor in the pixel driving circuit corresponding to the green light-emitting unit is smaller than the capacitance of the capacitor in the pixel driving circuit corresponding to the blue light-emitting unit;
  • the capacitance of the capacitor in the pixel driving circuit corresponding to the green light-emitting unit is smaller than the capacitance of the capacitor in the pixel driving circuit corresponding to the red light-emitting unit.
  • the pixel driving circuit further includes a second transistor, and the first electrode of the second transistor is connected to the gate of the driving transistor;
  • the display panel further includes: a first gate layer and a second gate layer, the first gate layer is located between the base substrate and the first source-drain layer, the first gate layer includes a first conductive portion, the first conductive portion is used to form the first electrode of the capacitor and the gate of the driving transistor;
  • the second gate layer is located between the first gate layer and the first source-drain layer, the second gate layer includes a second conductive portion, the orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the first conductive portion on the base substrate at least partially overlap, and the second conductive portion is used to form the second electrode of the capacitor, wherein a first opening is formed on the second conductive portion;
  • the first source-drain layer further includes: a second bridge portion, the second bridge portion is connected to the first electrode of the second transistor, and the second bridge portion is connected to the first conductive portion through
  • the area of the orthographic projection of the first opening in the pixel driving circuit corresponding to the green light-emitting unit on the substrate is greater than the area of the orthographic projection of the first opening in the pixel driving circuit corresponding to the blue light-emitting unit on the substrate.
  • the display panel further includes: a light-emitting unit layer and a color filter layer, wherein the light-emitting unit layer is located on a side of the pixel definition layer away from the base substrate, and the light-emitting unit layer includes a plurality of light-emitting units; the color filter layer is located on a side of the light-emitting unit layer away from the base substrate, and the color filter layer includes a plurality of color filter portions, the color filter portions are arranged corresponding to the electrode portions, and the orthographic projection of the color filter portions on the base substrate and the orthographic projection of the corresponding electrode portions on the base substrate at least partially overlap.
  • the display panel also includes a pixel driving circuit, which includes: a driving transistor, a first transistor, the second electrode of the first transistor is connected to the gate of the driving transistor, and the first electrode of the first transistor is connected to a first initial signal line;
  • the display panel also includes: a first gate layer, a second active layer, and a second gate layer, the second gate layer is located between the first gate layer and the second active layer, the second gate layer includes the first initial signal line, and the orthographic projection of the first initial signal line on the substrate extends along a first direction;
  • the first source and drain layer also includes: a first initial connection line, the orthographic projection of the first initial connection line on the substrate extends along a second direction, and the first direction and the second direction intersect; wherein the first initial connection line is connected to the first initial signal line intersecting with its orthographic projection on the substrate through a via.
  • the display panel also includes a pixel driving circuit and a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light
  • the pixel driving circuit includes: a driving transistor, a first transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the gate of the driving transistor; the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor; the first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the fifth transistor is connected to the power line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the electrode portion, and the electrode portion is used to form the first electrode of the light-e
  • the display panel further includes: a first active layer and a first gate layer.
  • the first active layer is located between the base substrate and the first source-drain layer, and the first active layer includes: a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion; wherein the third active portion is used to form a channel region of the driving transistor, the fourth active portion is used to form a channel region of the fourth transistor, the fifth active portion is used to form a channel region of the fifth transistor, the sixth active portion is used to form a channel region of the sixth transistor, and the seventh active portion is used to form a channel region of the seventh transistor;
  • the first gate layer is located between the first active layer and the first source-drain layer, and the first gate layer includes: a second reset signal line, a second gate line, an enable signal line, and a first conductive portion, wherein the positive projections of the second reset signal line, the second gate line, and the enable signal line on the base substrate extend along
  • the display panel also includes: a second active layer and a third gate layer, the second active layer is located between the first gate layer and the first source and drain layer, the second active layer includes a first active portion and a second active portion, the first active portion is used to form a channel region of the first transistor, and the second active portion is used to form a channel region of the second transistor;
  • the third gate layer is located between the second active layer and the first source and drain layer, and the third gate layer includes: the first gate line and the first reset signal line, the orthographic projections of the first gate line and the first reset signal line on the substrate extend along the first direction; a partial structure of the first gate line is used to form a top gate of the second transistor, and a partial structure of the first reset signal line is used to form a top gate of the first transistor.
  • the third gate layer also includes the second initial signal line
  • the second gate layer also includes the first initial signal line
  • the orthographic projections of the first initial signal line and the second initial signal line on the substrate extend along the first direction
  • the orthographic projections of the first initial signal line, the first reset signal line, the second gate line, the first gate line, the first conductive portion, the enable signal line, the second initial signal line, and the second reset signal line on the substrate are sequentially distributed in the second direction, and the first direction and the second direction intersect
  • the second gate line in the pixel driving circuit of this row is multiplexed as the second reset signal line in the pixel driving circuit of the previous row
  • the orthographic projections of the first initial signal line and the first reset signal line in the pixel driving circuit of the adjacent next row on the substrate are located between the orthographic projection of the second initial signal line of the pixel driving circuit of this row on the substrate and the orthographic projection of the second reset signal line on the substrate.
  • the first transistor and the second transistor are N-type transistors
  • the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors.
  • the display panel also includes a pixel driving circuit and a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light; the electrode portion is used to form a first electrode of the light-emitting unit, and the multiple electrode portions include a first electrode portion, a second electrode portion, and a third electrode portion; among the multiple electrode portions connected to the pixel driving circuit in the same row, the second electrode portion, the first electrode portion, the third electrode portion, and the first electrode portion are alternately distributed in sequence in the row direction; in two adjacent columns of pixel driving circuits, multiple second electrode portions and multiple third electrode portions are connected to the pixel driving circuit in the same column, and the second electrode portions and the third electrode portions connected to the pixel driving circuit in the same column are alternately distributed in sequence in the column direction Y, and multiple first electrode portions are connected to the pixel driving circuit in another column, and the first electrode portions connected to the pixel driving circuit in the same column are spaced apart in the column direction.
  • the pixel driving circuit is used to drive
  • a display device comprising the above-mentioned display panel.
  • FIG1 is a schematic diagram of a circuit structure of a pixel driving circuit in the related art
  • FIG2 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG1 ;
  • FIG3 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;
  • FIG4 is a structural layout diagram of the first source-drain layer and the second source-drain layer in FIG3 ;
  • FIG5 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;
  • FIG6 is a partial cross-sectional view of the display panel shown in FIG3 along dotted line AA;
  • FIG. 7 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;
  • FIG8 is a structural diagram of the shielding layer in FIG7 ;
  • FIG9 is a structural diagram of the first active layer in FIG7 ;
  • FIG10 is a structural layout diagram of the first gate layer in FIG7 ;
  • FIG11 is a structural layout diagram of the second gate layer in FIG7 ;
  • FIG12 is a structural layout diagram of the second active layer in FIG7;
  • FIG13 is a structural layout diagram of the third gate layer in FIG7 ;
  • FIG14 is a structural layout diagram of the first source and drain layer in FIG7 ;
  • FIG15 is a structural layout diagram of the second source and drain layer in FIG7 ;
  • FIG16 is a structural diagram of the electrode layer in FIG7 ;
  • FIG17 is a structural layout diagram of the shielding layer and the first active layer in FIG7 ;
  • FIG18 is a structural layout diagram of the shielding layer, the first active layer, and the first gate layer in FIG7 ;
  • FIG19 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG7 ;
  • FIG20 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG7 ;
  • FIG21 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG7 ;
  • FIG22 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in FIG7 ;
  • FIG23 is a structural layout diagram of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in FIG7 ;
  • FIG. 24 is a partial cross-sectional view of the display panel shown in FIG. 7 taken along the dotted line BB.
  • the pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2;
  • the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the gate of the driving transistor T3 is connected to the node N;
  • the first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1;
  • the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, the gate is connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2;
  • the pixel driving circuit can be connected to a light-emitting unit OLED, which is used to drive the light-emitting unit OLED to emit light, and the light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS.
  • the first transistor T1 and the second transistor T2 can be N-type transistors, for example, the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, and the N-type transistor has a small leakage current, so that the node N can be prevented from leaking through the first transistor T1 and the second transistor T2 during the light-emitting stage.
  • the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon transistors, and the P-type low-temperature polycrystalline silicon transistor has a high carrier mobility, which is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio.
  • the first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to actual conditions.
  • FIG2 it is a timing diagram of each node in a driving method of the pixel driving circuit in FIG1.
  • G1 represents the timing of the first gate driving signal terminal G1
  • G2 represents the timing of the second gate driving signal terminal G2
  • Re1 represents the timing of the first reset signal terminal Re1
  • Re2 represents the timing of the second reset signal terminal Re
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a first reset stage t1, a data writing stage t2, a second reset stage t3, and a light emitting stage t4.
  • the first reset stage t1 the first reset signal terminal Re1 outputs a high level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N.
  • the data writing stage t2 the first gate driving signal terminal G1 outputs a high level signal, the second gate driving signal terminal G2 outputs a low level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da outputs a data signal to write a voltage Vdata+Vth (i.e., the sum of the voltage Vdata and Vth) to the node N, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3.
  • Vdata+Vth i.e., the sum of the voltage Vdata and Vth
  • the second reset signal terminal Re2 outputs a low level signal
  • the seventh transistor T7 is turned on
  • the second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6.
  • Light-emitting stage t4 the enable signal terminal EM outputs a low level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C.
  • the output current formula of the driving transistor is as follows:
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • the display panel may include a base substrate, a second source-drain layer, and an electrode layer which are stacked in sequence.
  • the data line in the display panel is generally arranged in the second source-drain layer, and the electrode portion of the light-emitting unit in the display panel is generally arranged in the electrode layer.
  • the display panel is prone to low flatness of the electrode portion due to the data line.
  • COE Color On Encapsulation, color film on the encapsulation layer
  • poor flatness of the electrode portion will directly cause optical characteristics such as color separation and color deviation of the display panel.
  • this exemplary embodiment provides a display panel, which may include a substrate, a first source and drain layer, a second source and drain layer, an electrode layer, and a pixel definition layer.
  • a display panel which may include a substrate, a first source and drain layer, a second source and drain layer, an electrode layer, and a pixel definition layer.
  • Figure 3 is a structural layout diagram of an exemplary embodiment of a display panel disclosed in the present disclosure
  • Figure 4 is a structural layout diagram of the first source and drain layer and the second source and drain layer in Figure 3.
  • the first source and drain layer is located on one side of the substrate, and the first source and drain layer includes a data line Data; the second source and drain layer is located on the side of the first source and drain layer away from the substrate, and the second source and drain layer includes a power line VDD; the electrode layer is located on the side of the second source and drain layer away from the substrate, and the electrode layer includes a plurality of electrode portions: a first electrode portion G, a second electrode portion B, and a third electrode portion R; the pixel definition layer is located on the side of the electrode layer away from the substrate, and a plurality of pixel openings PH are formed on the pixel definition layer, and the pixel openings PH are arranged corresponding to the electrode portions, and the orthographic projection of the pixel openings PH on the substrate coincides with the orthographic projection of the electrode portions on the substrate; wherein the orthographic projection of the first electrode portion G on the substrate and the orthographic projection of the data line Data on the substrate at least partially overlap.
  • the data line overlapping the first electrode portion G is disposed in the first source-drain layer away from the electrode layer, so that the flatness of the first electrode portion G can be improved.
  • the first electrode portion G can be used to form the electrode portion of the green light-emitting unit in the display panel
  • the second electrode portion B can be used to form the electrode portion of the blue light-emitting unit in the display panel
  • the third electrode portion R can be used to form the electrode portion of the red light-emitting unit.
  • the orthographic projection of the second electrode portion B on the substrate and the orthographic projection of the third electrode portion R on the substrate can be located on the orthographic projection of the power line VDD on the substrate. This arrangement can make the second electrode portion B and the third electrode portion R have good flatness.
  • the second electrode portion B, the first electrode portion G, the third electrode portion R, and the first electrode portion G are alternately distributed in sequence in the row direction X; in two adjacent columns of pixel driving circuits, the multiple second electrode portions B and the multiple third electrode portions R are connected to the same column of pixel driving circuits, and the second electrode portions B and the third electrode portions R connected to the same column of pixel driving circuits are alternately distributed in sequence in the column direction Y; the multiple first electrode portions G are connected to another column of pixel driving circuits, and the first electrode portions G connected to the same column of pixel driving circuits are spaced apart in the column direction.
  • the electrode portions may have other types and distribution methods.
  • part of the electrode portions may also be used to form the electrode portions of the white light-emitting unit, and the electrode portions may also be distributed in a Real RGB manner.
  • the orthographic projection of the electrode portion on the base substrate overlaps the orthographic projection of the data line on the base substrate in the electrode layer, the flatness of the electrode portion may be improved by arranging the data line on the first source and drain layer.
  • FIG5 it is a structural layout diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the orthographic projection of the first electrode portion G on the substrate is located on the orthographic projection of the power line VDD on the substrate, and the orthographic projections of the second electrode portion B and the third electrode portion R on the substrate overlap at least partially with the orthographic projection of the data line Data on the substrate.
  • This setting can reduce the parasitic capacitance between the second electrode portion B, the third electrode portion R and other conductive structures.
  • the data signal voltage required for the blue light-emitting unit and the red light-emitting unit at zero grayscale is lower than the data signal voltage required for the green light-emitting unit at zero grayscale.
  • This exemplary embodiment can increase the light-on speed of the red light-emitting unit and the blue light-emitting unit by reducing the parasitic capacitance of the electrode portions of the red light-emitting unit and the blue light-emitting unit, thereby increasing the data signal voltage required for the blue light-emitting unit and the red light-emitting unit at zero grayscale, that is, this setting can increase the data signal potential range (Datarange) required for the blue light-emitting unit and the red light-emitting unit in the entire grayscale range, thereby improving the data signal voltage control accuracy of the light-emitting unit at low grayscale.
  • Datarange data signal potential range
  • the first source and drain layer is located on one side of the base substrate 91, and the display panel may also include a first flat layer 911 located between the first source and drain layer and the second source and drain layer, and a second flat layer 912 located between the second source and drain layer and the electrode layer.
  • the pixel definition layer PDL is located on the side of the electrode layer away from the base substrate 91.
  • the first flat layer 911 and the second flat layer 912 can improve the flatness of the electrode part.
  • the base substrate 91 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material.
  • the first flat layer 911 may include a polyimide layer, and the structure of the second flat layer 912 may be the same as that of the first flat layer 911.
  • the materials of the first source and drain layer and the second source and drain layer may include metal materials, for example, one of molybdenum, aluminum, copper, titanium, niobium or alloys, or molybdenum/titanium alloys or laminates, etc., or may be titanium/aluminum/titanium laminates.
  • the display panel may further include a passivation layer 910 between the first source and drain layer and the first planarization layer 911 .
  • the passivation layer 910 may include a silicon oxide layer.
  • This exemplary embodiment also provides a display panel, which may include a base substrate, a blocking layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source and drain layer, a second source and drain layer, and an electrode layer stacked in sequence, wherein an insulating layer may be arranged between the above adjacent layers.
  • Figure 7 is a structural layout of an exemplary embodiment of the display panel of the present disclosure
  • Figure 8 is a structural layout of the shielding layer in Figure 7
  • Figure 9 is a structural layout of the first active layer in Figure 7
  • Figure 10 is a structural layout of the first gate layer in Figure 7
  • Figure 11 is a structural layout of the second gate layer in Figure 7
  • Figure 12 is a structural layout of the second active layer in Figure 7
  • Figure 13 is a structural layout of the third gate layer in Figure 7
  • Figure 14 is a structural layout of the first source and drain layer in Figure 7
  • Figure 15 is a structural layout of the second source and drain layer in Figure 7
  • Figure 16 is a structural layout of the electrode layer in Figure 7
  • Figure 17 is a structural layout of the shielding layer and the first active layer in Figure 7, and
  • Figure 18 is a structural layout of the shielding layer, the first active layer, and the first gate layer in Figure 7.
  • FIG. 19 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in FIG. 7,
  • FIG. 20 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in FIG. 7,
  • FIG. 21 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in FIG. 7,
  • FIG. 22 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source and drain layer in FIG. 7, and FIG.
  • the display panel may include a plurality of pixel driving circuits shown in FIG. 1. As shown in FIG. 23, the plurality of pixel driving circuits may include a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2 adjacently distributed in a first direction X, and the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may be arranged in a mirror symmetric manner.
  • the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may form a repeating unit, and the display panel may include a plurality of repeating units distributed in an array in a first direction X and a second direction Y.
  • the first direction X and the second direction Y may intersect, for example, the first direction may be a row direction, and the second direction may be a column direction.
  • the blocking layer may include a plurality of blocking parts 71, connecting parts 73 and connecting parts 72, wherein the orthographic projection of the connecting part 73 on the base substrate extends along the second direction Y and is connected between adjacent blocking parts 71 in the second direction Y; the orthographic projection of the connecting part 72 on the base substrate extends along the first direction X and is connected between adjacent blocking parts 71 in the first direction X.
  • the first active layer may include a third active portion 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, a seventh active portion 67, an eighth active portion 68, a ninth active portion 69, a tenth active portion 610, an eleventh active portion 611 and a twelfth active portion 612.
  • the third active portion 63 can be used to form the channel region of the driving transistor T3; the fourth active portion 64 can be used to form the channel region of the fourth transistor T4; the fifth active portion 65 can be used to form the channel region of the fifth transistor T5; the sixth active portion 66 can be used to form the channel region of the sixth transistor T6; the seventh active portion 67 can be used to form the channel region of the seventh transistor T7; the eighth active portion 68 is connected to the end of the seventh active portion 67 away from the sixth active portion 66; the ninth active portion 69 is connected between the seventh active portion 67 and the sixth active portion 66; the tenth active portion 610 is connected between the third active portion 63 and the sixth active portion 66; the eleventh active portion 611 is connected to the end of the fifth active portion 65 away from the third active portion 63; the twelfth active portion 612 is connected to the end of the fourth active portion 64 away from the third active portion 63.
  • the orthographic projection of the shielding portion 71 on the substrate can cover the orthographic projection of the third active portion 63 on the substrate, and the shielding portion 71 can reduce the influence of light on the characteristics of the driving transistor.
  • the first active layer can be formed of polysilicon material, and accordingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polysilicon thin film transistors.
  • the first gate layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, and a second reset signal line Re2.
  • the second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1;
  • the enable signal line EM can be used to provide the enable signal terminal in Figure 1;
  • the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1.
  • the orthographic projection of the second gate line G2 on the substrate, the orthographic projection of the enable signal line EM on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can all extend along the first direction X.
  • the orthographic projection of the second gate line G2 on the substrate covers the orthographic projection of the fourth active portion 64 on the substrate, and a partial structure of the second gate line G2 is used to form the gate of the fourth transistor.
  • the orthographic projection of the enable signal line EM on the substrate covers the orthographic projection of the fifth active portion 65 on the substrate, and the orthographic projection of the sixth active portion 66 on the substrate, and a partial structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively.
  • the orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 67 on the substrate, and a partial structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7.
  • the orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 63 on the substrate, and the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C.
  • the second gate line G2 in the pixel driving circuit of this row can be reused as the second reset signal line Re2 in the pixel driving circuit of the previous row. This setting can improve the integration of the pixel driving circuit and reduce the layout area of the pixel driving circuit.
  • the shielding layer can be connected to a stable power supply terminal.
  • the shielding layer can be connected to the first power supply terminal, the first initial signal terminal, the second initial signal terminal, etc. in FIG1, and the shielding portion 71 can stabilize the voltage of the first conductive portion 11, thereby reducing the voltage fluctuation of the gate of the driving transistor T3 during the light-emitting stage.
  • the display panel can use the first gate layer as a mask to conduct the first active layer, that is, the area covered by the first gate layer in the first active layer can form the channel region of the transistor, and the area not covered by the first gate layer forms a conductor structure.
  • the second gate layer may include: a first initial signal line Vinit1, a third reset signal line 2Re1, a third gate line 2G1, and a plurality of second conductive parts 22.
  • the first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 1
  • the third reset signal line 2Re1 can be used to provide the first reset signal terminal in Figure 1
  • the third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1.
  • the orthographic projection of the first initial signal line Vinit1 on the substrate, the orthographic projection of the third reset signal line 2Re1 on the substrate, and the orthographic projection of the third gate line 2G1 on the substrate can all extend along the first direction X.
  • the second gate layer may further include a plurality of first connection portions 211 and a plurality of second connection portions 212, wherein the first connection portion 211 is connected between two second conductive portions 22 in the same repeating unit; and the second connection portion 212 is connected between two second conductive portions 22 in adjacent repeating units.
  • the orthographic projection of the first connection portion 211 on the substrate substrate may at least partially overlap with the orthographic projection of the connection portion 72 on the substrate substrate
  • the orthographic projection of the second connection portion 212 on the substrate substrate may at least partially overlap with the orthographic projection of the connection portion 72 on the substrate substrate. This arrangement may reduce the shading effect of the first connection portion 211 and the second connection portion 212 on the display panel, and improve the transmittance of the display panel.
  • the size of the orthographic projection of the first connection portion 211 on the substrate substrate in the second direction Y may be smaller than the size of the orthographic projection of the second conductive portion 22 on the substrate substrate in the second direction Y, and the orthographic projection of the first connection portion 211 on the substrate substrate may be located on the orthographic projection of the connection portion 72 on the substrate substrate, and this arrangement may greatly improve the transmittance of the display panel.
  • the size of the orthogonal projection of the second connection portion 212 on the base substrate in the second direction Y may be greater than the size of the orthogonal projection of the first connection portion 211 on the base substrate in the second direction Y, so as to reduce the self-resistance of the conductive strip extending in the row direction formed by the second conductive portion 22. It should be understood that in other exemplary embodiments, the first connection portion 211 may not be provided between two second conductive portions 22 in the same repeating unit.
  • the second active layer may include an active portion 8, and the active portion 8 may include a first active portion 81, a second active portion 82, a thirteenth active portion 813, a fourteenth active portion 814 and a fifteenth active portion 815.
  • the first active portion 81 may be used to form a channel region of the first transistor T1; the second active portion 82 may be used to form a channel region of the second transistor T2; the thirteenth active portion 813 is connected to an end of the first active portion 81 away from the second active portion 82, the fourteenth active portion 814 is connected to an end of the second active portion 82 away from the first active portion 81, and the fifteenth active portion 815 is connected between the first active portion 81 and the second active portion 82.
  • the second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.
  • the orthographic projection of the third gate line 2G1 on the substrate can cover the orthographic projection of the second active portion 82 on the substrate, and a partial structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor.
  • the orthographic projection of the third reset signal line 2Re1 on the substrate can cover the orthographic projection of the first active portion 81 on the substrate, and a partial structure of the third reset signal line 2Re1 can be used to form the bottom gate of the first transistor T1.
  • the third gate layer may include a first reset signal line 3Re1, a first gate line 3G1 and a second initial signal line Vinit2.
  • the orthographic projection of the first reset signal line 3Re1 on the substrate, the orthographic projection of the first gate line 3G1 on the substrate and the orthographic projection of the second initial signal line Vinit2 on the substrate may all extend along the first direction X.
  • the first reset signal line 3Re1 may be used to provide the first reset signal terminal in FIG.
  • the orthographic projection of the first reset signal line 3Re1 on the substrate may cover the orthographic projection of the first active portion 81 on the substrate, and a partial structure of the first reset signal line 3Re1 may be used to form a top gate of the first transistor T1, and at the same time, the first reset signal line 3Re1 may be connected to the third reset signal line 2Re1 through a via located in the edge wiring area of the display panel.
  • the first gate line 3G1 can be used to provide the first gate drive signal terminal in FIG. 1
  • the orthographic projection of the first gate line 3G1 on the substrate can cover the orthographic projection of the second active portion 82 on the substrate, and a partial structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2.
  • the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the edge wiring area of the display panel.
  • the orthographic projection of the first conductive portion 11 on the substrate can be located between the orthographic projection of the first gate line 3G1 on the substrate and the orthographic projection of the enable signal line EM on the substrate; the orthographic projection of the first reset signal line 3Re1 on the substrate can be located on the side of the orthographic projection of the first gate line 3G1 on the substrate away from the orthographic projection of the first conductive portion 11 on the substrate.
  • the orthographic projection of the second gate line G2 on the substrate can be located between the orthographic projection of the first gate line 3G1 on the substrate and the orthographic projection of the first reset signal line 3Re1 on the substrate.
  • the orthographic projection of the second initial signal line Vinit2 on the substrate substrate is located on a side where the orthographic projection of the enable signal line EM on the substrate substrate is away from the orthographic projection of the first conductive portion 11 on the substrate substrate.
  • the orthographic projection of the second reset signal line Re2 on the substrate substrate can be located on a side where the orthographic projection of the second initial signal line Vinit2 on the substrate substrate is away from the orthographic projection of the first conductive portion 11 on the substrate substrate.
  • the orthographic projection of the first initial signal line Vinit1 on the substrate substrate is located on a side where the orthographic projection of the first reset signal line 3Re1 on the substrate substrate is away from the orthographic projection of the first conductive portion 11 on the substrate substrate.
  • the orthographic projections of the first reset signal line 3Re1 and the first initial signal line Vinit1 in the adjacent next row of pixel driving circuits on the substrate substrate are located between the orthographic projection of the second reset signal line Re2 in the pixel driving circuit of the current row on the substrate substrate and the orthographic projection of the second initial signal line Vinit2 in the pixel driving circuit of the current row on the substrate substrate.
  • the display panel can use the third gate layer as a mask to conduct the second active layer, that is, the area of the second active layer covered by the third gate layer can form the channel region of the transistor, and the area not covered by the third gate layer forms a conductor structure.
  • the first source-drain layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a data line Data, and a first initial connection line 4Vinit1.
  • the first bridge portion 41 can be connected to the eleventh active portion 611 and the second conductive portion 22 through vias (black squares in the figure) to connect the first electrode of the fifth transistor T5 and the second electrode of the capacitor C.
  • the second bridge portion 42 can be connected to the first conductive portion 11 and the fifteenth active portion 815 through vias to connect the gate of the driving transistor and the second electrode of the first transistor and the first electrode of the second transistor.
  • the third bridge portion 43 can be connected to the tenth active portion 610 and the fourteenth active portion 814 through vias to connect the second electrode of the second transistor and the second electrode of the driving transistor.
  • the fourth bridge portion 44 can be connected to the ninth active portion 69 through vias to connect the second electrode of the sixth transistor.
  • the fifth bridge portion 45 can be connected to the eighth active portion 68 and the second initial signal line Vinit2 through vias, respectively, to connect the second electrode and the second initial signal end of the seventh transistor.
  • the positive projections of the data line Data and the first initial connection line 4Vinit1 on the substrate substrate substrate can extend along the second direction Y.
  • the data line Data can be used to provide the data signal end in FIG.
  • the data line Data can be connected to the twelfth active portion 612 through a via to connect the first electrode and the data signal end of the fourth transistor.
  • the first initial connection line 4Vinit1 is connected to the sixth bridge portion 46, and the first initial connection line 4Vinit1 can be connected by vias of the sixth bridge portion and the thirteenth active portion 813 and the first initial signal line Vinit1 to connect the first initial signal end and the first electrode of the first transistor.
  • the first initial connection line 4Vinit1 and the first initial signal line Vinit1 can form a grid structure to reduce the resistance of the first initial signal line Vinit1.
  • the orthographic projection of the data line Data on the substrate can be located between the orthographic projections of two adjacent first bridge portions 41 on the substrate.
  • the data line Data can include a first extension portion da1, a second extension portion da2, and a third extension portion da3, wherein the second extension portion da2 is connected between the first extension portion da1 and the third extension portion da3; in the pixel driving circuits located in different repeating units and adjacent in the first direction X, the first extension portions da1 in two adjacent data lines are arranged relative to each other in the first direction X, the second extension portions da2 in two adjacent data lines are arranged relative to each other in the first direction X, and the third extension portions da3 in two adjacent data lines are arranged relative to each other in the first direction X.
  • the structure A and the structure B are arranged relative to each other in the first direction, which can mean that the area covered by the orthographic projection of the structure A on the substrate infinitely moving in the first direction and the area covered by the orthographic projection of the structure B on the substrate infinitely moving in the first direction overlap.
  • the distance between the orthographic projections of two adjacent second extensions Da2 on the substrate in the first direction X is greater than the distance between the orthographic projections of two adjacent first extensions Da1 on the substrate in the first direction X; the distance between the orthographic projections of two adjacent second extensions Da2 on the substrate in the first direction X is greater than the distance between the orthographic projections of two adjacent third extensions Da3 on the substrate in the first direction X.
  • the orthographic projection of at least part of the structure of the second extension Da2 on the substrate is located between the orthographic projection of the first gate line 3G1 on the substrate and the orthographic projection of the second gate line G2 on the substrate.
  • the display panel also includes a light-emitting unit layer and a color filter layer.
  • the light-emitting unit layer includes at least a light-emitting material layer.
  • the light-emitting unit layer can be located on the side of the pixel definition layer away from the base substrate.
  • the light-emitting unit layer includes a plurality of light-emitting units.
  • the color filter layer is located on the side of the light-emitting unit layer away from the base substrate.
  • the color filter layer includes a plurality of color filter portions.
  • the color filter portions are arranged corresponding to the electrode portions.
  • the orthographic projections of the color filter portions on the base substrate and the orthographic projections of the corresponding electrode portions on the base substrate at least partially overlap.
  • the display panel may also include a common electrode layer and an encapsulation layer.
  • the common electrode layer is located between the light-emitting unit layer and the color filter layer, and the encapsulation layer is located between the common electrode layer and the color filter layer.
  • the pixel definition layer can be a black pixel definition layer.
  • a light-transmitting hole PT is also formed on the pixel definition layer, and the light-transmitting hole PT is located in the light-transmitting area of the display panel, and is located in different repeating units and in the pixel driving circuits adjacent in the first direction.
  • the orthogonal projection of at least part of the structure of the light-transmitting hole PT on the substrate substrate is between the orthogonal projections of two adjacent second extensions Da2 on the substrate substrate, and the orthogonal projection of at least part of the structure of the light-transmitting hole PT on the substrate substrate is between the orthogonal projection of the first gate line 3G1 on the substrate substrate and the orthogonal projection of the second gate line G2 on the substrate substrate.
  • the light-transmitting area of the display panel can refer to the area in the display panel where no light-shielding layers such as a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source and drain layer, a second source and drain layer, and an electrode layer are set.
  • the light-transmitting hole PT can realize the light transmission of the display panel, thereby facilitating the realization of technologies such as under-screen cameras, fingerprint recognition technology, and sensing ambient light.
  • the second source-drain layer may include a power line VDD and a seventh bridge portion 57.
  • the seventh bridge portion 57 may be connected to the fourth bridge portion 44 through a via hole to connect the second electrode of the sixth transistor.
  • the positive projection of the power line VDD on the substrate may extend along the second direction Y, and the power line VDD is used to provide the first power signal terminal in Figure 1.
  • the power line VDD may be connected to the first bridge portion 41 through a via hole to connect the first power signal terminal and the first electrode of the fifth transistor and the second electrode of the capacitor.
  • the power line VDD may include a fourth extension portion VDD4, a fifth extension portion VDD5, and a sixth extension portion VDD6, wherein the fifth extension portion VDD5 is connected between the fourth extension portion VDD4 and the sixth extension portion VDD6, and the size of the positive projection of the fifth extension portion VDD5 on the substrate in the first direction X may be greater than the size of the positive projection of the fourth extension portion VDD4 on the substrate in the first direction X, and the size of the positive projection of the fifth extension portion VDD5 on the substrate in the first direction X may be greater than the size of the positive projection of the sixth extension portion VDD6 on the substrate in the first direction X.
  • the orthographic projection of the fifth extension portion VDD5 on the substrate can cover the orthographic projection of the first active portion 81 and the second active portion 82 on the substrate, and the fifth extension portion VDD5 can reduce the influence of light on the characteristics of the first transistor and the second transistor.
  • the orthographic projection of the fifth extension portion VDD5 on the substrate can also cover the orthographic projection of the second bridge portion 42 on the substrate, and the fifth extension portion VDD5 can stabilize and shield the second bridge portion 42 to reduce the voltage fluctuation of the gate of the driving transistor T3 during the light-emitting stage.
  • the fifth extension portions VDD5 in the two power lines VDD can be interconnected, so that the power lines VDD and the second conductive portion 22 can form a grid structure, and the power lines of the grid structure can reduce the voltage drop of the power signal thereon.
  • the interconnected fifth extension portions VDD5 can form a conductive block 5VDD.
  • the electrode layer includes a plurality of electrode parts: a first electrode part G, a second electrode part B, and a third electrode part R, each of which can be connected to the seventh bridge part 57 through a via hole to connect the second electrode of the sixth transistor.
  • the display panel may also include a pixel definition layer located on the side of the electrode layer away from the substrate substrate, and a plurality of pixel openings PH are formed on the pixel definition layer, and the pixel openings PH are arranged corresponding to the electrode parts, and the orthographic projection of the pixel openings PH on the substrate substrate coincides with the orthographic projection of the electrode parts on the substrate substrate; wherein the orthographic projection of the first electrode part G on the substrate substrate and the orthographic projection of the data line Data on the substrate substrate at least partially overlap.
  • the orthographic projections of the second electrode part B and the third electrode part R on the substrate substrate may be located on the orthographic projection of the power line VDD on the substrate substrate, for example, the orthographic projections of the second electrode part B and the third electrode part R on the substrate substrate may be located on the orthographic projection of the conductive block 5VDD on the substrate substrate.
  • the first electrode part G may be used to form the electrode part of the green light-emitting unit in the display panel
  • the second electrode part B may be used to form the electrode part of the blue light-emitting unit in the display panel
  • the third electrode part R may be used to form the electrode part of the red light-emitting unit.
  • the second electrode portion B, the first electrode portion G, the third electrode portion R, and the first electrode portion G are alternately distributed in the row direction X; in two adjacent columns of pixel driving circuits, the plurality of second electrode portions B and the plurality of third electrode portions R are connected to the pixel driving circuit in the same column, and the second electrode portions B and the third electrode portions R connected to the pixel driving circuit in the same column are alternately distributed in the column direction Y; the plurality of first electrode portions G are connected to the pixel driving circuit in another column, and the first electrode portions G connected to the pixel driving circuit in the same column are alternately distributed in the column direction.
  • the minimum distance S1 of the orthogonal projections of the two first electrode portions G connected to the adjacent pixel driving circuit rows and the same pixel driving circuit column on the substrate in the column direction is greater than the size S2 of the orthogonal projection of the third electrode portion R on the substrate in the column direction or the size S3 of the orthogonal projection of the second electrode portion B on the substrate in the column direction.
  • a first opening 221 is formed on the second conductive portion 22, wherein the area of the first opening 221 corresponding to the green light-emitting unit on the substrate substrate is greater than the area of the first opening 221 corresponding to the blue light-emitting unit on the substrate substrate, and the area of the first opening 221 corresponding to the green light-emitting unit on the substrate substrate is greater than the area of the first opening 221 corresponding to the red light-emitting unit on the substrate substrate.
  • This arrangement can make the capacitance of the capacitor corresponding to the green light-emitting unit smaller than the capacitance of the capacitor corresponding to the blue light-emitting unit, and the capacitance of the capacitor corresponding to the green light-emitting unit is smaller than the capacitance of the capacitor corresponding to the red light-emitting unit. Since the luminous efficiency of the green light-emitting unit is higher, the closing voltage of the driving transistor T3 corresponding to the green light-emitting unit is higher.
  • the speed of writing the data signal to the gate of the driving transistor corresponding to the green light-emitting unit in the data writing stage can be increased, thereby reducing the data signal voltage required for turning off the driving transistor corresponding to the green light-emitting unit.
  • the black squares drawn on the side of the first source and drain layer away from the substrate substrate indicate that the first source and drain layer is connected to the via holes of other layers facing the substrate substrate side; the black squares drawn on the side of the second source and drain layer away from the substrate substrate indicate that the second source and drain layer is connected to the via holes of other layers facing the substrate substrate side; the black squares drawn on the side of the electrode layer away from the substrate substrate indicate that the electrode layer is connected to the via holes of other layers facing the substrate substrate side.
  • the black squares indicate the positions of the via holes, and different via holes represented by black squares at different positions can pass through different insulating layers.
  • the display panel may also include a blocking layer 92, a first buffer layer 93, a first insulating layer 94, a second insulating layer 95, a first dielectric layer 96, a second buffer layer 97, a third insulating layer 98, a second dielectric layer 99, a passivation layer 910, a first flat layer 911, and a second flat layer 912.
  • the base substrate 91, the blocking layer, the blocking layer 92, the first buffer layer 93, the first active layer, the first insulating layer 94, the first gate layer, the second insulating layer 95, the second gate layer, the first dielectric layer 96, the second buffer layer 97, the second active layer, the third insulating layer 98, the third gate layer, the second dielectric layer 99, the first source and drain layer, the passivation layer 910, the first flat layer 911, the second source and drain layer, the second flat layer 912, the electrode layer, and the pixel definition layer PDL are stacked in sequence.
  • the barrier layer 92 may include a silicon oxide layer; the first buffer layer 93 and the second buffer layer 97 may include one or more layers of silicon oxide and silicon nitride layers; the first insulating layer 94, the second insulating layer 95 and the third insulating layer 98 may include one or more layers of silicon oxide and silicon nitride layers; the first dielectric layer 96 and the second dielectric layer 99 may include silicon nitride layers; the passivation layer 910 may include a silicon nitride layer; the materials of the first flat layer 911 and the second flat layer 912 may be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc.
  • PI polyimide
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • SOG silicon-glass bonding structure
  • the substrate 91 may include a glass substrate, a barrier layer and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material.
  • the first gate layer, the second gate layer, the third gate layer, the first source-drain layer, and the second source-drain layer are all conductive layers.
  • the materials of the first gate layer, the second gate layer, and the third gate layer may be one of molybdenum, aluminum, copper, titanium, and niobium, or an alloy thereof, or a molybdenum/titanium alloy or a laminate, etc.
  • the materials of the first source-drain layer and the second source-drain layer may include metal materials, for example, one of molybdenum, aluminum, copper, titanium, and niobium, or an alloy thereof, or a molybdenum/titanium alloy or a laminate, etc., or a titanium/aluminum/titanium laminate.
  • the electrode layer may include an indium tin oxide layer and a silver layer. The square resistance of any conductive layer in the first gate layer, the second gate layer, and the third gate layer may be greater than the square resistance of any conductive layer in the first source-drain layer and the second source-drain layer.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the figure.
  • the drawings described in the present disclosure are only structural schematic diagrams.
  • the first, second and other qualifiers are only used to define different structural names, and they do not have a specific order and quantity.
  • the positive projection of a certain structure on the substrate substrate extends in a certain direction, which can be understood as the positive projection of the structure on the substrate substrate extending straight or bending along the direction.
  • a transistor refers to an element including at least three terminals: a gate, a drain and a source.
  • the transistor has a channel region between the drain (drain electrode terminal, a drain region or a drain electrode) and the source (source electrode terminal, a source region or a source electrode), and the current can flow through the drain, the channel region and the source.
  • the channel region refers to the area where the current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate electrode may also be referred to as a control electrode.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

Landscapes

  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

提供一种显示面板及显示装置，显示面板包括：衬底基板(91)、第一源漏层、第二源漏层、电极层、像素定义层(PDL)，第一源漏层位于衬底基板(91)的一侧，第一源漏层包括数据线(Data)；第二源漏层位于第一源漏层背离衬底基板(91)的一侧，第二源漏层包括电源线(VDD)；电极层位于第二源漏层背离衬底基板(91)的一侧，电极层包括多个电极部(R、G、B)；像素定义层(PDL)位于电极层背离衬底基板(91)的一侧，像素定义层上形成有多个像素开口(PH)，像素开口(PH)与电极部(R、G、B)对应设置，像素开口(PH)在衬底基板(91)上的正投影和电极部(R、G、B)在衬底基板(91)上的正投影重合；其中，多个电极部(R、G、B)中至少部分电极部在衬底基板(91)上的正投影和数据线(Data)在衬底基板(91)上的正投影至少部分交叠。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
相关技术中，显示面板中发光单元的电极部平坦度较差。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括：衬底基板、第一源漏层、第二源漏层、电极层、像素定义层，第一源漏层位于所述衬底基板的一侧，所述第一源漏层包括数据线；第二源漏层位于所述第一源漏层背离所述衬底基板的一侧，所述第二源漏层包括电源线；电极层位于所述第二源漏层背离所述衬底基板的一侧，所述电极层包括多个电极部；像素定义层位于所述电极层背离所述衬底基板的一侧，所述像素定义层上形成有多个像素开口，所述像素开口与所述电极部对应设置，所述像素开口在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影重合；其中，多个所述电极部中至少部分所述电极部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板还包括：第一平坦层、第二平坦层，第一平坦层位于所述第一源漏层和所述第二源漏层之间；第二平坦层位于所述第二源漏层和所述电极层之间。
本公开一种示例性实施例中，所述显示面板还包括绿色发光单元；多个所述电极部中包括第一电极部，所述第一电极部用于形成所述绿色发光单元的第一电极；所述第一电极部在所述衬底基板上的正投影和所述数据 线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板还包括蓝色发光单元和红色发光单元；所述电极层还包括：第二电极部、第三电极部，第二电极部用于形成所述蓝色发光单元的第一电极，所述第二电极部在所述衬底基板上的正投影位于所述电源线在所述衬底基板上的正投影上；第三电极部用于形成所述红色发光单元的第一电极，所述第三电极部在所述衬底基板上的正投影位于所述电源线在所述衬底基板上的正投影上。
本公开一种示例性实施例中，所述显示面板还包括绿色发光单元、蓝色发光单元、红色发光单元；多个所述电极部中包括：第一电极部、第二电极部、第三电极部，第一电极部用于形成所述绿色发光单元的第一电极,所述第一电极部在所述衬底基板上的正投影位于所述电源线在所述衬底基板上的正投影上；第二电极部用于形成所述蓝色发光单元的第一电极，所述第二电极部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影至少部分交叠；第三电极部用于形成所述红色发光单元的第一电极，所述第三电极部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板包括多个重复单元，多个所述重复单元在第一方向和第二方向上阵列分布，所述第一方向和所述第二方向相交；所述重复单元包括在所述第一方向上分布的两个像素驱动电路，同一所述重复单元中两个所述像素驱动电路镜像对称设置。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管、第五晶体管，所述第五晶体管的第二极连接所述驱动晶体管的第一极；所述第一源漏层还包括：第一桥接部，所述第一桥接部连接于所述第五晶体管的第一极，且所述第一桥接部通过过孔连接所述电源线；位于不同重复单元且在所述第一方向上相邻的像素驱动电路中，所述数据线在所述衬底基板上的正投影位于两相邻所述第一桥接部在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述数据线在所述衬底基板上的正投影沿所述第二方向延伸，所述数据线包括第一延伸部、第二延伸部、第三延伸部，所述第二延伸部连接于所述第一延伸部和所述第三延伸部之间；位 于不同重复单元且在所述第一方向上相邻的像素驱动电路中，相邻两数据线中的所述第一延伸部在所述第一方向上相对设置，相邻两数据线中的所述第二延伸部在所述第一方向上相对设置，相邻两数据线中的所述第三延伸部在所述第一方向上相对设置；相邻两所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的距离大于相邻两所述第一延伸部在所述衬底基板上的正投影在所述第一方向上的距离；相邻两所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的距离大于相邻两所述第三延伸部在所述衬底基板上的正投影在所述第一方向上的距离。
本公开一种示例性实施例中，所述像素驱动电路还包括驱动晶体管、第二晶体管、第四晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极，所述第四晶体管的第一极连接所述数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；所述显示面板还包括：第一栅线、第二栅线，第一栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第一栅线的部分结构用于形成所述第二晶体管的栅极；第二栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；所述第二延伸部至少部分结构在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影和所述第二栅线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述像素定义层为黑色的像素定义层；所述像素定义层上还形成有透光孔，所述透光孔位于所述显示面板的透光区，且位于不同重复单元且在所述第一方向上相邻的像素驱动电路中，所述透光孔的至少部分结构在所述衬底基板上的正投影位相邻两所述第二延伸部在所述衬底基板上的正投影之间，所述透光孔的至少部分结构在所述衬底基板上的正投影位所述第一栅线在所述衬底基板上的正投影和所述第二栅线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述第一方向为行方向，所述第二方向为列方向，每列所述像素驱动电路对应设置一条所述电源线，所述电源线在所述衬底基板上的正投影沿列方向延伸；所述电源线包括：第四延伸部、第五延伸部、第六延伸部，所述第五延伸部连接于所述第四延伸部和所述 第六延伸部之间；所述第五延伸部在所述衬底基板上的正投影在行方向上的尺寸大于所述第四延伸部在所述衬底基板上的正投影在行方向上的尺寸，且所述第五延伸部在所述衬底基板上的正投影在行方向上的尺寸大于所述第六延伸部在所述衬底基板上的正投影在行方向上的尺寸；其中，在同一所述重复单元中，相邻两所述电源线中的第五延伸部相连接，相连接的两所述第五延伸部形成导电块；多个所述电极部中至少部分所述电极部在所述衬底基板上的正投影与所述电源线在所述衬底基板上的正投影交叠，且与所述电源线交叠的所述电极部在所述衬底基板上的正投影位于所述导电块在所述衬底基板上的正投影上。
本公开一种示例性实施例中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路用于驱动所述发光单元发光；所述像素驱动电路包括驱动晶体管、电容，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接所述电源线；所述发光单元中包括红色发光单元、绿色发光单元、蓝色发光单元；所述绿色发光单元对应像素驱动电路中的所述电容容值小于所述蓝色发光单元对应像素驱动电路中的所述电容容值；所述绿色发光单元对应像素驱动电路中的所述电容容值小于所述红色发光单元对应像素驱动电路中的所述电容容值。
本公开一种示例性实施例中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极；所述显示面板还包括：第一栅极层、第二栅极层，第一栅极层位于所述衬底基板和所述第一源漏层之间，所述第一栅极层包括第一导电部，所述第一导电部用于形成所述电容的第一电极和所述驱动晶体管的栅极；第二栅极层位于所述第一栅极层和所述第一源漏层之间，所述第二栅极层包括第二导电部，所述第二导电部在所述衬底基板上的正投影和所述第一导电部在所述衬底基板上的正投影至少部分交叠，所述第二导电部用于形成所述电容的第二电极，其中，所述第二导电部上形成有第一开口；所述第一源漏层还包括：第二桥接部，所述第二桥接部连接所述第二晶体管的第一极，且所述第二桥接部通过贯穿所述第一开口的过孔连接所述第一导电部；其中，所述绿色发光单元对应像素驱动电路中的所述第一开口在所述衬底基板上的正投影的面积大于所述红色发光单元对应像素驱动电路中的所述第一开口在所 述衬底基板上的正投影的面积；所述绿色发光单元对应像素驱动电路中的所述第一开口在所述衬底基板上的正投影的面积大于所述蓝色发光单元对应像素驱动电路中的所述第一开口在所述衬底基板上的正投影的面积。
本公开一种示例性实施例中，所述显示面板还包括：发光单元层、彩膜层，发光单元层位于所述像素定义层背离所述衬底基板的一侧，所述发光单元层包括多个发光单元；彩膜层位于所述发光单元层背离所述衬底基板的一侧，所述彩膜层包括多个彩色滤光部，所述彩色滤光部与所述电极部对应设置，所述彩色滤光部在所述衬底基板上的正投影和与其对应的所述电极部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述显示面板还包括像素驱动电路，所述像素驱动电路包括：驱动晶体管、第一晶体管，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第一晶体管的第一极连接第一初始信号线；所述显示面板还包括：第一栅极层、第二有源层、第二栅极层，第二栅极层位于所述第一栅极层和所述第二有源层之间，所述第二栅极层包括所述第一初始信号线，所述第一初始信号线在所述衬底基板上的正投影沿第一方向延伸；所述第一源漏层还包括：第一初始连接线，所述第一初始连接线在所述衬底基板上的正投影沿第二方向延伸，所述第一方向和所述第二方向相交；其中，所述第一初始连接线通过过孔连接与其在所述衬底基板上正投影相交的所述第一初始信号线。
本公开一种示例性实施例中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路用于驱动所述发光单元发光，所述像素驱动电路包括：驱动晶体管、第一晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管，第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；第四晶体管的第一极连接所述数据线，第二极连接所述驱动晶体管的第一极；第五晶体管的第一极连接所述电源线，第二极连接所述驱动晶体管的第一极；第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述电极部，所述电极部用于形成所述发光单元的第一电极；第七晶体管的第一极连接第二初始信号线，第二极连接所述电极部；电容的第一电极连接所述驱动晶体管的栅极，第二 电极连接所述电源线。
本公开一种示例性实施例中，所述显示面板还包括：第一有源层、第一栅极层。第一有源层位于所述衬底基板和所述第一源漏层之间，所述第一有源层包括：第三有源部、第四有源部、第五有源部、第六有源部、第七有源部；其中，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四有源部用于形成所述第四晶体管的沟道区，所述第五有源部用于形成所述第五晶体管的沟道区，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；第一栅极层位于所述第一有源层和所述第一源漏层之间，所述第一栅极层包括：第二复位信号线、第二栅线、使能信号线、第一导电部，所述第二复位信号线、第二栅线、使能信号线在所述衬底基板上的正投影沿第一方向延伸；其中，所述第一导电部用于形成所述驱动晶体管的栅极和所述电容的第一电极，所述第二栅线的部分结构用于形成所述第四晶体管的栅极，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极，所述使能信号线的部分结构用于分别形成所述第五晶体管和所述第六晶体管的栅极。
本公开一种示例性实施例中，所述显示面板还包括：第二有源层、第三栅极层，第二有源层位于所述第一栅极层和所述第一源漏层之间，所述第二有源层包括第一有源部和第二有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区；第三栅极层位于所述第二有源层和所述第一源漏层之间，所述第三栅极层包括：所述第一栅线、第一复位信号线，所述第一栅线、第一复位信号线在所述衬底基板上的正投影沿所述第一方向延伸；所述第一栅线的部分结构用于形成所述第二晶体管的顶栅，所述第一复位信号线的部分结构用于形成所述第一晶体管的顶栅。
本公开一种示例性实施例中，所述第三栅极层还包括所述第二初始信号线，所述第二栅极层还包括所述第一初始信号线；所述第一初始信号线、第二初始信号线在所述衬底基板上的正投影沿所述第一方向延伸；在同一像素驱动电路中，所述第一初始信号线、第一复位信号线、第二栅线、第一栅线、第一导电部、使能信号线、第二初始信号线、第二复位信号线在所述衬底基板上的正投影在第二方向上依次分布，所述第一方向和所述第 二方向相交；本行像素驱动电路中所述第二栅线复用为上一行像素驱动电路中的所述第二复位信号线；相邻下一行像素驱动电路中的所述第一初始信号线、第一复位信号线在所述衬底基板上的正投影位于本行像素驱动电路所述第二初始信号线在所述衬底基板上的正投影和所述第二复位信号线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述第一晶体管、第二晶体管为N型晶体管，所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管。
本公开一种示例性实施例中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路用于驱动所述发光单元发光；所述电极部用于形成所述发光单元的第一电极，多个所述电极部中包括第一电极部、第二电极部、第三电极部；在连接于同一行像素驱动电路的多个电极部中，第二电极部、第一电极部、第三电极部、第一电极部在行方向上依次交替分布；在相邻两列像素驱动电路中，多个第二电极部、多个第三电极部连接于同一列像素驱动电路，且连接于同一列像素驱动电路的第二电极部和第三电极部在列方向Y上依次交替分布，多个第一电极部连接于另一列像素驱动电路，连接于同一列像素驱动电路中的第一电极部在列方向上间隔分布。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中像素驱动电路的电路结构示意图；
图2为图1中像素驱动电路一种驱动方法中各节点的时序图；
图3为本公开显示面板一种示例性实施例的结构版图；
图4为图3中第一源漏层和第二源漏层的结构版图；
图5为本公开显示面板另一种示例性实施例的结构版图；
图6为图3所示显示面板沿虚线AA的部分剖视图；
图7为本公开显示面板一种示例性实施例中的结构版图；
图8为图7中遮挡层的结构版图；
图9为图7中第一有源层的结构版图；
图10为图7中第一栅极层的结构版图；
图11为图7中第二栅极层的结构版图；
图12为图7中第二有源层的结构版图；
图13为图7中第三栅极层的结构版图；
图14为图7中第一源漏层的结构版图；
图15为图7中第二源漏层的结构版图；
图16为图7中电极层的结构版图；
图17为图7中遮挡层、第一有源层的结构版图；
图18为图7中遮挡层、第一有源层、第一栅极层的结构版图；
图19为图7中遮挡层、第一有源层、第一栅极层、第二栅极层的结构版图；
图20为图7中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层的结构版图；
图21为图7中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层的结构版图；
图22为图7中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层的结构版图；
图23为图7中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层的结构版图；
图24为图7所示显示面板沿虚线BB剖开的部分剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：驱动晶体管T3、第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第四晶体管T4的第一极连接数据信号端Da，第二极连接驱动晶体管T3的第一极，栅极连接第二栅极驱动信号端G2；第五晶体管T5的第一极连接第一电源端VDD，第二极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；驱动晶体管T3的栅极连接节点N；第二晶体管T2的第一极连接节点N，第二极连接驱动晶体管T3的第二极，栅极连接第一栅极驱动信号端G1；第六晶体管T6的第一极连接驱动晶体管T3的第二极，第二极连接第七晶体管T7的第二极，栅极连接使能信号端EM，第七晶体管T7的第一极连接第二初始信号端Vinit2，栅极连接第二复位信号端Re2；第一晶体管T1的第一极连接节点N，第二极连接第一初始信号端Vinit1，栅极连接第一复位信号端Re1；电容C的第一电极连接节点N，第二电极连接第一电源端VDD。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，第一晶体管T1和第二晶体管T2可以为N型晶体管，例如，第一晶体管T1和第二晶体管T2可以为N型金属氧化物晶体管，N型晶体管具有较小的漏电流，从而可以避免发光阶段，节点N通过第一晶体管T1和第二晶体管T2漏电。同时，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型晶体管，例如，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六 晶体管T6、第七晶体管T7可以为P型低温多晶体硅晶体管，P型低温多晶体硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。第一初始信号端和第二初始信号端可以根据实际情况输出相同或不同电压信号。
如图2所示，为图1中像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示第一栅极驱动信号端G1的时序，G2表示第二栅极驱动信号端G2的时序，Re1表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括第一复位阶段t1、数据写入阶段t2，第二复位阶段t3、发光阶段t4。在第一复位阶段t1：第一复位信号端Re1输出高电平信号，第一晶体管T1导通，第一初始信号端Vinit1向节点N输入初始信号。在数据写入阶段t2：第一栅极驱动信号端G1输出高电平信号，第二栅极驱动信号端G2输出低电平信号，第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输出数据信号以向节点N写入电压Vdata+Vth(即电压Vdata与Vth之和)，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压，在第二复位阶段t3，第二复位信号端Re2输出低电平信号，第七晶体管T7导通，第二初始信号端Vinit2向第六晶体管T6的第二极输入初始信号。发光阶段t4：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。
驱动晶体管输出电流公式如下：
I＝(μWCox/2L)(Vgs-Vth) 2
其中，I为驱动晶体管输出电流；μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。
根据上述驱动晶体管输出电流公式，将本公开像素驱动电路中驱动晶体管的栅极电压Vdata+Vth和源极电压Vdd带入上述公式可以得到：本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
相关技术中，显示面板可以包括依次层叠设置的衬底基板、第二源漏层、电极层。显示面板中的数据线一般设置在第二源漏层，显示面板中发光单元的电极部一般设置在电极层。当数据线在衬底基板上的正投影和电极部在衬底基板上的正投影交叠时，该显示面板容易因为数据线而导致电极部平坦度低。尤其在COE(Color On Encapsulation，封装层上的彩膜)技术中，电极部平坦度差会直接造成显示面板色分离、色偏等光学特性。
基于此，本示例性实施例提供一种显示面板，该显示面板可以包括衬底基板、第一源漏层、第二源漏层、电极层、像素定义层。如图3、4所示，图3为本公开显示面板一种示例性实施例的结构版图，图4为图3中第一源漏层和第二源漏层的结构版图。第一源漏层位于所述衬底基板的一侧，所述第一源漏层包括数据线Data；第二源漏层位于所述第一源漏层背离所述衬底基板的一侧，所述第二源漏层包括电源线VDD；电极层位于所述第二源漏层背离所述衬底基板的一侧，所述电极层包括多个电极部：第一电极部G、第二电极部B、第三电极部R，像素定义层位于所述电极层背离所述衬底基板的一侧，所述像素定义层上形成有多个像素开口PH，所述像素开口PH与所述电极部对应设置，所述像素开口PH在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影重合；其中，第一电极部G在所述衬底基板上的正投影和所述数据线Data在所述衬底基板上的正投影至少部分交叠。
本示例性实施例将与第一电极部G有交叠的数据线设置于远离电极层的第一源漏层，从而可以提高第一电极部G的平坦度。
本示例性实施例中，第一电极部G可以用于形成显示面板中绿色发光单元的电极部，第二电极部B可以用于形成显示面板中蓝色发光单元的电极部，第三电极部R可以用于形成红色发光单元的电极部。
如图3、4所示，第二电极部B在衬底基板上的正投影和第三电极部R在衬底基板上的正投影可以位于电源线VDD在衬底基板上的正投影上。该设置可以使得第二电极部B和第三电极部R具有较好的平坦度。
本示例性实施例中，如图3、4所示，在连接于同一行像素驱动电路的多个电极部中，第二电极部B、第一电极部G、第三电极部R、第一电极部G在行方向X上依次交替分布；在相邻两列像素驱动电路中，多个第二 电极部B、多个第三电极部R连接于同一列像素驱动电路，且连接于同一列像素驱动电路的第二电极部B和第三电极部R在列方向Y上依次交替分布；多个第一电极部G连接于另一列像素驱动电路，连接于同一列像素驱动电路中的第一电极部G在列方向上间隔分布。
应该理解的是，在其他示例性实施例中，电极部还可以有其他的种类和分布方式，例如，部分电极部还可以用于形成白色发光单元的电极部，电极部还可以以Real RGB方式分布。只要电极层中存在电极部在衬底基板上的正投影和数据线在衬底基板上的正投影交叠，均可以通过将数据线设置于第一源漏层的方式提高电极部的平坦度。
如图5所示，为本公开显示面板另一种示例性实施例的结构版图。其中，与图3所示显示面板不同的是，在图5所示显示面板中，第一电极部G在衬底基板上的正投影位于电源线VDD在衬底基板上的正投影上，第二电极部B和第三电极部R在衬底基板上的正投影和数据线Data在衬底基板上的正投影至少部分交叠。该设置可以降低第二电极部B、第三电极部R与其他导电结构的之间的寄生电容。基于各种颜色发光单元的发光特性，蓝色发光单元和红色发光单元在零灰阶下所需的数据信号电压低于绿色发光单元在零灰阶下所需的数据信号电压。本示例性实施例通过降低红色发光单元和蓝色发光单元电极部的寄生电容，从而可以提高红色发光单元和蓝色发光单元的启亮速度，进而提高蓝色发光单元和红色发光单元在零灰阶下所需的数据信号电压，即该设置可以增加蓝色发光单元和红色发光单元在整个灰阶范围内所需数据信号电位范围(Datarange)，从而提高了发光单元在低灰阶下的数据信号电压控制精度。
如图6所示，为图3所示显示面板沿虚线AA的部分剖视图。其中，第一源漏层位于衬底基板91的一侧，该显示面板还可以包括位于第一源漏层和第二源漏层之间的第一平坦层911，位于第二源漏层和电极层之间的第二平坦层912，像素定义层PDL位于电极层背离衬底基板91的一侧。第一平坦层911和第二平坦层912可以提高电极部的平坦度。其中，衬底基板91可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一平坦层911可以包括聚酰亚胺层，第二平坦层912的结构可以与第一平坦层911的结构相同，第一源漏层、第二源漏层的材 料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。该显示面板还可以包括位于第一源漏层和第一平坦层911之间的钝化层910，钝化层910可以包括氧化硅层。
本示例性实施例还提供一种显示面板，该显示面板可以包括依次层叠设置的衬底基板、遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层、电极层，其中，上述相邻层级之间可以设置有绝缘层。
如图7-23所示，图7为本公开显示面板一种示例性实施例中的结构版图，图8为图7中遮挡层的结构版图，图9为图7中第一有源层的结构版图，图10为图7中第一栅极层的结构版图，图11为图7中第二栅极层的结构版图，图12为图7中第二有源层的结构版图，图13为图7中第三栅极层的结构版图，图14为图7中第一源漏层的结构版图，图15为图7中第二源漏层的结构版图，图16为图7中电极层的结构版图，图17为图7中遮挡层、第一有源层的结构版图，图18为图7中遮挡层、第一有源层、第一栅极层的结构版图，图19为图7中遮挡层、第一有源层、第一栅极层、第二栅极层的结构版图，图20为图7中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层的结构版图，图21为图7中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层的结构版图，图22为图7中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层的结构版图，图23为图7中遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层的结构版图。该显示面板可以包括多个图1所示的像素驱动电路。如图23所示，多个像素驱动电路中可以包括在第一方向X上相邻分布第一像素驱动电路Pix1和第二像素驱动电路Pix2，第一像素驱动电路Pix1和第二像素驱动电路Pix2可以镜像对称设置。其中，第一像素驱动电路Pix1和第二像素驱动电路Pix2可以形成一重复单元，该显示面板可以包括在第一方向X和第二方向Y上阵列分布的多个重复单元。其中，第一方向X和第二方向Y可以相交，例如，第一方向可以为行方向，第二方向可以为列方向。
如图7、图8、图17所示，遮挡层可以包括多个遮挡部71、连接部73、连接部72，连接部73在衬底基板上的正投影沿第二方向Y延伸，且连接于在第二方向Y上相邻的遮挡部71之间；连接部72在衬底基板上的正投影沿第一方向X延伸，且连接于在第一方向X上相邻的遮挡部71之间。
如图7、9、17、18所示，第一有源层可以包括第三有源部63、第四有源部64、第五有源部65、第六有源部66、第七有源部67、第八有源部68、第九有源部69、第十有源部610、第十一有源部611、第十二有源部612。其中，第三有源部63可以用于形成驱动晶体管T3的沟道区；第四有源部64可以用于形成第四晶体管T4的沟道区；第五有源部65可以用于形成第五晶体管T5的沟道区；第六有源部66可以用于形成第六晶体管T6的沟道区；第七有源部67可以用于形成第七晶体管T7的沟道区；第八有源部68连接于第七有源部67远离第六有源部66的一端；第九有源部69连接于第七有源部67和第六有源部66之间；第十有源部610连接于第三有源部63和第六有源部66之间；第十一有源部611连接于第五有源部65远离第三有源部63的一端；第十二有源部612连接于第四有源部64远离第三有源部63的一端。如图17所示，遮挡部71在衬底基板上的正投影可以覆盖第三有源部63在衬底基板上的正投影，遮挡部71可以降低光照对驱动晶体管特性的影响。第一有源层可以由多晶硅材料形成，相应的，驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图7、10、18所示，第一栅极层可以包括：第一导电部11、第二栅线G2、使能信号线EM、第二复位信号线Re2。第二栅线G2可以用于提供图1中第二栅极驱动信号端；使能信号线EM可以用于提供图1中的使能信号端；第二复位信号线Re2可以用于提供图1中的第二复位信号端。第二栅线G2在衬底基板上的正投影、使能信号线EM在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影均可以沿第一方向X延伸。其中，第二栅线G2在衬底基板上的正投影覆盖第四有源部64在衬底基板上的正投影，第二栅线G2的部分结构用于形成第四晶体管的栅极。使能信号线EM在衬底基板上的正投影覆盖第五有源部65在衬底基板上的正投影、 第六有源部66在衬底基板上的正投影，使能信号线EM的部分结构可以分别用于形成第五晶体管T5、第六晶体管T6的栅极。第二复位信号线Re2在衬底基板上的正投影可以覆盖第七有源部67在衬底基板上的正投影，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极。第一导电部11在衬底基板上的正投影覆盖第三有源部63在衬底基板上的正投影，第一导电部11可以用于形成驱动晶体管T3的栅极和电容C的第一电极。如图18所示，本行像素驱动电路中的第二栅线G2可以复用为上一行像素驱动电路中的第二复位信号线Re2。该设置可以提高像素驱动电路的集成度，降低像素驱动电路的布图面积。遮挡层可以连接一稳定电源端，例如，遮挡层可以连接图1中的第一电源端、第一初始信号端、第二初始信号端等，遮挡部71可以对第一导电部11起到稳压作用，从而降低驱动晶体管T3栅极在发光阶段的电压波动。此外，该显示面板可以利用第一栅极层为掩膜对第一有源层进行导体化处理，即第一有源层中被第一栅极层覆盖的区域可以形成晶体管的沟道区，未被第一栅极层覆盖的区域形成导体结构。
如图7、11、19所示，第二栅极层可以包括：第一初始信号线Vinit1、第三复位信号线2Re1、第三栅线2G1、多个第二导电部22。其中，第一初始信号线Vinit1用于提供图1中的第一初始信号端，第三复位信号线2Re1可以用于提供图1中的第一复位信号端，第三栅线2G1可以用于提供图1中的第一栅极驱动信号端。第一初始信号线Vinit1在衬底基板上的正投影、第三复位信号线2Re1在衬底基板上的正投影、第三栅线2G1在衬底基板上的正投影均可以沿第一方向X延伸。第二导电部22在衬底基板上的正投影可以和第一导电部11在衬底基板上的正投影至少部分交叠，第二导电部22可以用于形成电容C的第二电极。如图11所示，第二栅极层还可以包括多个第一连接部211和多个第二连接部212，第一连接部211连接于同一重复单元中两第二导电部22之间；第二连接部212连接于相邻重复单元中两第二导电部22之间。如图19所示，在同一组相邻的两所述像素驱动电路之间，第一连接部211在衬底基板上的正投影可以与连接部72在衬底基板上的正投影至少部分重合，第二连接部212在衬底基板上的正投影可以与连接部72在衬底基板上的正投影至少部分重合。该设 置可以降低第一连接部211、第二连接部212对显示面板的遮光影响，提高显示面板的透过率。其中，第一连接部211在衬底基板上的正投影在第二方向Y上的尺寸可以小于第二导电部22在衬底基板上的正投影在第二方向Y上的尺寸，第一连接部211在衬底基板上的正投影可以位于连接部72在衬底基板上的正投影上，该设置可以极大的提高显示面板的透过率。本示例性实施例中，第二连接部212在衬底基板上的正投影在第二方向Y上的尺寸可以大于第一连接部211在衬底基板上的正投影在第二方向Y上的尺寸，以降低第二导电部22所形成的在行方向上延伸的导电条的自身电阻。应该理解的是，在其他示例性实施例中，同一重复单元中两第二导电部22之间也可以不设置第一连接部211。
如图7、12、20所示，第二有源层可以包括有源部8，有源部8可以包括第一有源部81、第二有源部82、第十三有源部813、第十四有源部814、第十五有源部815，第一有源部81可以用于形成第一晶体管T1的沟道区；第二有源部82可以用于形成第二晶体管T2的沟道区；第十三有源部813连接于第一有源部81远离第二有源部82的一端，第十四有源部814连接于第二有源部82远离第一有源部81的一端，第十五有源部815连接于第一有源部81和第二有源部82之间。其中，第二有源层可以由氧化铟镓锌形成，相应的，第一晶体管T1、第二晶体管T2可以为N型的金属氧化物薄膜晶体管。第三栅线2G1在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第三栅线2G1的部分结构可以用于形成第二晶体管的底栅。第三复位信号线2Re1在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影，第三复位信号线2Re1的部分结构可以用于形成第一晶体管T1的底栅。
如图7、13、21所示，第三栅极层可以包括第一复位信号线3Re1、第一栅线3G1、第二初始信号线Vinit2。第一复位信号线3Re1在衬底基板上的正投影、第一栅线3G1在衬底基板上的正投影、第二初始信号线Vinit2在衬底基板上的正投影均可以沿第一方向X延伸。第一复位信号线3Re1可以用于提供图1中的第一复位信号端，第一复位信号线3Re1在衬底基板上的正投影可以覆盖第一有源部81在衬底基板上的正投影，第一复位信号线3Re1的部分结构可以用于形成第一晶体管T1的顶栅，同时， 第一复位信号线3Re1可以通过位于显示面板边沿走线区的过孔连接第三复位信号线2Re1。第一栅线3G1可以用于提供图1中的第一栅极驱动信号端，第一栅线3G1在衬底基板上的正投影可以覆盖第二有源部82在衬底基板上的正投影，第一栅线3G1的部分结构可以用于形成第二晶体管T2的顶栅，同时，第一栅线3G1可以通过位于显示面板边沿走线区的过孔连接第三栅线2G1。如图7、13、21所示，在同一像素驱动电路中，第一导电部11在所述衬底基板上的正投影可以位于所述第一栅线3G1在所述衬底基板上的正投影和所述使能信号线EM在所述衬底基板上的正投影之间；第一复位信号线3Re1在所述衬底基板上的正投影可以位于第一栅线3G1在所述衬底基板上的正投影远离所述第一导电部11在所述衬底基板上的正投影的一侧。第二栅线G2在衬底基板上的正投影可以位于第一栅线3G1在所述衬底基板上的正投影和第一复位信号线3Re1在所述衬底基板上的正投影之间。第二初始信号线Vinit2在衬底基板上的正投影位于使能信号线EM在衬底基板上的正投影远离第一导电部11在衬底基板上的正投影的一侧。第二复位信号线Re2在所述衬底基板上的正投影可以位于第二初始信号线Vinit2在衬底基板上的正投影远离所述第一导电部11在所述衬底基板上的正投影的一侧。第一初始信号线Vinit1在衬底基板上的正投影位于第一复位信号线3Re1在衬底基板上的正投影远离第一导电部11在衬底基板上的正投影的一侧。相邻下一行像素驱动电路中的第一复位信号线3Re1、第一初始信号线Vinit1在衬底基板上的正投影位于本行像素驱动电路中第二复位信号线Re2在衬底基板上的正投影和本行像素驱动电路中第二初始信号线Vinit2在衬底基板上的正投影之间。该设计可以提高像素驱动电路的集成度。此外，该显示面板可以利用第三栅极层为掩膜对第二有源层进行导体化处理，即第二有源层中被第三栅极层覆盖的区域可以形成晶体管的沟道区，未被第三栅极层覆盖的区域形成导体结构。
如图7、14、22所示，第一源漏层可以包括第一桥接部41、第二桥接部42、第三桥接部43、第四桥接部44、第五桥接部45、第六桥接部46、数据线Data、第一初始连接线4Vinit1。其中，第一桥接部41可以分别通过过孔(图中黑色方块)连接第十一有源部611、第二导电部22，以连接第五晶体管T5的第一极和电容C的第二电极。第二桥接部42可以分别 通过过孔连接第一导电部11和第十五有源部815，以连接驱动晶体管栅极和第一晶体管的第二极、第二晶体管的第一极。第三桥接部43可以分别通过过孔连接第十有源部610和第十四有源部814，以连接第二晶体管的第二极和驱动晶体管的第二极。第四桥接部44可以通过过孔连接第九有源部69，以连接第六晶体管的第二极。第五桥接部45可以分别通过过孔连接第八有源部68和第二初始信号线Vinit2，以连接第七晶体管的第二极和第二初始信号端。数据线Data、第一初始连接线4Vinit1在衬底基板上的正投影可以沿第二方向Y延伸。数据线Data可以用于提供图1中的数据信号端，数据线Data可以通过过孔连接第十二有源部612，以连接第四晶体管的第一极和数据信号端。第一初始连接线4Vinit1连接第六桥接部46，第一初始连接线4Vinit1可以利用第六桥接部和第十三有源部813、第一初始信号线Vinit1过孔连接，以连接第一初始信号端和第一晶体管的第一极。同时，第一初始连接线4Vinit1和第一初始信号线Vinit1可以形成网格结构，以降低第一初始信号线Vinit1的电阻。
如图7、14、22、23所示，位于不同重复单元且在所述第一方向X上相邻的像素驱动电路中，所述数据线Data在所述衬底基板上的正投影可以位于两相邻所述第一桥接部41在所述衬底基板上的正投影之间。数据线Data可以包括第一延伸部da1、第二延伸部da2、第三延伸部da3，所述第二延伸部da2连接于所述第一延伸部da1和所述第三延伸部da3之间；位于不同重复单元且在所述第一方向X上相邻的像素驱动电路中，相邻两数据线中的所述第一延伸部da1在所述第一方向X上相对设置，相邻两数据线中的所述第二延伸部da2在所述第一方向X上相对设置，相邻两数据线中的所述第三延伸部da3在所述第一方向X上相对设置。其中，结构A和结构B在第一方向上相对设置，可以指结构A在衬底基板上的正投影沿第一方向无限移动所覆盖区域和结构B在衬底基板上的正投影在第一方向上无限移动所覆盖区域重合。相邻两所述第二延伸部Da2在所述衬底基板上的正投影在所述第一方向X上的距离大于相邻两所述第一延伸部Da1在所述衬底基板上的正投影在所述第一方向X上的距离；相邻两所述第二延伸部Da2在所述衬底基板上的正投影在所述第一方向X上的距离大于相邻两所述第三延伸部Da3在所述衬底基板上的正投影在所述第一方向X上的 距离。本示例性实施例中，第二延伸部Da2至少部分结构在所述衬底基板上的正投影位于所述第一栅线3G1在所述衬底基板上的正投影和所述第二栅线G2在所述衬底基板上的正投影之间。
本示例性实施例中，显示面板还包括包括发光单元层、彩膜层，发光单元层至少包括发光材料层，发光单元层可以位于所述像素定义层背离所述衬底基板的一侧，所述发光单元层包括多个发光单元；彩膜层位于所述发光单元层背离所述衬底基板的一侧，所述彩膜层包括多个彩色滤光部，所述彩色滤光部与所述电极部对应设置，所述彩色滤光部在所述衬底基板上的正投影和与其对应的所述电极部在所述衬底基板上的正投影至少部分交叠。本示例性实施例利用彩膜层代替现有技术中的偏光片，从而提高了显示面板的出光率。其中，显示面板还可以包括公共电极层、封装层，公共电极层位于发光单元层和彩膜层之间，封装层位于公共电极层和彩膜层之间。
本示例性实施例中，为了提高显示面板的分辨率，像素定义层可以为黑色的像素定义层。如图7所示，所述像素定义层上还形成有透光孔PT，所述透光孔PT位于所述显示面板的透光区，且位于不同重复单元且在所述第一方向上相邻的像素驱动电路中，所述透光孔PT的至少部分结构在所述衬底基板上的正投影位相邻两所述第二延伸部Da2在所述衬底基板上的正投影之间，所述透光孔PT的至少部分结构在所述衬底基板上的正投影位所述第一栅线3G1在所述衬底基板上的正投影和所述第二栅线G2在所述衬底基板上的正投影之间。其中，显示面板的透光区可以指显示面板中没有设置遮挡层、第一有源层、第一栅极层、第二栅极层、第二有源层、第三栅极层、第一源漏层、第二源漏层、电极层等遮光层的区域。本示例性实施例中，透光孔PT可以实现显示面板透光，从而便于屏下摄像头、指纹识别技术、感测环境光等技术的实现。
如图7、15、23所示，第二源漏层可以包括电源线VDD、第七桥接部57。第七桥接部57可以通过过孔连接第四桥接部44，以连接第六晶体管的第二极。电源线VDD在衬底基板上的正投影可以沿第二方向Y延伸，电源线VDD用于提供图1中的第一电源信号端。电源线VDD可以通过过孔连接第一桥接部41，以连接第一电源信号端和第五晶体管的第一极、电容的 第二电极。电源线VDD可以包括第四延伸部VDD4、第五延伸部VDD5、第六延伸部VDD6，第五延伸部VDD5连接于第四延伸部VDD4和第六延伸部VDD6之间，第五延伸部VDD5在所述衬底基板上的正投影在第一方向X上的尺寸可以大于第四延伸部VDD4在所述衬底基板上的正投影在第一方向X上的尺寸，且所述第五延伸部VDD5在所述衬底基板上的正投影在第一方向X上的尺寸可以大于所述第六延伸部VDD6在所述衬底基板上的正投影在第一方向X上的尺寸。第五延伸部VDD5在衬底基板上的正投影可以覆盖第一有源部81、第二有源部82在衬底基板上的正投影，第五延伸部VDD5可以降低光照对第一晶体管、第二晶体管的特性影响。第五延伸部VDD5在衬底基板上的正投影还可以覆盖第二桥接部42在衬底基板上的正投影，第五延伸部VDD5可以对第二桥接部42进行稳压和屏蔽，以降低驱动晶体管T3栅极在发光阶段的电压波动。在同一重复单元中，两电源线VDD中的第五延伸部VDD5可以相互连接，从而电源线VDD和第二导电部22可以形成网格结构，该网格结构的电源线可以降低其上电源信号的压降。本示例性示实施例中，相互连接的第五延伸部VDD5可以形成导电块5VDD。
如图7、16所示，所述电极层包括多个电极部：第一电极部G、第二电极部B、第三电极部R，各个电极部可以通过过孔连接第七桥接部57，以连接第六晶体管的第二极。该显示面板还可以包括位于电极层背离衬底基板一侧的像素定义层，像素定义层上形成有多个像素开口PH，所述像素开口PH与所述电极部对应设置，所述像素开口PH在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影重合；其中，第一电极部G在所述衬底基板上的正投影和所述数据线Data在所述衬底基板上的正投影至少部分交叠。第二电极部B和第三电极部R在衬底基板上的正投影可以位于电源线VDD在衬底基板上的正投影上，例如，第二电极部B和第三电极部R在衬底基板上的正投影可以位于导电块5VDD在衬底基板上的正投影上。第一电极部G可以用于形成显示面板中绿色发光单元的电极部，第二电极部B可以用于形成显示面板中蓝色发光单元的电极部，第三电极部R可以用于形成红色发光单元的电极部。在连接于同一行像素驱动电路的多个电极部中，第二电极部B、第一电极部G、第三电极部R、第一电极部G在行方向X上依次交替分布；在相邻两列像素驱动电路中，多个第二 电极部B、多个第三电极部R连接于同一列像素驱动电路，且连接于同一列像素驱动电路的第二电极部B和第三电极部R在列方向Y上依次交替分布；多个第一电极部G连接于另一列像素驱动电路，连接于同一列像素驱动电路中的第一电极部G在列方向上间隔分布。连接于相邻像素驱动电路行且连接于同一像素驱动电路列的两个第一电极部G在所述衬底基板上的正投影在列方向上的最小距离S1大于所述第三电极部R在所述衬底基板上的正投影在列方向的尺寸S2或者所述第二电极部B所述衬底基板上的正投影在列方向的尺寸S3。
如图7、11、19所示，第二导电部22上形成有第一开口221，其中，绿色发光单元对应的第一开口221在衬底基板上的面积大于蓝色发光单元对应的第一开口221在衬底基板上的面积，绿色发光单元对应的第一开口221在衬底基板上的面积大于红色发光单元对应的第一开口221在衬底基板上的面积。该设置可以使得绿色发光单元对应电容容值小于蓝色发光单元对应电容容值，以及绿色发光单元对应电容容值小于红色发光单元对应电容容值。由于绿色发光单元的发光效率较高，绿色发光单元对应驱动晶体管T3的闭合电压较高，本示例性实施例通过降低绿色发光单元对应电容的容值可以提高绿色发光单元对应驱动晶体管栅极在数据写入阶段写入数据信号的速度，从而可以降低绿色发光单元对应驱动晶体管关断所需的数据信号电压。
需要说明的是，如图3、5、7、22、23所示，画于第一源漏层背离衬底基板一侧的黑色方块表示第一源漏层连接面向衬底基板一侧的其他层级的过孔；画于第二源漏层背离衬底基板一侧的黑色方块表示第二源漏层连接面向衬底基板一侧的其他层级的过孔；画于电极层背离衬底基板一侧的黑色方块表示电极层连接面向衬底基板一侧的其他层级的过孔。该黑色方块表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
如图24所示，为图7所示显示面板沿虚线BB剖开的部分剖视图。该显示面板还可以包括阻挡层92、第一缓冲层93、第一绝缘层94、第二绝缘层95、第一介电层96、第二缓冲层97、第三绝缘层98、第二介电层99、钝化层910、第一平坦层911、第二平坦层912。其中，衬底基板91、遮 挡层、阻挡层92、第一缓冲层93、第一有源层、第一绝缘层94、第一栅极层、第二绝缘层95、第二栅极层、第一介电层96、第二缓冲层97、第二有源层、第三绝缘层98、第三栅极层、第二介电层99、第一源漏层、钝化层910、第一平坦层911、第二源漏层、第二平坦层912、电极层、像素定义层PDL依次层叠设置。阻挡层92可以包括氧化硅层；第一缓冲层93、第二缓冲层97可以包括氧化硅、氮化硅层中的一层或多层；第一绝缘层94、第二绝缘层95、第三绝缘层98可以包括氧化硅、氮化硅层中的一层或多层；第一介电层96、第二介电层99可以包括氮化硅层；钝化层910可以包括氮化硅层；第一平坦层911、第二平坦层912的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。衬底基板91可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一栅极层、第二栅极层、第三栅极层、第一源漏层、第二源漏层均为导电层，例如，第一栅极层、第二栅极层、第三栅极层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第一源漏层、第二源漏层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。电极层可以包括氧化铟锡层、银层。第一栅极层、第二栅极层、第三栅极层中任一导电层的方块电阻可以大于第一源漏层、第二源漏层中任一导电层的方块电阻。
需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。此外，第一、第二等限定词仅用于限定不同的结构名称，其并没有特定顺序和数量的含义。在本示例性实施例中，某一结构在衬底基板上的正投影沿某一方向延伸，可以理解为该结构在衬底基板上的正投影沿该方向直线延伸或弯折延伸。晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区，并且电流能够 流过漏极、沟道区以及源极。在本示例性实施例中，沟道区是指电流主要流过的区域。在本示例性实施例中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源极”及“漏极”的功能有时互相调换。因此，在本示例性实施例中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (22)

  1. 一种显示面板，其中，所述显示面板包括：
    衬底基板；
    第一源漏层，位于所述衬底基板的一侧，所述第一源漏层包括数据线；
    第二源漏层，位于所述第一源漏层背离所述衬底基板的一侧，所述第二源漏层包括电源线；
    电极层，位于所述第二源漏层背离所述衬底基板的一侧，所述电极层包括多个电极部；
    像素定义层，位于所述电极层背离所述衬底基板的一侧，所述像素定义层上形成有多个像素开口，所述像素开口与所述电极部对应设置，所述像素开口在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影重合；
    其中，多个所述电极部中至少部分所述电极部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影至少部分交叠。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    第一平坦层，位于所述第一源漏层和所述第二源漏层之间；
    第二平坦层，位于所述第二源漏层和所述电极层之间。
  3. 根据权利要求1所述的显示面板，其中，所述显示面板还包括绿色发光单元；
    多个所述电极部中包括第一电极部，所述第一电极部用于形成所述绿色发光单元的第一电极；
    所述第一电极部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影至少部分交叠。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板还包括蓝色发光单元和红色发光单元；
    所述电极层还包括：
    第二电极部，用于形成所述蓝色发光单元的第一电极，所述第二电极部在所述衬底基板上的正投影位于所述电源线在所述衬底基板上的正投影上；
    第三电极部，用于形成所述红色发光单元的第一电极，所述第三电极 部在所述衬底基板上的正投影位于所述电源线在所述衬底基板上的正投影上。
  5. 根据权利要求1所述的显示面板，其中，所述显示面板还包括绿色发光单元、蓝色发光单元、红色发光单元；
    多个所述电极部中包括：
    第一电极部，用于形成所述绿色发光单元的第一电极,所述第一电极部在所述衬底基板上的正投影位于所述电源线在所述衬底基板上的正投影上；
    第二电极部，用于形成所述蓝色发光单元的第一电极，所述第二电极部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影至少部分交叠；
    第三电极部，用于形成所述红色发光单元的第一电极，所述第三电极部在所述衬底基板上的正投影和所述数据线在所述衬底基板上的正投影至少部分交叠。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板包括多个重复单元，多个所述重复单元在第一方向和第二方向上阵列分布，所述第一方向和所述第二方向相交；
    所述重复单元包括在所述第一方向上分布的两个像素驱动电路，同一所述重复单元中两个所述像素驱动电路镜像对称设置。
  7. 根据权利要求6所述的显示面板，其中，所述像素驱动电路包括驱动晶体管、第五晶体管，所述第五晶体管的第二极连接所述驱动晶体管的第一极；
    所述第一源漏层还包括：
    第一桥接部，所述第一桥接部连接于所述第五晶体管的第一极，且所述第一桥接部通过过孔连接所述电源线；
    位于不同重复单元且在所述第一方向上相邻的像素驱动电路中，所述数据线在所述衬底基板上的正投影位于两相邻所述第一桥接部在所述衬底基板上的正投影之间。
  8. 根据权利要求6所述的显示面板，其中，所述数据线在所述衬底基板上的正投影沿所述第二方向延伸，所述数据线包括第一延伸部、第二 延伸部、第三延伸部，所述第二延伸部连接于所述第一延伸部和所述第三延伸部之间；
    位于不同重复单元且在所述第一方向上相邻的像素驱动电路中，相邻两数据线中的所述第一延伸部在所述第一方向上相对设置，相邻两数据线中的所述第二延伸部在所述第一方向上相对设置，相邻两数据线中的所述第三延伸部在所述第一方向上相对设置；
    相邻两所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的距离大于相邻两所述第一延伸部在所述衬底基板上的正投影在所述第一方向上的距离；
    相邻两所述第二延伸部在所述衬底基板上的正投影在所述第一方向上的距离大于相邻两所述第三延伸部在所述衬底基板上的正投影在所述第一方向上的距离。
  9. 根据权利要求8所述的显示面板，其中，所述像素驱动电路还包括驱动晶体管、第二晶体管、第四晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极，所述第四晶体管的第一极连接所述数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    第一栅线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第一栅线的部分结构用于形成所述第二晶体管的栅极；
    第二栅线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第二栅线的部分结构用于形成所述第四晶体管的栅极；
    所述第二延伸部至少部分结构在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影和所述第二栅线在所述衬底基板上的正投影之间。
  10. 根据权利要求9所述的显示面板，其中，所述像素定义层为黑色的像素定义层；
    所述像素定义层上还形成有透光孔，所述透光孔位于所述显示面板的透光区，且位于不同重复单元且在所述第一方向上相邻的像素驱动电路中，所述透光孔的至少部分结构在所述衬底基板上的正投影位相邻两所述第 二延伸部在所述衬底基板上的正投影之间，所述透光孔的至少部分结构在所述衬底基板上的正投影位所述第一栅线在所述衬底基板上的正投影和所述第二栅线在所述衬底基板上的正投影之间。
  11. 根据权利要求6所述的显示面板，其中，所述第一方向为行方向，所述第二方向为列方向，每列所述像素驱动电路对应设置一条所述电源线，所述电源线在所述衬底基板上的正投影沿列方向延伸；
    所述电源线包括：第四延伸部、第五延伸部、第六延伸部，所述第五延伸部连接于所述第四延伸部和所述第六延伸部之间；
    所述第五延伸部在所述衬底基板上的正投影在行方向上的尺寸大于所述第四延伸部在所述衬底基板上的正投影在行方向上的尺寸，且所述第五延伸部在所述衬底基板上的正投影在行方向上的尺寸大于所述第六延伸部在所述衬底基板上的正投影在行方向上的尺寸；
    其中，在同一所述重复单元中，相邻两所述电源线中的第五延伸部相连接，相连接的两所述第五延伸部形成导电块；
    多个所述电极部中至少部分所述电极部在所述衬底基板上的正投影与所述电源线在所述衬底基板上的正投影交叠，且与所述电源线交叠的所述电极部在所述衬底基板上的正投影位于所述导电块在所述衬底基板上的正投影上。
  12. 根据权利要求1所述的显示面板，其中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路用于驱动所述发光单元发光；
    所述像素驱动电路包括驱动晶体管、电容，所述电容的第一电极连接所述驱动晶体管的栅极，所述电容的第二电极连接所述电源线；
    所述发光单元中包括红色发光单元、绿色发光单元、蓝色发光单元；
    所述绿色发光单元对应像素驱动电路中的所述电容容值小于所述蓝色发光单元对应像素驱动电路中的所述电容容值；
    所述绿色发光单元对应像素驱动电路中的所述电容容值小于所述红色发光单元对应像素驱动电路中的所述电容容值。
  13. 根据权利要求12所述的显示面板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极；
    所述显示面板还包括：
    第一栅极层，位于所述衬底基板和所述第一源漏层之间，所述第一栅极层包括第一导电部，所述第一导电部用于形成所述电容的第一电极和所述驱动晶体管的栅极；
    第二栅极层，位于所述第一栅极层和所述第一源漏层之间，所述第二栅极层包括第二导电部，所述第二导电部在所述衬底基板上的正投影和所述第一导电部在所述衬底基板上的正投影至少部分交叠，所述第二导电部用于形成所述电容的第二电极，其中，所述第二导电部上形成有第一开口；
    所述第一源漏层还包括：
    第二桥接部，所述第二桥接部连接所述第二晶体管的第一极，且所述第二桥接部通过贯穿所述第一开口的过孔连接所述第一导电部；
    其中，所述绿色发光单元对应像素驱动电路中的所述第一开口在所述衬底基板上的正投影的面积大于所述红色发光单元对应像素驱动电路中的所述第一开口在所述衬底基板上的正投影的面积；
    所述绿色发光单元对应像素驱动电路中的所述第一开口在所述衬底基板上的正投影的面积大于所述蓝色发光单元对应像素驱动电路中的所述第一开口在所述衬底基板上的正投影的面积。
  14. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    发光单元层，位于所述像素定义层背离所述衬底基板的一侧，所述发光单元层包括多个发光单元；
    彩膜层，位于所述发光单元层背离所述衬底基板的一侧，所述彩膜层包括多个彩色滤光部，所述彩色滤光部与所述电极部对应设置，所述彩色滤光部在所述衬底基板上的正投影和与其对应的所述电极部在所述衬底基板上的正投影至少部分交叠。
  15. 根据权利要求1所述的显示面板，其中，所述显示面板还包括像素驱动电路，所述像素驱动电路包括：驱动晶体管、第一晶体管，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第一晶体管的第一极连接第一初始信号线；
    所述显示面板还包括：
    第一栅极层；
    第二有源层；
    第二栅极层，位于所述第一栅极层和所述第二有源层之间，所述第二栅极层包括所述第一初始信号线，所述第一初始信号线在所述衬底基板上的正投影沿第一方向延伸；
    所述第一源漏层还包括：第一初始连接线，所述第一初始连接线在所述衬底基板上的正投影沿第二方向延伸，所述第一方向和所述第二方向相交；
    其中，所述第一初始连接线通过过孔连接与其在所述衬底基板上正投影相交的所述第一初始信号线。
  16. 根据权利要求1所述的显示面板，其中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路用于驱动所述发光单元发光，所述像素驱动电路包括：
    驱动晶体管；
    第一晶体管，第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；
    第二晶体管，第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；
    第四晶体管，第一极连接所述数据线，第二极连接所述驱动晶体管的第一极；
    第五晶体管，第一极连接所述电源线，第二极连接所述驱动晶体管的第一极；
    第六晶体管，第一极连接所述驱动晶体管的第二极，第二极连接所述电极部，所述电极部用于形成所述发光单元的第一电极；
    第七晶体管，第一极连接第二初始信号线，第二极连接所述电极部；
    电容，第一电极连接所述驱动晶体管的栅极，第二电极连接所述电源线。
  17. 根据权利要求16所述的显示面板，其中，所述显示面板还包括：
    第一有源层，位于所述衬底基板和所述第一源漏层之间，所述第一有源层包括：第三有源部、第四有源部、第五有源部、第六有源部、第七有源部；
    其中，所述第三有源部用于形成所述驱动晶体管的沟道区，所述第四 有源部用于形成所述第四晶体管的沟道区，所述第五有源部用于形成所述第五晶体管的沟道区，所述第六有源部用于形成所述第六晶体管的沟道区，所述第七有源部用于形成所述第七晶体管的沟道区；
    第一栅极层，位于所述第一有源层和所述第一源漏层之间，所述第一栅极层包括：第二复位信号线、第二栅线、使能信号线、第一导电部，所述第二复位信号线、第二栅线、使能信号线在所述衬底基板上的正投影沿第一方向延伸；
    其中，所述第一导电部用于形成所述驱动晶体管的栅极和所述电容的第一电极，所述第二栅线的部分结构用于形成所述第四晶体管的栅极，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极，所述使能信号线的部分结构用于分别形成所述第五晶体管和所述第六晶体管的栅极。
  18. 根据权利要求17所述的显示面板，其中，所述显示面板还包括：
    第二有源层，位于所述第一栅极层和所述第一源漏层之间，所述第二有源层包括第一有源部和第二有源部，所述第一有源部用于形成所述第一晶体管的沟道区，所述第二有源部用于形成所述第二晶体管的沟道区；
    第三栅极层，位于所述第二有源层和所述第一源漏层之间，所述第三栅极层包括：所述第一栅线、第一复位信号线，所述第一栅线、第一复位信号线在所述衬底基板上的正投影沿所述第一方向延伸；
    所述第一栅线的部分结构用于形成所述第二晶体管的顶栅，所述第一复位信号线的部分结构用于形成所述第一晶体管的顶栅。
  19. 根据权利要求18所述的显示面板，其中，所述第三栅极层还包括所述第二初始信号线，所述第二栅极层还包括所述第一初始信号线；
    所述第一初始信号线、第二初始信号线在所述衬底基板上的正投影沿所述第一方向延伸；
    在同一像素驱动电路中，所述第一初始信号线、第一复位信号线、第二栅线、第一栅线、第一导电部、使能信号线、第二初始信号线、第二复位信号线在所述衬底基板上的正投影在第二方向上依次分布，所述第一方向和所述第二方向相交；
    本行像素驱动电路中所述第二栅线复用为上一行像素驱动电路中的 所述第二复位信号线；
    相邻下一行像素驱动电路中的所述第一初始信号线、第一复位信号线在所述衬底基板上的正投影位于本行像素驱动电路所述第二初始信号线在所述衬底基板上的正投影和所述第二复位信号线在所述衬底基板上的正投影之间。
  20. 根据权利要求16所述的显示面板，其中，所述第一晶体管、第二晶体管为N型晶体管，所述驱动晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管为P型晶体管。
  21. 根据权利要求1所述的显示面板，其中，所述显示面板还包括像素驱动电路和发光单元，所述像素驱动电路用于驱动所述发光单元发光；
    所述电极部用于形成所述发光单元的第一电极，多个所述电极部中包括第一电极部、第二电极部、第三电极部；
    在连接于同一行像素驱动电路的多个电极部中，第二电极部、第一电极部、第三电极部、第一电极部在行方向上依次交替分布；
    在相邻两列像素驱动电路中，多个第二电极部、多个第三电极部连接于同一列像素驱动电路，且连接于同一列像素驱动电路的第二电极部和第三电极部在列方向上依次交替分布，多个第一电极部连接于另一列像素驱动电路，连接于同一列像素驱动电路中的第一电极部在列方向上间隔分布。
  22. 一种显示装置，其中，所述显示装置包括权利要求1-21任一项所述的显示面板。
PCT/CN2022/135049 2022-11-29 2022-11-29 显示面板及显示装置 WO2024113163A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/135049 WO2024113163A1 (zh) 2022-11-29 2022-11-29 显示面板及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/135049 WO2024113163A1 (zh) 2022-11-29 2022-11-29 显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2024113163A1 true WO2024113163A1 (zh) 2024-06-06

Family

ID=91322764

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/135049 WO2024113163A1 (zh) 2022-11-29 2022-11-29 显示面板及显示装置

Country Status (1)

Country Link
WO (1) WO2024113163A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200193917A1 (en) * 2018-12-18 2020-06-18 Samsung Display Co., Ltd. Display device
CN113327947A (zh) * 2019-11-29 2021-08-31 京东方科技集团股份有限公司 显示基板以及显示装置
CN216818344U (zh) * 2021-12-16 2022-06-24 京东方科技集团股份有限公司 显示面板和显示装置
CN114679914A (zh) * 2019-11-29 2022-06-28 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
WO2022198573A1 (zh) * 2021-03-25 2022-09-29 京东方科技集团股份有限公司 显示基板以及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200193917A1 (en) * 2018-12-18 2020-06-18 Samsung Display Co., Ltd. Display device
CN113327947A (zh) * 2019-11-29 2021-08-31 京东方科技集团股份有限公司 显示基板以及显示装置
CN114679914A (zh) * 2019-11-29 2022-06-28 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
WO2022198573A1 (zh) * 2021-03-25 2022-09-29 京东方科技集团股份有限公司 显示基板以及显示装置
CN216818344U (zh) * 2021-12-16 2022-06-24 京东方科技集团股份有限公司 显示面板和显示装置

Similar Documents

Publication Publication Date Title
WO2022193712A1 (zh) 显示面板、显示装置
WO2022057527A1 (zh) 显示基板及显示装置
KR20190107255A (ko) 표시장치
WO2022057528A1 (zh) 显示基板及显示装置
US20220352294A1 (en) Display device
US20220319422A1 (en) Display substrate and display device
WO2022160492A1 (zh) 显示基板及其制备方法、显示装置
WO2022226994A1 (zh) 显示面板和显示装置
WO2024027775A9 (zh) 显示面板及显示装置
WO2024113163A1 (zh) 显示面板及显示装置
CN114464137B (zh) 显示基板及显示装置
WO2024113370A1 (zh) 显示面板及显示装置
WO2024045037A9 (zh) 显示面板及显示装置
WO2024065591A9 (zh) 显示面板及显示装置
WO2024092496A1 (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
WO2024108389A1 (zh) 显示面板及显示装置
WO2023109232A1 (zh) 显示面板和显示装置
WO2024045059A1 (zh) 显示面板及显示装置
WO2023159602A1 (zh) 显示面板、显示装置
WO2023206157A1 (zh) 显示面板及显示装置
WO2023050273A9 (zh) 显示面板和显示装置
WO2023016335A1 (zh) 显示基板及显示装置
US20240164162A1 (en) Display panel and display apparatus
WO2024098247A1 (zh) 显示面板及其制备方法、显示装置
WO2022232988A1 (zh) 显示基板及显示装置