WO2016113865A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims abstract description 45
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Definitions
- the present invention relates to a structure and a manufacturing method of an insulated gate bipolar transistor (IGBT: “Insulated Gate Bipolar Transistor”).
- IGBT Insulated Gate Bipolar Transistor
- IGBTs are used in power modules for variable speed control of three-phase motors in the fields of general-purpose inverters and AC servos.
- IGBT there is a trade-off relationship among switching loss, on-voltage, and SOA (Safe Operating Area), but a device with low switching loss / on-voltage and wide SOA is required.
- CSTBT Carrier Stored Trench Gate Bipolar Transistor
- IEGT Insertion Enhanced Gate Transistor
- an n + type layer is provided under the p type base layer.
- the n + -type layer, n - the diffusion potential formed by the type drift layer and the n + -type layer the holes from the back side n - is accumulated in the type drift layer, it is possible to reduce the on-voltage.
- the carrier accumulation effect is enhanced, the on-voltage is lowered and the characteristics are improved, but there is a problem that the breakdown voltage is lowered.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device and a method for manufacturing the same that can improve a withstand voltage while ensuring a low on-voltage.
- a semiconductor device is formed under an n-type semiconductor substrate, a p-type base layer formed on the surface side of the n-type semiconductor substrate, and below the p-type base layer on the surface side of the n-type semiconductor substrate.
- An emitter electrode formed on the emitter layer and electrically connected thereto; a p-type collector layer formed on the back side of the n-type semiconductor substrate; a collector electrode connected to the p-type collector layer;
- On the surface side of the n-type semiconductor substrate A p-type well region formed, wherein a distance between the first trench and the second trench is narrower than a distance between the second trench and the third trench, and the n-type emitter layer is the first trench.
- the p-type well region is formed in a dummy region between the second trench and the third trench, and the n-type region is formed in the dummy region.
- the outermost surface of the semiconductor substrate is only p-type, and the p-type well region is deeper than the first, second, and third trenches.
- a p-type well region deeper than the trench is formed in the inter-trench region wider than the MOS region.
- 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the semiconductor device which concerns on Embodiment 1 of this invention. 1 is an enlarged plan view of a part of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention.
- FIG. FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1 of the present invention.
- a termination region 2 for maintaining a withstand voltage is formed on the outer periphery of the transistor region 1 of the IGBT.
- a voltage is applied between the emitter and collector of the IGBT, a depletion layer extends in the lateral direction in the termination region 2, and the electric field at the end of the transistor region 1 is relaxed.
- FIG. 2 is a sectional view showing the semiconductor device according to the first embodiment of the present invention.
- a p-type base layer 4 is formed on the surface side of the n-type semiconductor substrate 3 in the entire transistor region 1 excluding the ineffective region such as the termination region 2, and an n + -type layer 5 is formed under the p-type base layer 4. ing.
- the n + type layer 5 has a higher impurity concentration than the n type semiconductor substrate 3.
- An n + type emitter layer 6 and a p + type contact layer 7 are formed on the p type base layer 4.
- trenches 8, 9 and 10 are formed on the surface side of the n-type semiconductor substrate 3, and penetrate the p-type base layer 4 and the n + -type layer 5.
- a p-type well region 11 is formed on the surface side of the n-type semiconductor substrate 3.
- a trench gate electrode 13 is formed in the trenches 8, 9, 10 via an insulating film 12.
- An emitter electrode 14 is formed on the p-type base layer 4 and the n + -type emitter layer 6 and is electrically connected to each.
- the p-type well region 11 and the emitter electrode 14 are insulated and separated by the interlayer insulating film 15.
- An n + type buffer layer 16 and a p + type collector layer 17 are formed on the back side of the n type semiconductor substrate 3.
- a collector electrode 18 is connected to the p + -type collector layer 17.
- the distance between the trench 8 and the trench 9 is narrower than the distance between the trench 9 and the trench 10.
- the n + -type emitter layer 6 and the p + -type contact layer 7 are formed in the cell region between the narrower trench 8 and the trench 9 to form the channel of the MOS transistor.
- the p-type well region 11 is formed in a dummy region between the wider trench 9 and the trench 10. In the dummy region, the outermost surface of the n-type semiconductor substrate 3 is only p-type.
- the p-type well region 11 is deeper than the trenches 8, 9 and 10. However, they are arranged so as not to affect the characteristics of the MOS transistor formed in the narrower inter-trench region.
- FIG. 3 is an enlarged plan view of a part of the semiconductor device according to the first embodiment of the present invention.
- a plurality of p-type well regions 11 exist in regions separated from each other, and are connected to each other so as to surround the ends of the trenches 8, 9, and 10.
- 4 to 10 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
- a p-type impurity such as B is implanted into the surface of the n-type semiconductor substrate 3 by using a photoengraving technique and an implantation technique, so that the p-type well region 11 becomes a transistor region 1 and a termination region 2.
- the p-type well region 11 requires a deep diffusion depth of 5 ⁇ m or more, impurities are implanted using a MeV implanter so that a concentration peak can be formed inside the substrate with a high energy of 1 MeV or more.
- a p-type impurity such as B is implanted into the entire transistor region 1 by using a photoengraving technique and an implantation technique to form a p-type base layer 4 and an n-type impurity such as P. Is implanted to form the n + -type layer 5.
- a photoengraving technique and an implantation technique to form a p-type base layer 4 and an n-type impurity such as P.
- the p-type base layer 4 and the n + -type layer 5 by impurity implantation using the same mask.
- an n + -type emitter layer 6 is formed by selectively implanting an n-type impurity such as As.
- trenches 8, 9, and 10 penetrating the p-type base layer 4 and the n + -type layer 5 are formed on the surface side of the n-type semiconductor substrate 3 by dry etching.
- a trench gate electrode 13 is formed by burying doped polysilicon in the trenches 8, 9, 10 via the insulating film 12 by CVD or the like.
- ap type impurity such as B is implanted to selectively form ap + type contact layer 7.
- a contact pattern is formed.
- the emitter electrode 14 is selectively formed of Al or AlSi.
- the n-type semiconductor substrate 3 is ground from the back surface so as to have a desired thickness, an n + -type buffer layer 16 and a p + -type collector layer 17 are formed by implantation and activation annealing, and finally a collector electrode 18 is formed.
- FIG. 11 is a cross-sectional view showing a semiconductor device according to a comparative example.
- the p-type well region 11 does not exist.
- FIG. 12 is a diagram showing the relationship between the cell size of the IGBT and the on-voltage investigated by device simulation.
- FIG. 13 is a diagram showing the relationship between the cell size and breakdown voltage of the IGBT investigated by device simulation.
- FIG. 14 is a diagram showing an electric field distribution at the time of holding the withstand voltage of the IGBT according to the comparative example investigated by the device simulation.
- FIG. 15 is a diagram showing an electric field distribution when maintaining the breakdown voltage of the IGBT according to the first embodiment investigated by device simulation.
- the p-type well region 11 deeper than the trench is formed in the dummy region wider than the cell region.
- the presence of the p-type well region 11 as shown in FIG. 15 reduces the concentration of the electric field between the trenches as compared with the comparative example of FIG. For this reason, even if the cell size increases, the breakdown voltage can be improved while securing a low on-voltage as shown in FIGS.
- the p-type well region 11 and the emitter electrode 14 are insulated and separated by the interlayer insulating film 15 to block the passage of holes. As a result, carriers are easily accumulated in the n-type semiconductor substrate 3 in the ON state, and the ON voltage can be reduced.
- the p-type well region 11 surrounds the ends of the trenches 8, 9, and 10, the electric field at the bottom of the trenches is alleviated, so that the breakdown voltage can be improved.
- the p-type well region 11 which is a deep impurity diffusion layer first.
- the p-type well region 11 in the termination region 2 arranged so as to surround the transistor region 1 and the p-type well region 11 between the trench 9 and the trench 10 are formed by the same process. Thereby, manufacturing cost can be reduced by process reduction.
- the heat treatment time can be reduced by increasing the ion range and implanting impurities with a high energy of 1 MeV or more to form the p-type well region 11, lateral diffusion of the p-type well region 11 can be reduced. Can be reduced.
- FIG. FIG. 16 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
- the recess 19 is formed on the surface of the n-type semiconductor substrate 3 by etching.
- a p-type well region 11 is formed by implanting impurities into the formation portion of the recess 19.
- the p-type well region 11 can be formed deeply, and the breakdown voltage can be improved.
- the recess 19 is formed, the heat treatment time for obtaining a desired depth from the surface can be reduced, so that the lateral diffusion of the p-type well region 11 can be reduced. Therefore, even if there are manufacturing variations in the p-type well region 11 and the photoengraving of the trenches, it is difficult for impurities to diffuse into the narrow MOS transistor region, so that variations in the electrical characteristics of the transistors can be suppressed.
- FIG. 17 is a cross-sectional view showing a semiconductor device according to the third embodiment of the present invention.
- the n + -type emitter layer 6 is formed on both sides of the trench 8, and the emitter electrode 14 is electrically connected to the p-type base layer 4 and the n + -type emitter layer 6 on both sides of the trench 8.
- the feedback capacitance determined by the gate-collector capacitance can be reduced as compared with the first embodiment, so that the switching speed can be increased and the switching loss can be reduced.
- a dermy trench gate electrode 21 is formed in the trenches 9 and 10 via an insulating film 20 and is electrically connected to the emitter electrode 14.
- FIG. FIG. 18 is a cross-sectional view showing a semiconductor device according to Embodiment 4 of the present invention. An opening is provided in the interlayer insulating film 15, and the p-type well region 11 is electrically connected to the emitter electrode 14.
- the latch-up is a transitional situation such as when the IGBT is switched, and the npn transistor formed by the n + -type emitter layer 6, the p-type base layer 4 and the n-type semiconductor substrate 3 on the surface operates. appear. In order to prevent this operation, it is effective to reduce the hole current from the back surface flowing in the p-type base layer 4 immediately below the n + -type emitter layer 6.
- the hole current flows not to the MOS transistor side but to the p-type well region 11 side.
- the on-voltage increases, but the latch-up resistance is improved.
- the impurity concentration of the p-type well region 11 is higher than the impurity concentration of the p-type base layer 4. As a result, the hole current easily flows into the p-type well region 11 having a low resistance, so that the latch-up resistance can be further improved.
- the semiconductor substrate is not limited to being formed of silicon, but may be formed of a wide band gap semiconductor having a larger band gap than silicon.
- the wide band gap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond.
- a semiconductor device formed of such a wide band gap semiconductor has high voltage resistance and high allowable current density, and thus can be miniaturized.
- a semiconductor module incorporating this device can also be miniaturized.
- the heat resistance of the semiconductor device is high, the heat dissipating fins of the heat sink can be reduced in size, and the water cooling part can be cooled in the air, so that the semiconductor module can be further reduced in size.
- the power loss of the device is low and the efficiency is high, the efficiency of the semiconductor module can be increased.
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Abstract
Description
図1は、本発明の実施の形態1に係る半導体装置を示す平面図である。IGBTのトランジスタ領域1の外周に、耐圧を保持するための終端領域2が形成されている。IGBTのエミッタ-コレクタ間に電圧が印加された時に、終端領域2では横方向に空乏層が伸び、トランジスタ領域1の端の電界を緩和させる。
図16は、本発明の実施の形態2に係る半導体装置の製造方法を示す断面図である。本実施の形態ではn型半導体基板3の表面にエッチングにより凹部19を形成する。この凹部19の形成部分に不純物を注入することでp型ウェル領域11を形成する。
図17は、本発明の実施の形態3に係る半導体装置を示す断面図である。n+型エミッタ層6はトレンチ8の両サイドに形成され、トレンチ8の両サイドでエミッタ電極14はp型ベース層4とn+型エミッタ層6に電気的に接続されている。これにより、実施の形態1よりもゲート-コレクタ間の容量で決まる帰還容量を低減できるため、スイッチング速度が上がり、スイッチング損失を低減することができる。
図18は、本発明の実施の形態4に係る半導体装置を示す断面図である。層間絶縁膜15に開口が設けられ、p型ウェル領域11がエミッタ電極14に電気的に接続されている。
Claims (13)
- n型半導体基板と、
前記n型半導体基板の表面側に形成されたp型ベース層と、
前記n型半導体基板の表面側において前記p型ベース層の下に形成され、前記n型半導体基板より高い不純物濃度を持つn型層と、
前記p型ベース層上に形成されたn型エミッタ層と、
前記n型半導体基板の表面側に形成され、前記p型ベース層及び前記n型層を貫通する第1、第2及び第3のトレンチと、
前記第1のトレンチ内に絶縁膜を介して形成されたトレンチゲート電極と、
前記p型ベース層と前記n型エミッタ層上に形成されそれぞれと電気的に接続されたエミッタ電極と、
前記n型半導体基板の裏面側に形成されたp型コレクタ層と、
前記p型コレクタ層に接続されたコレクタ電極と、
前記n型半導体基板の表面側に形成されたp型ウェル領域とを備え、
前記第1のトレンチと前記第2のトレンチの間隔は前記第2のトレンチと前記第3のトレンチの間隔より狭く、
前記n型エミッタ層は前記第1のトレンチと前記第2のトレンチの間のセル領域に形成され、
前記p型ウェル領域は前記第2のトレンチと前記第3のトレンチの間のダミー領域に形成され、
前記ダミー領域において前記n型半導体基板の最表面はp型のみであり、
前記p型ウェル領域は前記第1、第2及び第3のトレンチよりも深さが深いことを特徴とする半導体装置。 - 前記n型半導体基板の表面に垂直な平面視において、互いに分離した領域に複数の前記p型ウェル領域が存在し、前記第1、第2及び第3のトレンチの端部を囲んで互いに接続されていることを特徴とする請求項1に記載の半導体装置。
- 前記n型エミッタ層は前記第1のトレンチの両サイドに形成され、前記第1のトレンチの両サイドで前記エミッタ電極は前記p型ベース層と前記n型エミッタ層に電気的に接続されていることを特徴とする請求項1又は2に記載の半導体装置。
- 前記第2及び第3のトレンチ内に絶縁膜を介して形成され、前記エミッタ電極と電気的に接続されたダーミートレンチゲート電極を更に備えることを特徴とする請求項1~3の何れか1項に記載の半導体装置。
- 前記p型ウェル領域と前記エミッタ電極を絶縁分離する層間絶縁膜を更に備えることを特徴とする請求項1~4の何れか1項に記載の半導体装置。
- 前記p型ウェル領域は前記エミッタ電極に電気的に接続されていることを特徴とする請求項1~4の何れか1項に記載の半導体装置。
- 前記p型ウェル領域の不純物濃度は前記p型ベース層の不純物濃度よりも高いことを特徴とする請求項6に記載の半導体装置。
- n型半導体基板の表面側にp型ベース層を形成する工程と、
前記n型半導体基板の表面側において前記p型ベース層の下に、前記n型半導体基板より高い不純物濃度を持つn型層を形成する工程と、
前記p型ベース層上にn型エミッタ層を形成する工程と、
前記n型半導体基板の表面側に、前記p型ベース層及び前記n型層を貫通する第1、第2及び第3のトレンチを形成する工程と、
前記第1のトレンチ内に絶縁膜を介してトレンチゲート電極を形成する工程と、
前記p型ベース層と前記n型エミッタ層上にそれぞれと電気的に接続されたエミッタ電極を形成する工程と、
前記n型半導体基板の裏面側にp型コレクタ層を形成する工程と、
前記p型コレクタ層に接続されたコレクタ電極を形成する工程と、
前記n型半導体基板の表面側にp型ウェル領域を形成する工程とを備え、
前記第1のトレンチと前記第2のトレンチの間隔は前記第2のトレンチと前記第3のトレンチの間隔より狭く、
前記n型エミッタ層は前記第1のトレンチと前記第2のトレンチの間のセル領域に形成され、
前記p型ウェル領域は前記第2のトレンチと前記第3のトレンチの間のダミー領域に形成され、
前記ダミー領域において前記n型半導体基板の最表面はp型のみであり、
前記p型ウェル領域は前記第1、第2及び第3のトレンチよりも深さが深いことを特徴とする半導体装置の製造方法。 - 前記n型半導体基板の表面にエッチングにより凹部を形成する工程と、
前記n型半導体基板の前記凹部の形成部分に不純物を注入することで前記p型ウェル領域を形成する工程とを備えることを特徴とする請求項8に記載の半導体装置の製造方法。 - 前記第1、第2及び第3のトレンチを形成する前に、前記p型ウェル領域、前記p型ベース層、前記n型層を順に形成することを特徴とする請求項8又は9に記載の半導体装置の製造方法。
- 前記p型ベース層と前記n型層を同一マスクを用いた不純物注入で形成することを特徴とする請求項8~10の何れか1項に記載の半導体装置の製造方法。
- トランジスタ領域を囲むように配置された終端領域のp型ウェル領域と、前記第2のトレンチと前記第3のトレンチの間の前記p型ウェル領域とを同一のプロセスで形成することを特徴とする請求項8~11の何れか1項に記載の半導体装置の製造方法。
- 1MeV以上のエネルギーで不純物を注入して前記p型ウェル領域を形成することを特徴とする請求項8~12の何れか1項に記載の半導体装置の製造方法。
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JP6996461B2 (ja) * | 2018-09-11 | 2022-01-17 | 株式会社デンソー | 半導体装置 |
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