CN107534053A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN107534053A
CN107534053A CN201580073503.4A CN201580073503A CN107534053A CN 107534053 A CN107534053 A CN 107534053A CN 201580073503 A CN201580073503 A CN 201580073503A CN 107534053 A CN107534053 A CN 107534053A
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铃木健司
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Mitsubishi Electric Corp
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Abstract

沟槽(8、9、10)形成于n型半导体衬底(3)的表面侧，将p型基极层(4)及n型层(5)贯穿。沟槽(8)和沟槽(9)的间隔比沟槽(9)和沟槽(10)的间隔狭窄。n型发射极层(6)形成于沟槽(8)与沟槽(9)之间的单元区域。p型阱区域(11)形成于沟槽(9)与沟槽(10)之间的哑区域。在哑区域，n型半导体衬底(3)的最表面仅为p型。p型阱区域(11)与沟槽(8、9、10)相比深度更深。

Description

半导体装置及其制造方法
技术领域
本发明涉及绝缘栅双极型晶体管(IGBT:Insulated Gate Bipolar Transistor)的构造及制造方法。
背景技术
从节能的观点出发，在通用逆变器以及AC伺服等领域中，在用于对三相电动机进行可变速控制的功率模块等中使用了IGBT。对于IGBT，虽然通断损耗、导通电压、SOA(SafeOperating Area)之间有折衷(trade off)关系，但要求通断损耗、导通电压低，SOA大的器件。
导通电压的大半取决于保持耐压所需的较厚的n-型漂移层的电阻，为了将该电阻降低，有效的方法是，使来自背面的空穴积蓄于n-型漂移层，激活电导率调制，使n-型漂移层的电阻降低。作为使IGBT的导通电压得到了降低的器件，存在CSTBT(Carrier StoredTrench Gate Bipolar Transistor)和IEGT(Injection Enhanced Gate Transistor)等。在专利文献1等中公开有CSTBT的例子，在专利文献2等中公开有IEGT的例子。
专利文献1：日本专利第3288218号公报
专利文献2：日本专利第2950688号公报
发明内容
就作为沟槽型IGBT之一的CSTBT而言，在p型基极层之下设置有n+型层。通过引入n+型层，从而能够通过由n-型漂移层和n+型层形成的扩散电位，使来自背面的空穴积蓄于n-型漂移层，使导通电压降低。然而，如果单元尺寸变大，则载流子积蓄效果提高，导通电压降低，特性变得良好，但存在耐压反而会降低的问题。
本发明就是为了解决上述课题而提出的，其目的在于得到一种能够确保低的导通电压并且使耐压提高的半导体装置及其制造方法。
本发明涉及的半导体装置的特征在于，具备：n型半导体衬底；p型基极层，其形成于所述n型半导体衬底的表面侧；n型层，其在所述n型半导体衬底的表面侧形成于所述p型基极层之下，具有比所述n型半导体衬底高的杂质浓度；n型发射极层，其形成于所述p型基极层之上；第1、第2及第3沟槽，它们形成于所述n型半导体衬底的表面侧，将所述p型基极层及所述n型层贯穿；沟槽栅极电极，其隔着绝缘膜而形成于所述第1沟槽内；发射极电极，其形成于所述p型基极层和所述n型发射极层之上，与它们分别电连接；p型集电极层，其形成于所述n型半导体衬底的背面侧；集电极电极，其连接于所述p型集电极层；以及p型阱区域，其形成于所述n型半导体衬底的表面侧，所述第1沟槽和所述第2沟槽的间隔比所述第2沟槽和所述第3沟槽的间隔窄，所述n型发射极层形成于所述第1沟槽与所述第2沟槽之间的单元区域，所述p型阱区域形成于所述第2沟槽与所述第3沟槽之间的哑区域，在所述哑区域，所述n型半导体衬底的最表面仅为p型，所述p型阱区域与所述第1、第2及第3沟槽相比深度更深。
发明的效果
在本发明中，在比MOS区域更大的沟槽间区域形成比沟槽更深的p型阱区域。由此，能够确保低的导通电压，并且使耐压提高。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。
图2是表示本发明的实施方式1涉及的半导体装置的剖视图。
图3是将本发明的实施方式1涉及的半导体装置的一部分放大的俯视图。
图4是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图5是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图6是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图7是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图8是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图9是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图10是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
图11是表示对比例涉及的半导体装置的剖视图。
图12是表示通过器件模拟而调查出的IGBT的单元尺寸和导通电压的关系的图。
图13是表示通过器件模拟而调查出的IGBT的单元尺寸和耐压的关系的图。
图14是表示通过器件模拟而调查出的对比例涉及的IGBT的耐压保持时的电场分布的图。
图15是表示通过器件模拟而调查出的实施方式1涉及的IGBT的耐压保持时的电场分布的图。
图16是表示本发明的实施方式2涉及的半导体装置的制造方法的剖视图。
图17是表示本发明的实施方式3涉及的半导体装置的剖视图。
图18是表示本发明的实施方式4涉及的半导体装置的剖视图。
具体实施方式
参照附图对本发明的实施方式涉及的半导体装置及其制造方法进行说明。对相同或对应的结构要素标注相同的标号，有时省略重复的说明。
实施方式1.
图1是表示本发明的实施方式1涉及的半导体装置的俯视图。在IGBT的晶体管区域1的外周，形成有用于保持耐压的末端区域2。在向IGBT的发射极-集电极间施加了电压时，在末端区域2耗尽层横向延伸，使晶体管区域1的端部的电场得到缓和。
图2是表示本发明的实施方式1涉及的半导体装置的剖视图。在除了末端区域2等无效区域以外的晶体管区域1整体，在n型半导体衬底3的表面侧形成有p型基极层4，在该p型基极层4之下形成有n+型层5。n+型层5具有比n型半导体衬底3高的杂质浓度。在p型基极层4之上形成有n+型发射极层6和p+型接触层7。在晶体管区域1处，在n型半导体衬底3的表面侧形成有沟槽8、9、10，该沟槽8、9、10将p型基极层4及n+型层5贯穿。在n型半导体衬底3的表面侧形成有p型阱区域11。
在沟槽8、9、10内隔着绝缘膜12形成有沟槽栅极电极13。发射极电极14形成于p型基极层4和n+型发射极层6之上，并分别与它们电连接。通过层间绝缘膜15对p型阱区域11和发射极电极14进行绝缘分离。在n型半导体衬底3的背面侧形成有n+型缓冲层16和p+型集电极层17。集电极电极(emitter electrode)18与p+型集电极层17连接。
沟槽8和沟槽9的间隔比沟槽9和沟槽10的间隔窄。n+型发射极层6和p+型接触层7形成于较窄的沟槽8与沟槽9之间的单元区域，形成MOS晶体管的沟道。p型阱区域11形成于较宽的沟槽9与沟槽10之间的哑(dummy)区域。在哑区域，n型半导体衬底3的最表面仅为p型。p型阱区域11与沟槽8、9、10相比深度更深。但是，是以不会影响在较窄的沟槽间区域形成的MOS晶体管的特性的方式配置的。
另外，图3是将本发明的实施方式1涉及的半导体装置的一部分放大的俯视图。在垂直于n型半导体衬底3的表面进行俯视观察时，多个p型阱区域11存在于相互分离的区域，将沟槽8、9、10的端部包围而相互连接。
下面，对本实施方式涉及的半导体装置的制造方法进行说明。图4至图10是表示本发明的实施方式1涉及的半导体装置的制造方法的剖视图。
首先，如图4所示，使用照片制版技术及注入技术，将B等p型杂质注入至n型半导体衬底3的表面，在晶体管区域1及末端区域2选择性地形成p型阱区域11。由于p型阱区域11需要大于或等于5μm的较深的扩散深度，因此使用MeV注入机以大于或等于1MeV的高能量对杂质进行注入，以能够在衬底内部形成浓度的峰值。
接下来，如图5所示，使用照片制版技术及注入技术，在晶体管区域1整体对B等p型杂质进行注入，形成p型基极层4，对P等n型杂质进行注入，形成n+型层5。为了通过工序的削减而降低制造成本，优选通过使用了同一掩模的杂质注入来形成p型基极层4和n+型层5。接下来，如图6所示，选择性地注入As等n型杂质而形成n+型发射极层6。
接下来，如图7所示，在n型半导体衬底3的表面侧，通过干蚀刻而形成将p型基极层4及n+型层5贯穿的沟槽8、9、10。在沟槽8、9、10内隔着绝缘膜12而通过CVD等埋入掺杂多晶硅，形成沟槽栅极电极13。
接下来，如图8所示，对B等p型杂质进行注入，选择性地形成p+型接触层7。接下来，如图9所示，在形成层间绝缘膜15之后，形成接触图案。接下来，如图10所示，利用Al或AlSi等选择性地形成发射极电极14。然后，从背面对n型半导体衬底3进行磨削以成为希望的厚度，通过注入及活性化退火而形成n+型缓冲层16和p+型集电极层17，最后形成集电极电极18。
接下来，与对比例进行比较而说明本实施方式的效果。图11是表示对比例涉及的半导体装置的剖视图。在对比例中不存在p型阱区域11。图12是表示了通过器件模拟而调查出的IGBT的单元尺寸和导通电压的关系的图。图13是表示通过器件模拟而调查出的IGBT的单元尺寸和耐压的关系的图。图14是表示通过器件模拟而调查出的对比例涉及的IGBT的耐压保持时的电场分布的图。图15是表示通过器件模拟而调查出的实施方式1涉及的IGBT的耐压保持时的电场分布的图。
在对比例中，如果单元尺寸变大，则载流子积蓄效果增强，导通电压降低，特性变得良好，但是，耐压反而降低。使用图14对该原因进行说明。如图14中虚线所包围的那样，在与沟槽栅极9分离的p型基极层4和n+型层5的结处，电场升高。因此，如果单元尺寸变大，则沟槽间的电场升高，耐压降低。
另一方面，在本实施方式中，在比单元区域大的哑区域形成比沟槽深的p型阱区域11。通过如图15所示具有p型阱区域11，从而与图14的对比例相比，沟槽间的电场的集中得到缓和。因此，即使单元尺寸变大，也如图12、13所示能够确保低的导通电压、且使耐压提高。
另外，通过层间绝缘膜15对p型阱区域11和发射极电极14进行绝缘分离，对空穴的释放路径进行封堵。由此，在导通状态下载流子容易在n型半导体衬底3内部积蓄，能够使导通电压降低。
另外，p型阱区域11将沟槽8、9、10的端部包围，由此端部的沟槽底处的电场得到缓和，因此能够使耐压提高。
另外，在形成沟槽8、9、10之前，依次形成p型阱区域11、p型基极层4、n+型层5。通过以该方式先形成较深的杂质扩散层即p型阱区域11，从而能够使特性稳定化。
另外，通过同一工艺形成以将晶体管区域1包围的方式配置的末端区域2的p型阱区域11、以及沟槽9与沟槽10之间的p型阱区域11。由此，能够通过工序的削减而降低制造成本。
另外，将离子的射程增大而以大于或等于1MeV的高能量对杂质进行注入，形成p型阱区域11，由此能够减少热处理时间，因此能够减少p型阱区域11的横向扩散。
实施方式2.
图16是表示本发明的实施方式2涉及的半导体装置的制造方法的剖视图。在本实施方式中，在n型半导体衬底3的表面通过蚀刻而形成凹部19。在形成该凹部19的部分对杂质进行注入，由此形成p型阱区域11。
在n型半导体衬底3的表面形成凹部19，由此能够将p型阱区域11形成得较深，能够使耐压提高。
另外，相应于凹部19的形成，能够减少用于从表面起得到希望的深度的热处理时间，因此能够减少p型阱区域11的横向扩散。因此，即使在p型阱区域11、沟槽的照片制版等中有制造波动，杂质也难以向狭窄的MOS晶体管区域扩散，因此能够对晶体管的电气特性的波动进行抑制。
实施方式3.
图17是表示本发明的实施方式3涉及的半导体装置的剖视图。n+型发射极层6形成于沟槽8的两侧，在沟槽8的两侧，发射极电极14与p型基极层4、n+型发射极层6电连接。由此，与实施方式1相比，能够降低由栅极-集电极间的电容决定的反馈电容，因此通断速度上升，能够将通断损耗降低。
在沟槽9、10内隔着绝缘膜20而形成有哑沟槽栅极电极21，该哑沟槽栅极电极21与发射极电极14电连接。通过哑沟槽栅极电极21对单元区域和保持耐压的哑区域进行分离，由此能够使晶体管的动作稳定化。
实施方式4.
图18是表示本发明的实施方式4涉及的半导体装置的剖视图。在层间绝缘膜15设置有开口，p型阱区域11与发射极电极14电连接。
在这里，在IGBT进行通断时等的过渡状态中，由表面的n+型发射极层6、p型基极层4、n型半导体衬底3形成的npn晶体管动作，从而产生了闩锁效应。为了防止该动作，将在n+型发射极层6正下方的p型基极层4流过的来自背面的空穴电流降低是有效的。
在这里，通过如本实施方式那样使p型阱区域11连接于发射极电极14，从而使得空穴电流不向MOS晶体管侧流动，而是向p型阱区域11侧流动。由此，虽然导通电压增加，但闩锁效应耐量提高。
另外，优选将p型阱区域11的杂质浓度设为比p型基极层4的杂质浓度更高。由此，空穴电流变得容易流过低电阻的p型阱区域11，因此能够进一步提高闩锁效应耐量。
此外，半导体衬底不限定于由硅形成，也可以由与硅相比带隙宽的宽带隙半导体形成。宽带隙半导体为例如碳化硅、氮化镓类材料或者金刚石。由这种宽带隙半导体形成的半导体装置的耐电压性和容许电流密度高，因此能够小型化。通过使用该小型化的半导体装置，从而组装有该装置的半导体模块也能够小型化。另外，半导体装置的耐热性高，因此能够将散热器的散热鳍片小型化，能够将水冷部空冷化，因此能够将半导体模块进一步小型化。另外，装置的电力损耗低且高效率，因此能够将半导体装置高效率化。
标号的说明
1 晶体管区域，2 末端区域，3 n型半导体衬底，4 p型基极层，5 n+型层，6 n+型发射极层，8、9、10 沟槽，11 p型阱区域，12，20 绝缘膜，13 沟槽栅极电极，14 发射极电极，15层间绝缘膜，17 p+型集电极层，18 集电极电极，19 凹部，21 哑沟槽栅极电极。

Claims (13)

1.一种半导体装置，其特征在于，具备：
n型半导体衬底；
p型基极层，其形成于所述n型半导体衬底的表面侧；
n型层，其在所述n型半导体衬底的表面侧形成于所述p型基极层之下，具有比所述n型半导体衬底高的杂质浓度；
n型发射极层，其形成于所述p型基极层之上；
第1、第2及第3沟槽，它们形成于所述n型半导体衬底的表面侧，将所述p型基极层及所述n型层贯穿；
沟槽栅极电极，其隔着绝缘膜而形成于所述第1沟槽内；
发射极电极，其形成于所述p型基极层和所述n型发射极层之上，与它们分别电连接；
p型集电极层，其形成于所述n型半导体衬底的背面侧；
集电极电极，其连接于所述p型集电极层；以及
p型阱区域，其形成于所述n型半导体衬底的表面侧，
所述第1沟槽和所述第2沟槽的间隔比所述第2沟槽和所述第3沟槽的间隔窄，
所述n型发射极层形成于所述第1沟槽与所述第2沟槽之间的单元区域，
所述p型阱区域形成于所述第2沟槽与所述第3沟槽之间的哑区域，
在所述哑区域，所述n型半导体衬底的最表面仅为p型，
所述p型阱区域与所述第1、第2及第3沟槽相比深度更深。
2.根据权利要求1所述的半导体装置，其特征在于，
在垂直于所述n型半导体衬底的表面而进行俯视观察时，多个所述p型阱区域存在于相互分离的区域，将所述第1、第2及第3沟槽的端部包围而相互连接。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述n型发射极层形成于所述第1沟槽的两侧，在所述第1沟槽的两侧，所述发射极电极与所述p型基极层和所述n型发射极层电连接。
4.根据权利要求1至3中任一项所述的半导体装置，其特征在于，
还具备哑沟槽栅极电极，该哑沟槽栅极电极隔着绝缘膜而形成在所述第2及第3沟槽内，与所述发射极电极电连接。
5.根据权利要求1至4中任一项所述的半导体装置，其特征在于，
还具备层间绝缘膜，该层间绝缘膜对所述p型阱区域和所述发射极电极进行绝缘分离。
6.根据权利要求1至4中任一项所述的半导体装置，其特征在于，
所述p型阱区域与所述发射极电极电连接。
7.根据权利要求6所述的半导体装置，其特征在于，
所述p型阱区域的杂质浓度比所述p型基极层的杂质浓度高。
8.一种半导体装置的制造方法，其特征在于，具备下述工序：
在n型半导体衬底的表面侧形成p型基极层；
在所述n型半导体衬底的表面侧，在所述p型基极层之下形成n型层，该n型层与所述n型半导体衬底相比具有更高的杂质浓度；
在所述p型基极层之上形成n型发射极层；
在所述n型半导体衬底的表面侧形成将所述p型基极层及所述n型层贯穿的第1、第2及第3沟槽；
在所述第1沟槽内隔着绝缘膜而形成沟槽栅极电极；
在所述p型基极层和所述n型发射极层之上形成与它们分别电连接的发射极电极；
在所述n型半导体衬底的背面侧形成p型集电极层；
形成与所述p型集电极层连接的集电极电极；以及
在所述n型半导体衬底的表面侧形成p型阱区域，
所述第1沟槽和所述第2沟槽的间隔比所述第2沟槽和所述第3沟槽的间隔窄，
所述n型发射极层形成于所述第1沟槽与所述第2沟槽之间的单元区域，
所述p型阱区域形成于所述第2沟槽与所述第3沟槽之间的哑区域，
在所述哑区域，所述n型半导体衬底的最表面仅为p型，
所述p型阱区域与所述第1、第2及第3沟槽相比深度更深。
9.根据权利要求8所述的半导体装置的制造方法，其特征在于，具备下述工序：
在所述n型半导体衬底的表面通过蚀刻而形成凹部；以及
通过对所述n型半导体衬底的形成所述凹部的部分注入杂质而形成所述p型阱区域。
10.根据权利要求8或9所述的半导体装置的制造方法，其特征在于，
在形成所述第1、第2及第3沟槽之前，依次形成所述p型阱区域、所述p型基极层、所述n型层。
11.根据权利要求8至10中任一项所述的半导体装置的制造方法，其特征在于，
通过使用了同一掩模的杂质注入来形成所述p型基极层和所述n型层。
12.根据权利要求8至11中任一项所述的半导体装置的制造方法，其特征在于，
通过同一工艺形成以将晶体管区域包围的方式配置的末端区域的p型阱区域、以及所述第2沟槽与所述第3沟槽之间的所述p型阱区域。
13.根据权利要求8至12中任一项所述的半导体装置的制造方法，其特征在于，
以大于或等于1MeV的能量对杂质进行注入而形成所述p型阱区域。
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CN110265300B (zh) * 2019-06-18 2022-11-08 龙腾半导体股份有限公司 增强微元胞结构igbt短路能力的方法
CN117637831A (zh) * 2023-11-20 2024-03-01 海信家电集团股份有限公司 半导体装置和半导体装置的制造方法

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