WO2012140934A1 - 高周波パッケージ - Google Patents
高周波パッケージ Download PDFInfo
- Publication number
- WO2012140934A1 WO2012140934A1 PCT/JP2012/052117 JP2012052117W WO2012140934A1 WO 2012140934 A1 WO2012140934 A1 WO 2012140934A1 JP 2012052117 W JP2012052117 W JP 2012052117W WO 2012140934 A1 WO2012140934 A1 WO 2012140934A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- dielectric substrate
- high frequency
- dielectric
- conductor
- ground conductor
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0007—Casings
- H05K9/006—Casings specially adapted for signal processing applications, e.g. CATV, tuner, antennas amplifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention relates to high frequency packages.
- the configuration of the conventional high frequency package is mounted on the first dielectric substrate having the signal wiring and the ground conductor on the back surface and the back surface of the first dielectric substrate.
- a high frequency element, a second dielectric substrate having a signal wiring and a ground conductor on the surface surface layer, and a connecting conductor, the high frequency element is mounted on the back surface layer of the first dielectric substrate, and the high frequency element is a first
- a connection conductor is connected between the ground conductors of the first and second dielectric substrates so as to surround the high frequency element, which is configured to be sandwiched between the back surface of the dielectric substrate and the surface of the second dielectric substrate. It has a shielded space.
- the present invention has been made in view of the above, and it is an object of the present invention to obtain a high frequency package in which isolation between terminals is improved.
- the present invention provides a first dielectric substrate provided with a signal wiring and a ground conductor on the back surface, and a first connection conductor on the back surface of the first dielectric substrate. And a second dielectric substrate provided with a signal wiring and a ground conductor on the surface facing the back surface and the high frequency element, and arranged to surround the high frequency element; A plurality of second connection conductors for connecting the ground conductor on the back surface of the dielectric substrate to the ground conductor on the surface of the second dielectric substrate, and the lower portion of the high frequency element on the surface of the second dielectric substrate And a dielectric space surrounded by the conductor pattern.
- FIG. 1 is a diagram showing a circuit configuration of a high frequency package according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing a circuit configuration of a high frequency package according to a second embodiment of the present invention.
- FIG. 3A is a diagram showing calculation results of isolation between terminals when there is no dielectric space.
- FIG. 3B is a diagram of calculation results of isolation between terminals when there is a dielectric space according to the first embodiment of the present invention.
- FIG. 1 is a diagram showing a circuit configuration of a high frequency package 100 according to a first embodiment of the present invention.
- the high frequency package 100 includes a first dielectric substrate 10 having a signal wiring and a ground conductor on the back surface, a high frequency element 20 mounted on the first dielectric substrate 10 through the connection conductor 40, and a signal wiring on the surface surface.
- a solder ball 41 which is a connection conductor connecting between the ground conductors 30 of the dielectric substrate 11, is provided.
- the high frequency device 20 is mounted on the first dielectric substrate 10 via the connection conductor 40.
- the high frequency device 20 is surrounded by the first dielectric substrate 10 and the second dielectric substrate 11 so that the solder balls 41 surround the high frequency device 20.
- the ground conductor 30 of the dielectric substrate 11 is connected to each other and has a shielding space.
- a dielectric space 60 configured by being surrounded by the via 50 which is a conductor and the inner layer pattern 51 is formed. For this reason, the effective dielectric constant in the shielding space is increased by the dielectric constant of the dielectric space 60, and the cavity resonant frequency is shifted to a lower frequency to improve the isolation between the terminals.
- FIG. 3A shows the calculation result of isolation between terminals when there is no dielectric space
- FIG. 3B shows the calculation result of isolation between terminals when there is a dielectric space.
- FIG. 2 is a diagram showing a circuit configuration of the high frequency package 200 according to the second embodiment of the present invention.
- the high frequency package 200 includes a first dielectric substrate 10 having a signal wiring and a ground conductor on the back surface, a high frequency element 20 mounted on the first dielectric substrate 10 through the connection conductor 40, and a signal wiring on the surface surface.
- a second dielectric substrate 11, a first dielectric substrate 10 and a second dielectric substrate 11 having a ground conductor 30 and having a cavity 50 surrounded by a via 50 made of a conductor and an inner layer pattern 51.
- the solder ball 41 which is a connection conductor which connects between the ground conductors 30 of these is provided.
- the high frequency device 20 is mounted on the first dielectric substrate 10 via the connection conductor 40.
- the high frequency device 20 is surrounded by the first dielectric substrate 10 and the second dielectric substrate 11 so that the solder balls 41 surround the high frequency device 20.
- the ground conductor 30 of the dielectric substrate 11 is connected to each other and has a shielding space.
- a cavity space 70 surrounded by the via 50 which is a conductor and the inner layer pattern 51 is formed.
- the effective dielectric constant in the shielding space is reduced by the dielectric constant of the cavity space 70, and the cavity resonant frequency shifts to a high frequency, whereby the isolation between the terminals is improved.
- the present invention is not limited to the above embodiment, and can be variously modified without departing from the scope of the invention at the implementation stage.
- the above embodiments include inventions of various stages, and various inventions can be extracted by appropriate combinations of a plurality of disclosed configuration requirements.
- the high frequency package according to the present invention is useful for isolation between terminals, and is particularly suitable when the high frequency element is an active element.
- first dielectric substrate 11 second dielectric substrate 20 high frequency element 30 ground conductor 40 connection conductor 41 solder ball 50 via 51 inner layer pattern 60 dielectric space 70 cavity space 100, 200 high frequency package
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Signal Processing (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Waveguides (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
図1は、本発明の実施の形態1にかかる高周波パッケージ100の回路構成を示す図である。高周波パッケージ100は、裏面表層に信号配線と接地導体を有する第1の誘電体基板10、接続導体40を介して第1の誘電体基板10に実装された高周波素子20、表面表層に信号配線と接地導体30を有し、導体からなるビア50および内層パターン51で周りを囲まれて構成された誘電体空間60を有する第2の誘電体基板11、第1の誘電体基板10および第2の誘電体基板11の接地導体30間を接続する接続導体であるはんだボール41を備える。
図2は、本発明の実施の形態2にかかる高周波パッケージ200の回路構成を示す図である。高周波パッケージ200は、裏面表層に信号配線と接地導体を有する第1の誘電体基板10、接続導体40を介して第1の誘電体基板10に実装された高周波素子20、表面表層に信号配線と接地導体30を有し、導体からなるビア50および内層パターン51で周りを囲まれたキャビティ空間70を有する第2の誘電体基板11、第1の誘電体基板10および第2の誘電体基板11の接地導体30間を接続する接続導体であるはんだボール41を備える。
11 第2の誘電体基板
20 高周波素子
30 接地導体
40 接続導体
41 はんだボール
50 ビア
51 内層パターン
60 誘電体空間
70 キャビティ空間
100、200 高周波パッケージ
Claims (2)
- 裏面に信号配線と接地導体を設けた第1の誘電体基板と、
第1の誘電体基板の裏面に第1接続導体を介して接続された高周波素子と、
前記裏面と前記高周波素子を挟み込んで対向する表面に信号配線と接地導体を設けた第2の誘電体基板と、
前記高周波素子を囲むように配置され、第1の誘電体基板の裏面の接地導体と第2の誘電体基板の表面の接地導体とを接続する複数の第2接続導体と、
を備え、
前記第2の誘電体基板の表面の高周波素子の下部に、導体パターンで囲まれた誘電体空間が形成されている
ことを特徴とする高周波パッケージ。 - 前記導体パターンで囲まれた誘電体空間は、前記第2の誘電体基板を構成する誘電体が存在しないキャビティ空間
であることを特徴とする請求項1に記載の高周波パッケージ。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013509810A JP5693710B2 (ja) | 2011-04-14 | 2012-01-31 | 高周波パッケージ |
US14/111,107 US9693492B2 (en) | 2011-04-14 | 2012-01-31 | High-frequency package |
EP12771789.0A EP2698819B1 (en) | 2011-04-14 | 2012-01-31 | High-frequency package |
CN201280017668.6A CN103460377B (zh) | 2011-04-14 | 2012-01-31 | 高频封装 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011-090259 | 2011-04-14 | ||
JP2011090259 | 2011-04-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012140934A1 true WO2012140934A1 (ja) | 2012-10-18 |
Family
ID=47009120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2012/052117 WO2012140934A1 (ja) | 2011-04-14 | 2012-01-31 | 高周波パッケージ |
Country Status (5)
Country | Link |
---|---|
US (1) | US9693492B2 (ja) |
EP (1) | EP2698819B1 (ja) |
JP (1) | JP5693710B2 (ja) |
CN (1) | CN103460377B (ja) |
WO (1) | WO2012140934A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015173140A (ja) * | 2014-03-11 | 2015-10-01 | 三菱電機株式会社 | 高周波パッケージ |
WO2024084556A1 (ja) * | 2022-10-18 | 2024-04-25 | 三菱電機株式会社 | 高周波半導体パッケージ |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3598484B1 (en) | 2008-09-05 | 2021-05-05 | Mitsubishi Electric Corporation | High-frequency circuit package and sensor module |
TWI570854B (zh) | 2015-08-10 | 2017-02-11 | 頎邦科技股份有限公司 | 具中空腔室之半導體封裝結構及其下基板及製程 |
TWI663701B (zh) * | 2017-04-28 | 2019-06-21 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
Citations (6)
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JP2001135775A (ja) * | 1999-09-22 | 2001-05-18 | Lucent Technol Inc | 集積回路マルチチップモジュールパッケージ |
JP2003163304A (ja) * | 2001-11-29 | 2003-06-06 | Mitsubishi Electric Corp | 高周波パッケージ |
JP2006210530A (ja) * | 2005-01-26 | 2006-08-10 | Sony Corp | 機能素子体及びその製造方法並びに回路モジュール |
WO2007058280A1 (ja) * | 2005-11-16 | 2007-05-24 | Kyocera Corporation | 電子部品封止用基板および複数個取り形態の電子部品封止用基板、並びに電子部品封止用基板を用いた電子装置および電子装置の製造方法 |
WO2010026990A1 (ja) | 2008-09-05 | 2010-03-11 | 三菱電機株式会社 | 高周波回路パッケージおよびセンサモジュール |
JP2010258137A (ja) * | 2009-04-23 | 2010-11-11 | Panasonic Corp | 高周波モジュールおよびその製造方法 |
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JP3609935B2 (ja) * | 1998-03-10 | 2005-01-12 | シャープ株式会社 | 高周波半導体装置 |
US6137693A (en) * | 1998-07-31 | 2000-10-24 | Agilent Technologies Inc. | High-frequency electronic package with arbitrarily-shaped interconnects and integral shielding |
US6486534B1 (en) | 2001-02-16 | 2002-11-26 | Ashvattha Semiconductor, Inc. | Integrated circuit die having an interference shield |
US6998292B2 (en) * | 2001-11-30 | 2006-02-14 | Vitesse Semiconductor Corporation | Apparatus and method for inter-chip or chip-to-substrate connection with a sub-carrier |
JP3858854B2 (ja) * | 2003-06-24 | 2006-12-20 | 富士通株式会社 | 積層型半導体装置 |
US7613010B2 (en) * | 2004-02-02 | 2009-11-03 | Panasonic Corporation | Stereoscopic electronic circuit device, and relay board and relay frame used therein |
US7514774B2 (en) * | 2006-09-15 | 2009-04-07 | Hong Kong Applied Science Technology Research Institute Company Limited | Stacked multi-chip package with EMI shielding |
JP4833192B2 (ja) * | 2007-12-27 | 2011-12-07 | 新光電気工業株式会社 | 電子装置 |
-
2012
- 2012-01-31 CN CN201280017668.6A patent/CN103460377B/zh active Active
- 2012-01-31 JP JP2013509810A patent/JP5693710B2/ja active Active
- 2012-01-31 WO PCT/JP2012/052117 patent/WO2012140934A1/ja active Application Filing
- 2012-01-31 US US14/111,107 patent/US9693492B2/en active Active
- 2012-01-31 EP EP12771789.0A patent/EP2698819B1/en active Active
Patent Citations (6)
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JP2001135775A (ja) * | 1999-09-22 | 2001-05-18 | Lucent Technol Inc | 集積回路マルチチップモジュールパッケージ |
JP2003163304A (ja) * | 2001-11-29 | 2003-06-06 | Mitsubishi Electric Corp | 高周波パッケージ |
JP2006210530A (ja) * | 2005-01-26 | 2006-08-10 | Sony Corp | 機能素子体及びその製造方法並びに回路モジュール |
WO2007058280A1 (ja) * | 2005-11-16 | 2007-05-24 | Kyocera Corporation | 電子部品封止用基板および複数個取り形態の電子部品封止用基板、並びに電子部品封止用基板を用いた電子装置および電子装置の製造方法 |
WO2010026990A1 (ja) | 2008-09-05 | 2010-03-11 | 三菱電機株式会社 | 高周波回路パッケージおよびセンサモジュール |
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Non-Patent Citations (1)
Title |
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See also references of EP2698819A4 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015173140A (ja) * | 2014-03-11 | 2015-10-01 | 三菱電機株式会社 | 高周波パッケージ |
WO2024084556A1 (ja) * | 2022-10-18 | 2024-04-25 | 三菱電機株式会社 | 高周波半導体パッケージ |
Also Published As
Publication number | Publication date |
---|---|
EP2698819A4 (en) | 2014-10-01 |
EP2698819B1 (en) | 2019-08-14 |
JP5693710B2 (ja) | 2015-04-01 |
US20140085858A1 (en) | 2014-03-27 |
EP2698819A1 (en) | 2014-02-19 |
JPWO2012140934A1 (ja) | 2014-07-28 |
CN103460377B (zh) | 2017-09-22 |
CN103460377A (zh) | 2013-12-18 |
US9693492B2 (en) | 2017-06-27 |
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