WO2007060765A1 - Dispositif d’extraction de minutage, et appareil de reproduction d’informations et dispositif dvd utilisant ledit dispositif - Google Patents

Dispositif d’extraction de minutage, et appareil de reproduction d’informations et dispositif dvd utilisant ledit dispositif Download PDF

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Publication number
WO2007060765A1
WO2007060765A1 PCT/JP2006/314171 JP2006314171W WO2007060765A1 WO 2007060765 A1 WO2007060765 A1 WO 2007060765A1 JP 2006314171 W JP2006314171 W JP 2006314171W WO 2007060765 A1 WO2007060765 A1 WO 2007060765A1
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WIPO (PCT)
Prior art keywords
frequency
extraction device
timing extraction
clock
output
Prior art date
Application number
PCT/JP2006/314171
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English (en)
Japanese (ja)
Inventor
Kouji Okamoto
Akira Yamamoto
Hiroki Mouri
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Matsushita Electric Industrial Co., Ltd.
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Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to JP2006552389A priority Critical patent/JP4124798B2/ja
Publication of WO2007060765A1 publication Critical patent/WO2007060765A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the present invention relates to a timing extraction device that extracts timing information contained in a read signal from a read signal read from a recording medium such as an optical disk.
  • this feedback type timing extraction device quantizes the input reproduction signal by the AZD converter 1 and passes the phase correction through the offset correction unit 8 based on the quantized data.
  • the frequency error and phase error are calculated by the wave number comparator 13, the obtained digital correction amount is converted to an analog value by the DZA converter (not shown) through the loop filter 14, and the oscillation of the VCO (voltage controlled oscillator) 15 It is configured to control the frequency.
  • the clock that drives the AZD change 1 and the digital units 8, 13, and 14 and the reproduction signal are synchronized.
  • the decoding of data since the clock and the quantized data are synchronized, it is possible to perform a decoding process based on the quantized data.
  • Patent Document 2 has also studied a feedforward type timing extraction circuit using a frequency synthesizer operating at a fixed rate.
  • Figure 21 shows the block configuration of the feedforward type timing extractor.
  • This feed forward method uses an AZD variant that quantizes the playback signal with a fixed rate clock of a constant clock oscillator 18 that generates and outputs a clock with a constant period (fixed rate), and a digital data sequence quantized with this AZD variant.
  • the fixed rate clock the synchronous clock arithmetic circuit 17 estimates the edge position of the synchronous clock, the interpolation circuit 16 performs the interpolation processing of the quantized data, and the fixed rate clock is thinned out.
  • a pseudo-synchronized clock Data CLK is generated, and a decoding process is performed using the quantized data after the interpolation process and the pseudo-synchronized clock Data CLK.
  • the feedforward control is a method of calculating the correction amount for the quantized data sequence force and performing correction processing on the already quantized data sequence, so that the influence of the clock latency is affected. Therefore, it is suitable for high-speed playback.
  • Patent Document 1 Japanese Patent Laid-Open No. 2002-8315
  • Patent Document 2 JP-A-8-161829
  • this feed-forward type timing extraction device requires a clock that always operates at a fixed rate (usually a frequency synthesizer or the like is used to generate this clock). It is assumed that the sample is oversampled with respect to the playback frequency (playback rate) of the playback signal. Therefore, and the playback frequency of the playback signal
  • FIG. 22 shows the relationship between the fixed CLK and Data CLK in FIG. 21 when the playback speed changes continuously.
  • the object of the present invention is to obtain timing information from a reproduction signal.
  • the feed-forward type timing extractor that extracts, even if the reproduction frequency (reproduction rate) changes with time, the ratio of thinning out the fixed clock is fixed, and the power consumption is optimized. This makes it possible to simplify the control when a digital waveform equalizer operating at a constant clock is connected to the output stage of the variable ⁇ .
  • the output clock of the clock generation unit and the reproduction frequency (reproduction rate) of the reproduction signal are set.
  • the frequency division ratio of the clock generator is adjusted so that the frequency ratio is constant.
  • the timing extraction device of the present invention generates a clock according to a set division ratio in a timing extraction device in an information reproduction device that extracts data and a recording timing of the data from a reproduction signal.
  • Output of the clock generation unit, quantization means for quantizing and outputting the reproduction signal at the timing of the output clock of the clock generation unit, and a specific pattern and a specific pattern included in the output sequence of the quantization unit The appearance interval or both are measured based on the output clock of the clock generation unit, and the frequency between the reproduction frequency of the reproduction signal and the frequency of the output clock of the clock generation unit based on the measured value.
  • a frequency ratio calculation unit for calculating a ratio, and a phase correction value of the output clock of the clock generation unit for the quantized signal of the quantization means In response to the phase correction amount calculation unit, the frequency ratio calculated by the frequency ratio calculation unit, and the phase correction amount calculated by the phase correction amount calculation unit, the division ratio of the clock generation unit, A control unit that calculates and sets a cycle of an output clock of the clock generation unit with respect to a reproduction cycle of a reproduction signal; and A pseudo-synchronous clock generator that generates a clock that is pseudo-synchronized with the recording timing of the recording data by thinning out the output clock of the clock generator.
  • the control unit when the start signal or the restart signal of the reproduction process is input, the control unit has a preset frequency ratio of the frequency ratio calculation unit.
  • Set the division ratio of the clock generator as The frequency division ratio of the clock generation unit is updated so that the frequency ratio of the frequency ratio calculation unit is constant based on the phase correction amount of the phase correction amount calculation unit.
  • the control unit when the start signal or the restart signal of the reproduction process is input, the control unit has a frequency ratio set in advance by the frequency ratio calculation unit.
  • the frequency ratio of the clock generation unit is set as described above and the frequency ratio of the frequency ratio calculation unit exceeds a preset threshold, the phase correction amount of the phase correction amount calculation unit is used. Then, the frequency division ratio of the clock generation unit is updated so that the frequency ratio of the frequency ratio calculation unit falls within the threshold value.
  • the control unit when the start signal or the restart signal of the reproduction process is input, the control unit has a preset frequency ratio of the frequency ratio calculation unit.
  • the frequency division ratio of the clock generation unit is set so that the frequency ratio of the frequency ratio calculation unit is constant when the frequency ratio of the frequency ratio calculation unit changes thereafter. It is characterized by updating the division ratio.
  • the control unit assumes that the frequency ratio of the frequency ratio calculation unit is a preset value. Then, when the frequency ratio of the frequency ratio calculation unit exceeds a preset threshold, the frequency ratio of the frequency ratio calculation unit falls within the threshold.
  • the division ratio of the clock generation unit is updated so as to be within the range.
  • the present invention provides the timing extraction device in which the appearance interval of the specific pattern included in the output sequence of the quantization means is based on the pseudo-synchronization clock of the pseudo-synchronization clock generation unit after the reproduction process is started. Is compared with the ideal value when measured with a synchronous clock, and when the preset value is exceeded continuously for a preset number of times, restart is performed to update the division ratio of the clock generator. A restart signal generation unit for generating a signal is provided.
  • the present invention provides the timing extraction apparatus, wherein when the reproduction processing start signal or restart signal is input, the control unit performs the frequency ratio calculation of the frequency ratio calculation unit. After setting the frequency division ratio of the clock generation unit so that the rate becomes a preset value, the frequency ratio of the frequency ratio calculation unit exceeds the preset value continuously for a preset number of times. Sometimes, a restart signal generator for generating a restart signal is provided.
  • the present invention provides the timing extraction device, wherein when the start signal or restart signal of the reproduction process is input, the control unit has a frequency at which the frequency of the output clock of the clock generation unit is set in advance.
  • the frequency dividing ratio of the clock generation unit is set so as to be less than.
  • the present invention provides the timing extraction device, wherein the control unit uses the result of smoothing the phase correction amount of the phase correction amount calculation unit and the frequency ratio of the frequency ratio calculation unit, The reproduction cycle of the clock generation unit with respect to the reproduction cycle of the reproduction signal is calculated and output to the pseudo synchronous clock generation unit.
  • the present invention provides the timing extraction apparatus, wherein when the output sequence of the quantization means is binarized with "0" and "1", the ratio of consecutive "0" and “1” of the specific pattern Is 14: 4 or 4:14 for 0 ⁇ 0—1 ⁇ 01 ⁇ 71 ⁇ [, where the recording data is recorded, 11:11 for CD, 2 for Blu-ray : 9: 9 or 9: 9: 2 ratio.
  • the present invention provides the timing extraction device, wherein the appearance interval of the specific pattern in the output sequence of the quantization means is a medium on which the recording data is recorded when measured at the reproduction rate of the reproduction signal. 1488 for DVD-ROMZRAM, 588 for CD, and 1932 for Blu-ray.
  • the present invention provides the timing extraction device, wherein an output of the quantizing unit is connected to an offset correcting unit for correcting an offset included in the output of the quantizing unit, and the frequency ratio calculating unit
  • the phase correction amount calculation unit operates using the output of the offset correction unit instead of the output of the quantization unit.
  • the present invention provides the timing extraction device, wherein the output of the quantizing unit performs waveform equalization of the output of the quantizing unit based on an output clock of the clock generating unit.
  • a waveform equalization unit is connected, and the frequency ratio calculation unit and the phase correction amount calculation unit operate using the output of the waveform equalization unit instead of the output of the quantization unit.
  • the present invention is directed to the timing extraction device, wherein an input of the quantization means is connected to an analog filter that performs waveform equalization of the reproduced signal or high-frequency noise removal processing.
  • the equalization characteristic or cutoff characteristic of the analog filter is changed according to a frequency division ratio of the clock generation unit.
  • the division ratio of the clock generation unit which is an output of the control unit, includes an integer part and a decimal part, and the clock generation unit performs fractional division control. It is a frequency synthesizer capable of performing
  • the information reproduction device of the present invention is configured to output the data from the output of the quantization means included in the timing extraction device based on the output of the timing extraction device and a pseudo-synchronous clock generation unit included in the timing extraction device. And a signal processing circuit for decoding.
  • the DVD device of the present invention based on the output of the timing extraction device and the pseudo synchronous clock generation unit included in the timing extraction device, the data from the output of the quantization means included in the timing extraction device. And a signal processing circuit for decoding.
  • the present invention is characterized in that, in the timing extraction device, the reproduction signal is supplied through a communication path including a wireless communication path, an optical fiber, a coaxial cable, or a power line.
  • the present invention is characterized in that, in the timing extraction device, the reproduction signal is supplied from an optical disc card including a DVD disc, a CD disc, or a Blu-ray disc.
  • the frequency ratio calculation unit includes the specific pattern included in the output sequence of the quantizing means or the appearance of the specific pattern. The interval or both are measured based on the output clock of the clock generation unit, and the reproduction frequency (reproduction rate) of the reproduction signal and the frequency ratio of the output clock of the clock generation unit are calculated. And the control unit generates the clock With respect to the division ratio set in the unit, the division ratio of the clock generation unit is updated so that, for example, the calculated frequency ratio becomes a preset frequency ratio in accordance with the calculated frequency ratio.
  • the frequency of the reproduction signal and the frequency of the output clock of the clock generation unit are always maintained at a constant frequency ratio. It is possible to set the interval to be constant or within a certain range. As a result, the output clock of the clock generator is set to a high-frequency fixed rate clock in consideration of changes in the signal reproduction speed as in the past. Compared with, power consumption is reduced because it is not necessary to operate the digital circuit at high speed.
  • the timing extraction device of the present invention in the feed-forward type that extracts timing information from a reproduction signal, the reproduction frequency (reproduction rate) of the reproduction signal and the output clock of the clock generation unit Since the frequency ratio with respect to the frequency is controlled to be a desired constant value or a value within a preset range, the power consumption of the system can be optimized and the control can be simplified. It is possible to provide a timing extraction device.
  • FIG. 1 is a block diagram of a timing extraction device according to a first embodiment of the present invention.
  • FIG. 2 is a diagram showing a DVD data format.
  • FIG. 3 is a block diagram of the frequency ratio calculation unit 2 in FIG.
  • FIG. 4 is another configuration diagram of the frequency ratio calculation unit 2 in FIG.
  • FIG. 5 is a diagram showing the phase state of the output clock of the frequency synthesizer 6 standardized by the channel bit period.
  • FIG. 6 is a diagram showing the relationship between the correction amount of the phase correction unit 3 and the output sample of the AZD converter 1 It is.
  • FIG. 7 is a configuration diagram of the control unit 4 in FIG. 1.
  • FIG. 8 is a configuration diagram of the smoothing filter 42 in FIG.
  • FIG. 9 is a diagram showing an operation process of the control unit in FIG.
  • FIG. 10 is a block diagram of a similar synchronous clock generator 5.
  • FIG. 11 is a diagram showing a timing chart of the pseudo synchronous clock generation unit 5.
  • FIG. 12 is a diagram showing a configuration example of the frequency synthesizer 6 in FIG.
  • FIG. 13 is a diagram showing a timing chart of the timing extraction device in FIG. 1.
  • FIG. 14 is a block diagram showing a modification of the timing extraction device shown in FIG. 1.
  • FIG. 15 is a block diagram showing another modification of the timing extraction device shown in FIG. 1.
  • FIG. 16 is a block diagram showing another modification of the timing extraction device shown in FIG. 1.
  • FIG. 17 is a block diagram showing still another modification of the timing extraction device shown in FIG. 1.
  • FIG. 18 is a block diagram showing still another modification of the timing extraction device shown in FIG. 1.
  • FIG. 19 is a block diagram showing an overall schematic configuration of an information reproducing apparatus including the timing extracting device shown in FIG.
  • FIG. 20 is a block diagram showing a configuration of a conventional feedback type timing extraction device used in an optical disk reproducing device or the like.
  • FIG. 21 is a block diagram showing a configuration of a conventional feedforward type timing extraction device used in an optical disk reproducing device or the like.
  • FIG. 22 is a diagram showing a timing chart of the circuit of FIG.
  • FIG. 1 is a block diagram showing a first embodiment of the timing extraction device of the present invention.
  • the timing extraction device of the present embodiment is an information reproduction device that extracts recording data and its data recording timing from an analog reproduction signal that is recorded when reproducing the data recorded on a recording medium such as an optical disk.
  • a recording medium such as an optical disk.
  • FIG. 1 1 is an AZ D converter
  • 2 is a frequency ratio calculation unit
  • 3 is a phase correction amount calculation unit
  • 4 is a control unit
  • 5 is a pseudo-synchronous clock generation unit
  • 6 is a frequency synthesizer (clock generation unit). is there. The detailed operation of each block is described below.
  • the AZD variation is sampled based on the output clock of the frequency synthesizer 6 for the input reproduction signal, quantized and output.
  • the frequency ratio calculation unit 2 measures the intermediate specific pattern of the output sequence of the AZD converter (quantization means) 1 and / or the appearance interval of the specific pattern based on the output clock of the frequency synthesizer 6.
  • the frequency ratio between the playback frequency of the playback signal (playback rate) and the output clock of the frequency synthesizer 6 is calculated based on the measured value.
  • the specific pattern for example, when the playback signal is a DVD or CD, a sync mark is used.
  • Fig. 2 shows the data format of the DVD-ROM.
  • DVD-ROM is composed of ECC blocks (Error Correction Coding Blocks).
  • ECC block consists of 16 sectors, and one sector consists of 26 frames.
  • One frame consists of 1488 channel bit data, and a sync mark is inserted in its header.
  • This sync mark is a specific pattern consisting of a predetermined bit interval. For example, in the case of DVD-ROM, “1” of 14 consecutive channel bits and “0” of 4 consecutive channel bits, or It consists of 14 consecutive channel bits “0” and 4 consecutive channel bits “1”. At this time, a sync mark appears every 1488 channel bits.
  • the sync mark is a continuous 11 channel bit “0” and a continuous 11 channel bit “1”, or vice versa, and appears every 588 channel bits.
  • the sync mark in Blu-ray is a continuous 2-channel bit “0” and a continuous 9-channel bit “1” and a continuous 9-channel bit “0”, or vice versa. Appears on.
  • Such a sync mark is a pattern that does not appear in the user data. Therefore, by using this sync mark, the reproduction signal reproduction frequency (reproduction rate) and the frequency ratio of the frequency synthesizer can be calculated.
  • the sync ratio detector 21, the divider 22, and the sync mark setting value 23 constitute the frequency ratio calculation unit 2.
  • the sync mark detector 21 detects a sync mark from the output series of AZD changes.
  • AZD change 1 does not necessarily operate at the channel bit period, so the output sequence of AZD converter 1 is binarized and sync mark detection is performed based on the state transition interval. There is a need to do.
  • the sync mark may be detected when the ratio of the interval between state transitions is proportional to 14: 4 (7: 2).
  • the sync mark detection may be set with a margin.
  • the reproduction frequency (reproduction level of the reproduction signal) is obtained.
  • Frequency ratio or period ratio of the frequency synthesizer.
  • FIG. 4 can be considered as another configuration of the frequency ratio calculation unit 3.
  • 21 is a sync mark detector
  • 24 is a sync mark interval counter
  • 22 is a divider
  • 25 is a sync mark interval set value.
  • the measured value obtained by counting the interval between two consecutive sync marks detected by the sync mark detector 21 using the output clock of the frequency synthesizer 6 (of the sync mark interval counter 24). Output) is used to calculate the frequency ratio (or period ratio).
  • a sync mark appears for every 1488 channel bits in the case of DVD-ROM, and by using these, a more accurate frequency ratio (or period ratio) can be calculated.
  • the reproduction signal reproduction frequency (reproduction rate) and the frequency ratio (or period ratio) of the output synthesizer 6 can be calculated in this way, the period ratio of the frequency synthesizer 6 to the reproduction period can be calculated.
  • the pseudo-synchronous clock generator 5 can calculate the timing at which the output clock of the frequency synthesizer 6 is thinned out. Note that regarding the timing of thinning out, it is necessary to reflect the output result of the phase correction amount calculation unit 3 in consideration of jitter and frequency fluctuation of the reproduction signal.
  • FIG. 5 shows a timing chart of the reproduction signal channel clock and the frequency synthesizer 6 output clock.
  • the reference edge is aligned, and the frequency of the output clock of the frequency synthesizer 6 is 2.5 times the playback frequency (playback rate) of the playback signal.
  • the edge of the output clock of the frequency synthesizer 6 often does not coincide with the reference point, so phase correction must be performed.
  • the phase error as shown in Fig.
  • phase error value perr up to the zero cross point of the reference value force reproduction signal.
  • the ratio between the playback frequency (playback rate) of the playback signal and the frequency of the output clock of the frequency synthesizer 6 is known, so the phases of the two sample values before and after the zero cross point of the playback signal ⁇ 1, ⁇ 2 can be calculated.
  • These voltage values VI and V2 at phases 0 1 and 0 2 are also known because they are the output results of AZD changes. Therefore, the phase error value perr is
  • phase correction amount calculation unit 3 calculates the phase correction amount between the output clock of the frequency synthesizer 6 and the reproduction signal.
  • the control unit 4 receives the output of the frequency ratio calculation unit 2 and the output of the phase correction amount calculation unit 3 as inputs. Generate two control signals. The first is the frequency division ratio of the frequency synthesizer 6. The second is the period of the output clock of the frequency synthesizer 6 with respect to the reproduction period of the reproduction signal output to the pseudo synchronous clock generation unit. This period is a value indicating how many periods of the output clock of the current frequency synthesizer 6 is, assuming that the channel bit period is 1.
  • Figure 7 shows an example of the configuration of the control unit 4. In the configuration of FIG. 7, the frequency ratio lock detector 41 detects whether or not the frequency ratio has become steady after the start Z restart signal is input. This start / restart signal is a control signal output from a system controller (not shown).
  • the smoothing filter 42 is a smoothing filter that smoothes the phase correction amount.
  • the configuration of the smoothing filter 42 for example, a configuration that performs a proportional operation as shown in FIG. 8 and a configuration that includes a partial force that performs an integration operation are conceivable.
  • the output of the selector 421 becomes 0, the integrator is also reset to 0, and the output of this block becomes 0.
  • the phase correction amount is divided into proportional and integral terms.
  • the multiplier 422 multiplies the gain by Gp.
  • the integral term is multiplied by Gi by the multiplier 423 and then integrated by the integrator 424.
  • Each term is subjected to addition processing by an adder 425 and output as an output of the smoothing filter 42 to an adder 43 connected to the next stage.
  • the adder 43 adds the frequency ratio from the frequency ratio calculation unit 2 and the output of the smoothing filter 42 to obtain the current frequency synthesizer. Outputs the size of the output clock of sizer 6 (value standardized with the channel bit cycle set to 1).
  • the target frequency ratio setting unit 44 the frequency ratio that is the target of the frequency of the output clock of the frequency synthesizer 6 and the reproduction frequency of the reproduction signal is set, and this target frequency ratio is the frequency of the output clock of the frequency synthesizer 6. Is set in advance so that it does not always fall below the preset frequency.
  • the frequency division ratio calculation unit 45 calculates the frequency division ratio of the frequency synthesizer 6 based on the frequency ratio information calculated by the frequency ratio calculation unit 2 and the target frequency ratio of the target frequency ratio setting unit 44. calculate.
  • FIG. 9 shows an operation process of the control unit 4 related to the division ratio calculation. A process called “Calculate the division ratio so that the frequency ratio calculation result is the target frequency ratio” ,
  • the frequency division ratio of the frequency synthesizer 6 is preferably set by Equation 3.
  • Equation 3 after the frequency ratio lock is detected, only the output fluctuation of the force smoothing filter 42 or the frequency ratio is reset based on the output fluctuation of the adder 43.
  • the same effect can be obtained by recalculating the frequency division ratio of the frequency synthesizer 6 using only the fluctuation of.
  • it may be controlled so that the division ratio is reset only when a preset threshold value is exceeded.
  • FIG. 10 shows the configuration of the pseudo synchronous clock generation unit 5.
  • the synth period that is the output of the control unit 4 is input to the edge generation circuit 51.
  • the AND circuit 52 performs an AND operation on the edge generation circuit and the output clock of the frequency synthesizer 6 and outputs the result as a data clock.
  • the edge generation circuit 51 performs modi calculation of the input synth period. Specifically, accumulation processing is performed for the input synth period, and if the calculation result exceeds “1”, the result obtained by subtracting “1” is taken as the accumulation result.
  • the example shown in Fig. 11 shows a case where the frequency ratio between the frequency synthesizer and the playback rate is 1.33 (the playback rate period is 1 and converted to a period ratio of 0.75). .
  • the synth period is a constant value of 0.75. Therefore, the edge generation circuit 51 performs 0.75 accumulation processing in synchronization with the output clock of the frequency synthesizer 6.
  • modi calculation is performed every time when it is simply accumulated, 0, 0.75, 1.5, ..., so the phase that is the result of modi calculation is 0, 0.75, 0.5 (1.5 is 1.
  • the result of subtracting 1 from 1.5 is the modi operation result).
  • the edge output becomes HI when subtraction is performed when modi operation is performed.
  • Data CLK is the result of AND operation of this edge output and the output clock of frequency synthesizer 6. is there.
  • FIG. 12 shows a configuration example of the frequency synthesizer 6.
  • a fractional frequency synthesizer is shown.
  • 61 is the phase frequency comparator that compares the phase Z frequency of the reference signal and the frequency synthesizer output clock
  • 62 is the charge pump
  • 63 is the loop filter
  • 64 is the VCO
  • 65 is the output of VC064 NZN + 1 minute
  • a frequency divider 66 a pulse slow counter 66, and a ⁇ modulator 67.
  • the fractional frequency division type frequency synthesizer has been described as the clock generation unit.
  • a clock generation unit having an oscillator, a frequency divider, and a modulator power may be used instead. Similar effects can be obtained.
  • the frequency division ratio of the frequency divider uses a modulation signal generated by the modulator according to the input frequency division ratio.
  • a ⁇ modulator is generally used as the modulator.
  • FIG. 13 shows a timing chart of the timing extraction device of the present system when the reproduction frequency (reproduction rate) of the reproduction signal changes.
  • the frequency division ratio of the frequency synthesizer 6 is made constant (or within a certain range) according to the playback frequency (playback rate) of the playback signal and the playback signal playback frequency (playback rate) and the frequency synthesizer 6 frequency ratio.
  • FIGS. 14 to 18 are block diagrams showing modifications of the first embodiment of the timing extraction device of the present invention.
  • the start Z restart signal (restart signal generator) is not input directly from the start Z restart signal input from the controller (not shown). )
  • the start Z restart signal is generated via 71.
  • the start Z restart signal generation unit 71 resamples the output series of the AZD converter 1 with Data CLK, and the sync mark or sync mark Check whether the appearance interval is equal to the ideal value when measured with a synchronous clock and can be detected normally, and set the preset value continuously for the preset number of times. If exceeded, the start Z restart signal is generated so as to reset the frequency synthesizer 6 division ratio.
  • a start Z restart signal of a reproduction process input from a controller (not shown) is input to the start Z restart generation unit 72 and this start is performed.
  • a start Z restart signal is generated via the Z restart generation unit 72.
  • the start Z restart signal generation unit 72 samples the output sequence of the AZD change with the output clock of the frequency synthesizer 6, and performs a sync mark or Check whether the appearance interval of the sync mark is normal or not, and if it exceeds the preset value continuously for a preset number of times, the frequency synthesizer 6 frequency division ratio is reset.
  • the start Z restart signal is generated as set.
  • start Z restart generation units 71 and 72 shown in FIG. 14 and FIG. 15 have the frequency ratio of the frequency ratio calculation unit 2 exceeded a preset value continuously for a preset number of times. In some cases, a restart signal may be generated.
  • an offset correction unit 8 is further connected to the output stage of the AZD change with respect to the timing extraction device shown in FIG. 1, and the timing extraction calculation is performed after offset correction of the reproduction signal.
  • a digital waveform equalizer 91 is further connected to the output stage of the AZD conversion 1 for the timing extraction device shown in FIG. 1, and the waveform equalization processing of the reproduction signal is performed in the digital domain. After that, the timing extraction calculation is performed.
  • control is performed so that the frequency ratio between the reproduction frequency of the reproduction signal (reproduction rate) and the output clock of the frequency synthesizer 6 is always constant or within a certain range.
  • an analog filter 92 is further connected to the timing extraction apparatus shown in FIG. 1 before the AZD transformation 1, and waveform equalization processing or high-frequency noise removal processing of the reproduction signal is performed in the analog domain. Then, the timing extraction calculation is performed.
  • the filter characteristics of the analog filter 92 It is necessary to adjust the characteristics according to changes in In this configuration, since the equalization characteristic or cutoff characteristic of the analog filter 92 can be adjusted in accordance with the frequency division ratio of the frequency synthesizer 6 output from the control unit 4, the control can be greatly simplified.
  • FIG. 19 is a block diagram showing an overall schematic configuration of an information reproducing apparatus including the LSI 12 incorporating the present timing extraction apparatus.
  • the description is applied to a DVD playback device and the like.
  • the information recording unit 10 is a recording medium (DVD medium)
  • the information reading unit 11 is a pickup that reads recorded data from the recording medium
  • the LSI 12 is read by the pickup.
  • a signal processing circuit (not shown) that performs waveform equalization, error correction, data demodulation, and the like using the reproduced signal waveform.
  • information is displayed and converted into sound.
  • timing information included in a reproduction signal from a recording medium such as a DVD is extracted has been described.
  • a wireless communication path such as an optical fiber, a coaxial cable, and a power line
  • the present invention can also be applied to extracting timing information included in a signal supplied via a wired communication path.
  • timing extraction device of the present invention for example, the control of the division ratio setting by the target frequency ratio setting unit 44 and the division ratio calculation unit 45 built in the control unit 4 shown in FIG. It goes without saying that the timing information may be extracted by performing the above. Industrial applicability
  • the frequency of the reproduction signal (reproduction rate) and the frequency of the output clock frequency of the clock generation unit (frequency synthesizer).
  • the ratio is also useful as an information reproduction apparatus that extracts timing information, such as a timing extraction apparatus for an optical disc.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Dans un dispositif d’extraction de minutage de type à correction aval permettant d’extraire des informations de minutage à partir d’un signal de reproduction, une unité de calcul de rapport de fréquence (2) utilise un motif particulier dans le signal de reproduction et son intervalle d’apparition pour obtenir un rapport de fréquence entre la fréquence du signal de reproduction et la fréquence de l’horloge de sortie d’un synthétiseur de fréquence (6). Une unité de commande (4) commande le rapport de division du synthétiseur de fréquence (6) de sorte que le rapport de fréquence calculé dans l’unité de calcul de rapport de fréquence (2) est une valeur prédéterminée. En conséquence, il n’est pas nécessaire d’utiliser un circuit numérique avec une grande vitesse par rapport au cas dans lequel l’horloge de sortie du synthétiseur de fréquence (6) est réglée sur une horloge de vitesse fixe présentant une fréquence élevée. C’est la raison pour laquelle, même si la fréquence de reproduction (vitesse de reproduction) d’un signal varie dans le temps, la vitesse d’amincissement d’une horloge fixe devient constante et la consommation est réduite.
PCT/JP2006/314171 2005-11-28 2006-07-18 Dispositif d’extraction de minutage, et appareil de reproduction d’informations et dispositif dvd utilisant ledit dispositif WO2007060765A1 (fr)

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JPWO2007060765A1 (ja) 2009-05-07
JP4124798B2 (ja) 2008-07-23

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