KR960017939A - 상이한 두께의 게이트 산화물을 반도체층에 성장하기 위한 프로세스 - Google Patents

상이한 두께의 게이트 산화물을 반도체층에 성장하기 위한 프로세스 Download PDF

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KR960017939A
KR960017939A KR1019950044509A KR19950044509A KR960017939A KR 960017939 A KR960017939 A KR 960017939A KR 1019950044509 A KR1019950044509 A KR 1019950044509A KR 19950044509 A KR19950044509 A KR 19950044509A KR 960017939 A KR960017939 A KR 960017939A
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치티패디 사이레쉬
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엘리 와이스
에이티 앤드 티 코포레이션
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    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

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Abstract

상이한 두께의 게이트 산화물은 반도체층을 기판상에 성장하는 단계와, 산화물층을 반도체층상에 성장하는 단계와, 산화물층의 선택 영역을 노출시키는 단계와, 노출된 산화물 아래의 반도체층을 비결정화 하는 단계와,비결정화 영역과 결정화 영역을 갖는 반도체층을 노출하도록 산화물층을 제거하는 단계와, 게이트 산화물을 반도체층의 비결정화 영역과 결정화 영역상에 성장하는 단계를 포함한 프로세스로 반도체층상에 성장된다. 비결정화 영역상에 성장된 게이트 산화물은 결정화 영역상에 성장된 게이트 산화물 보다 두껍게 된다. 본 발명의 프로세스는 설계 변경을 제조하는 특정의 집적 회로를 필요로 하지 않으며 각종 디바이스, 특히 MOS형 디바이스를 용이하게 제조가능케 한다.

Description

상이한 두께의 게이트 산화물을 반도체층에 서장하기 위한 프로세스
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (25)

  1. 상이한 두개의 게이트 산화물을 반도체 기판에 성장시키는 프로세스에 있어서, 반도체층을 가판상에 성장시키는 단계와, 산화물층을 상기 반도체층상에 증착시키는 단계와, 상기 반도체충의 선택된 영역을 비결정화 하는 단계와, 상기 산화물층을 제거시켜 비결정화 영역 및 결정화 영역을 갖는 상기 반도체층을 노출시키는 단계와, 상기 반도체층의 결정화 영역 및 비결정화 영역상에 성장시켜 상이한 두개의 게이트 산화물을 상기 반도체층상에 설치하는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  2. 제1항에 있어서, 상기 기판은 실리콘 웨이퍼인 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  3. 제1항에 있어서, 상기 반도체층은 에피택셜 실리콘, 다결정 실리콘 또는 실리콘 게르마늄인 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  4. 제1항에 있어서, 상기 산화물층을 성장하기 전에, 희생 열적 산화물을 상기 반도체층상에 성장, 제거하는 상기 단계는 상기 반도체층의 표면으로부터의 결합을 제거하도록 실행되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  5. 제1항에 있어서, 상기 반도체층에는 상기 산화물층을 성장하기 전에 복수의 디바이스 터브가 설치되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  6. 제1항에 있어서, 상기 산화물층은 상기 기판을 약 600℃ 내지 1200℃의 온도 범위로 가열하여 상기 기판을 산화시키므로써 상기 기판상에 성장되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  7. 제1항에 있어서, 상기 산화물층은 약 60A 내지 약 500A의 두께 범위를 가지는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  8. 제1항에 있어서, 상기 산화물층은 약 80A 내지 약 200A의 두께 범위를 가지는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  9. 제1항에 있어서, 상기 반도체층의 선택 영역을 비결정화 하는 상기 단계는 마스킹층을 산화물층상에 증착시켜 상기 마스킹층을 패턴화시키므로써 상기 산화물층의 선택 영역을 노출시키는 윈도우를 설치한 후, 상기 노출 산화물층 아래의 상기 반도체층에 이온을 주입하는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  10. 제9항에 있어서, 상기 이온을 실리콘, 플루오르, 비소, 및 이들의 혼합물로 이루어진 군(group)에서 선택되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  11. 제9항에 있어서, 상기 이온은 이온 믹싱 주입을 통해 주입되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  12. 제9항에 있어서, 상기 이온은 ㎠당 약 1×1012내지 약 5x1016이온범위의 도우즈로 주입되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  13. 제9항에 있어서, 상기 이온은 ㎠당 약 1×1015내지 약 5x1015이온범위의 도우즈로 주입되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  14. 제9항에 있어서, 상기 이온온 약 5KeV 내지 약 500KeV 범위의 에너지로 주입되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  15. 제9항에 있어서, 상기 이온온 약 20KeV 내지 약 50KeV 범위의 에너지로 주입되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  16. 제1항에 있어서, 상기 산화물층은 제거되기전 어닐링되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  17. 제1항에 있어서, 상기 게이트 산화물은 상기 기판을 약 600℃내지 약 1200℃의 온도 범위에서 가열시켜 상기 기판을 산화하므로써 상기 반도체층의 비결정화 영역과 결정화 영역상에서 성장되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  18. 제1항에 있어서, 상기 반도체층의 비결정화 영역상에 성장된 게이트 산화물은 약 40A 내지 500A의 두께 범위를 가지는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  19. 제1항에 있어서, 상기 반도체층의 비결정화 영역상에 성장된 게이트 산화물은 약 100A 내지 160A의 두께 범위를 가지는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  20. 제1항에 있어서, 상기 반도체층의 비결정화 영역상에 성장된 게이트 산화물은 약 20A 내지 400A의 두께 범위를 가지는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  21. 제1항에 있어서, 상기 기판의 비결정화 영역상에 성장된 게이트 산화물은 약 80A 내지 130A의 두께 범위를 가지는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  22. 제1항에 있어서, 상이한 두께의 게이트 산화물상에서 디바이스를 제조하는 단계를 더 포함하는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  23. 제22항에 있어서, 상기 디바이스는 듀얼 전압, 혼합 신호, 순수 아날로그 디바이스 및 디지탈 디바이스로 이루어진 군에서 선택되는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  24. 제22항에 있어서, 상기 디바이스는 MOS 디바이스인 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
  25. 제22항에 있어서, 적어도 하나의 디바이스는 약 1.8V 내지 약 3.3V의 전압 범위에서 동착하며, 적어도 하나의 디바이스가 야가 5V의 전압 범위에서 동작하는 것을 특징으로 하는 게이트 산화물의 성장 프로세스.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950044509A 1994-11-30 1995-11-29 상이한 두께의 게이트 산화물을 반도체층에 성장하기 위한 프로세스 KR960017939A (ko)

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