KR880004580A - 전력 mosfet와 제어회로가 통합된 반도체소자 - Google Patents

전력 mosfet와 제어회로가 통합된 반도체소자 Download PDF

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KR880004580A
KR880004580A KR870010532A KR870010532A KR880004580A KR 880004580 A KR880004580 A KR 880004580A KR 870010532 A KR870010532 A KR 870010532A KR 870010532 A KR870010532 A KR 870010532A KR 880004580 A KR880004580 A KR 880004580A
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semiconductor device
control circuit
semiconductor
semiconductor body
power mosfet
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KR870010532A
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KR930009475B1 (ko
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아이징거 요셉
라이폴드 루드비히
티한니 제뇌
베버 롤란드
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휘티시, 네테부쉬.
지멘스 악티엔게젤샤프트
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Publication of KR880004580A publication Critical patent/KR880004580A/ko
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Publication of KR930009475B1 publication Critical patent/KR930009475B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electronic Switches (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Ignition Installations For Internal Combustion Engines (AREA)

Abstract

내용 없음

Description

전력 MOSFET와 제어회로가 통합된 반도체소자
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1의 예시적인 실시예를 나타내는 간략화된 측면도.
제2도는 제1도에 보인 실시예의 평면도.
제3도는 본 발명의 제2실시예를 나타내는 평면도.

Claims (10)

  1. 전력 MOSFET 의 반도체 몸체의 어느하나의 주표면에 배치되고 절연층을 통해 반도체 몸체에 기계적으로 연결된 MOSFET 제어용 반도체 제어회로가 전력 MOSFET 와 별개로 집적되어 있는 것을 특징으로 하는 전력 MOSFET 와 제어회로가 통합된 반도체소자.
  2. 제1항에 있어서, 절연층이 전력 MOSFET 의 반도체 몸체위에 배치되어 있는 것을 특징으로 하는 반도체소자.
  3. 제1항에 있어서, 절연층이 제어회로의 반도체몸체위에 배치되어 있는 것을 특징으로하는 반도체소자.
  4. 상기항중 어느한항에 있어서, 상기 2개의 반도체몸체는 점착물에 의해 서로 고정되어 지는 것을 특징으로 하는 반도체소자.
  5. 제4항에 있어서, 상기 점착물은 절연성점착제인 것을 특징으로 하는 반도체소자.
  6. 상기항중 어느 한항에 있어서, 제어회로의 반도체몸체는 전력 MOSFET 의 반도체몸체위의 하나의 주표면에 배치되고, 상기 반도체 몸체의 다른 주표면은 방열기에 고정되는 것을 특징으로 하는 반도체소자.
  7. 상기항중 어느한 항에 있어서, 제어회로의 반도체몸체는 전력 MOSFET 의 반도체몸체와 열접촉되며, 제어회로는 온도가 예정된 열한계치에 도달할 때 신호를 발생하는 스위치에 전기적으로 연결된 열감지소자를 포함하는 것을 특징으로 하는 반도체소자.
  8. 상기항중 어느한 항에 있어서, 상기 제어회로는 자기절연 CMOS 제조기술로써 고농도로 도프된 기판위에 구성되고, 전력 MOSFET 와 떨어져 있는 그 반도체 몸체의 측면은 기판에 전기적으로 연결되어 있는 접점이 설치되어 있는 것을 특징으로 하는 반도체소자.
  9. 제8항에 있어서, 상기 접점은 기판과 동일한 도전성을 갖는 고농도로 도프된 지역위에 배치되는 것을 특징으로 하는 반도체소자.
  10. 제1도 및 제2도를 참고로 설명되고 또한 제3도내지 5도의 어느하나에 따라 변경된 전력 MOSFET 와 별개로 집적된 제어회로를 포함하는 반도체소자.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870010532A 1986-09-23 1987-09-23 전력 모스페트(mosfet)와 제어회로가 통합된 반도체소자 KR930009475B1 (ko)

Applications Claiming Priority (3)

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DE3632199.0 1986-09-23
DE3632199 1986-09-23
DEP3632199 1986-09-23

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KR880004580A true KR880004580A (ko) 1988-06-07
KR930009475B1 KR930009475B1 (ko) 1993-10-04

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KR1019870010532A KR930009475B1 (ko) 1986-09-23 1987-09-23 전력 모스페트(mosfet)와 제어회로가 통합된 반도체소자

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US (1) US4947234A (ko)
EP (1) EP0262530B1 (ko)
JP (1) JP2566207B2 (ko)
KR (1) KR930009475B1 (ko)
DE (1) DE3786314D1 (ko)
MY (1) MY102712A (ko)

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Publication number Publication date
JPS6387758A (ja) 1988-04-19
KR930009475B1 (ko) 1993-10-04
MY102712A (en) 1992-09-30
EP0262530B1 (de) 1993-06-23
US4947234A (en) 1990-08-07
DE3786314D1 (de) 1993-07-29
EP0262530A1 (de) 1988-04-06
JP2566207B2 (ja) 1996-12-25

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