KR20000058316A - 다층 인쇄회로기판 및 그 제조방법 - Google Patents
다층 인쇄회로기판 및 그 제조방법 Download PDFInfo
- Publication number
- KR20000058316A KR20000058316A KR1020000019037A KR20000019037A KR20000058316A KR 20000058316 A KR20000058316 A KR 20000058316A KR 1020000019037 A KR1020000019037 A KR 1020000019037A KR 20000019037 A KR20000019037 A KR 20000019037A KR 20000058316 A KR20000058316 A KR 20000058316A
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- Prior art keywords
- resin layer
- circuit board
- forming
- printed circuit
- circuit pattern
- Prior art date
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
- H05K2201/09527—Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1536—Temporarily stacked PCBs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
Claims (10)
- 절연성물질로 형성되는 수지층과,상기 수지층상에 형성되는 회로패턴을 포함하여 다층개의 층으로 구성된 인쇄회로기판에서,부품이 장착되어 연결되는 상면의 회로패턴의 두께를 메인 PCB측에 연결되는 하면의 회로패턴의 두께보다 얇게 형성한 것을 특징으로 하는 다층 인쇄회로기판.
- 절연성물질로 형성되는 수지층과,상기 수지층상에 형성되는 회로패턴을 포함하여 다수개의 층으로 구성된 인쇄회로기판에서,상기 다수개의 층 내부에 블라인드비어홀이 형성되고, 상기 블라인드비어홀의 외측에 상기 다수개의 층을 전기적으로 연결하는 도금층이 형성되며, 상기 블라인드비어홀 중심과 대략 일치되는 위치의 상면에 부품을 실장하기 위한 범프를 형성한 것을 특징으로 하는 다층 인쇄회로기판.
- 제 2 항에 있어서, 상기 범프의 직경은 상기 블라인드비어홀의 직경보다 크게 형성하는 것을 특징으로 하는 다층 인쇄회로기판.
- 절연성물질로 형성되는 수지층과,상기 수지층상에 형성되는 회로패턴을 포함하여 다수개의 층으로 구성된 인쇄회로기판에서,상기 다수개의 층 내부에 블라인드비어홀이 형성되고, 상기 블라인드비어홀은 부품이 실장되는 인쇄회로기판의 상면을 향하여 형성되어 상측이 막힌 상태로 되고, 블라인드비어홀의 상면에 부품실장용 범프가 형성된 것을 특징으로 하는 다층 인쇄회로기판.
- 코어형성용 수지층의 일측면에 이형제를 위치시키고, 상기 이형제를 포함하는 수지층의 일측면에 금속박판층과 적층수지층을 형성하는 제1단계와,상기 적층수지층을 관통하여 상하의 금속박판층을 전기적으로 연결하는 블라인드비어홀을 형성하는 제2단계와,상기 블라인드비어홀이 개구된 표면에 회로패턴을 형성하는 제3단계와,상기 회로패턴상에 적층수지층과 금속박판층을 형성하는 제4단계와,상기 적층수지층을 관통하여 상하의 금속박판층을 전기적으로 연결하는 블라인드비어홀을 형성하는 제5단계와,위에서 형성된 패널을 이형제를 이용하여 분리하는 제6단계와,상기 분리된 각각의 패널의 상면과 하면에 회로패턴을 형성하는 제7단계를 포함하여 구성됨을 특징으로 하는 다층 인쇄회로기판의 제조방법.
- 제 5 항에 있어서, 상기 제4단계와 제5단계를 반복하여 적층되는 층수를 결정함을 특징으로 하는 다층 인쇄회로기판의 제조방법.
- 제 5 항에 있어서, 상기 제2단계와 제5단계는 레이저를 이용하여 블라인드비어홀을 천공하는 단계와,상기 블라인드비어홀을 포함하는 외층에 도금층을 형성하는 단계를 포함하여 구성됨을 특징으로 하는 다층 인쇄회로기판의 제조방법.
- 제 5 항에 있어서, 상기 이형제 측면에 위치한 금속박판의 회로패턴에 부품 실장용 범프와 그 반대면의 회로패턴에 메인 PCB연결용 범프를 형성하는 8단계를 더 포함하여 구성됨을 특징으로 하는 다층 인쇄회로기판의 제조방법.
- 일측면에 제1금속박판과 반대면에 제2금속박판을 가지는 제1수지층을 제2금속박판 측에서 제1금속박판측으로 관통하여 상기 제1,2금속박판층을 전기적으로 연결하는 블라인드비어홀을 형성하는 제1단계와,상기 제2금속박판측 표면에 회로패턴을 형성하며 제1수지층을 노출시키는 제2단계와,제3금속박판을 한면에만 가지는 제2수지층을 상기 노출된 제1수지층과 마주하도록 상기 제1수지층에 제2금속박판측면에 적층하여 상기 제1수지층과 제2수지층을 일체화하는 제3단계와,상기 제3금속박판측에서 제2수지층을 관통하여 상기 제2금속박판과 제3금속박판을 전기적으로 연결하는 블라인드비어홀을 형성하는 제4단계와,상기 제1금속박판과 제3금속박판에 회로패턴을 형성하는 제5단계와,상기 제1금속박판의 회로패턴과 연결된 블라인드비어홀의 중심과 대략 일치하는 위치에 부품실장용 범프를 형성하는 제6단계를 포함하여 구성됨을 특징으로 하는 다층 인쇄회로기판의 제조방법.
- 제 9 항에 있어서, 상기 제1단계 및 제4단계에서 형성되는 블라인드비어홀에는 도금층을 형성하여 상하 금속박판을 연결하는 것을 특징으로 하는 다층 인쇄회로기판의 제조방법.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20000019037A KR100333627B1 (ko) | 2000-04-11 | 2000-04-11 | 다층 인쇄회로기판 및 그 제조방법 |
JP2001096366A JP5000809B2 (ja) | 2000-04-11 | 2001-03-29 | 多層印刷回路基板及びその製造方法並びに多層印刷回路基板を利用したbga半導体パッケージ |
US09/832,193 US6580036B2 (en) | 2000-04-11 | 2001-04-11 | Multi-layer printed circuit board and a BGA semiconductor package using the multi-layer printed circuit board |
US10/384,658 US6884945B2 (en) | 2000-04-11 | 2003-03-11 | Multi-layer printed circuit board and a BGA semiconductor package using the multi-layer printed circuit board |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020000019040A KR100366411B1 (ko) | 2000-04-11 | 2000-04-11 | 다층 인쇄회로기판 및 그 제조방법 |
KR20000019037A KR100333627B1 (ko) | 2000-04-11 | 2000-04-11 | 다층 인쇄회로기판 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20000058316A true KR20000058316A (ko) | 2000-10-05 |
KR100333627B1 KR100333627B1 (ko) | 2002-04-22 |
Family
ID=26637807
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR20000019037A KR100333627B1 (ko) | 2000-04-11 | 2000-04-11 | 다층 인쇄회로기판 및 그 제조방법 |
Country Status (3)
Country | Link |
---|---|
US (2) | US6580036B2 (ko) |
JP (1) | JP5000809B2 (ko) |
KR (1) | KR100333627B1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102883538A (zh) * | 2012-10-16 | 2013-01-16 | 田茂福 | Fpc自动成型机 |
KR101505248B1 (ko) * | 2011-11-09 | 2015-03-23 | 니혼도꾸슈도교 가부시키가이샤 | 다층 배선기판의 제조방법 |
Families Citing this family (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6896826B2 (en) * | 1997-01-09 | 2005-05-24 | Advanced Technology Materials, Inc. | Aqueous cleaning composition containing copper-specific corrosion inhibitor for cleaning inorganic residues on semiconductor substrate |
JP2003059971A (ja) * | 2001-08-20 | 2003-02-28 | Nec Kansai Ltd | 配線基板及びその製造方法並びに半導体装置 |
JP3910387B2 (ja) * | 2001-08-24 | 2007-04-25 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法並びに半導体装置 |
JP4082995B2 (ja) * | 2001-11-30 | 2008-04-30 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
JP2003188541A (ja) * | 2001-12-19 | 2003-07-04 | Kyocera Corp | 配線基板の製造方法 |
US9691635B1 (en) | 2002-05-01 | 2017-06-27 | Amkor Technology, Inc. | Buildup dielectric layer having metallization pattern semiconductor package fabrication method |
US7548430B1 (en) | 2002-05-01 | 2009-06-16 | Amkor Technology, Inc. | Buildup dielectric and metallization process and semiconductor package |
JP2004186265A (ja) * | 2002-11-29 | 2004-07-02 | Ngk Spark Plug Co Ltd | 多層配線基板の製造方法 |
US6787443B1 (en) * | 2003-05-20 | 2004-09-07 | Intel Corporation | PCB design and method for providing vented blind vias |
US20060278430A1 (en) * | 2003-07-08 | 2006-12-14 | Viasystems Group, Inc. | Method for manufacturing a midplane |
US6972382B2 (en) * | 2003-07-24 | 2005-12-06 | Motorola, Inc. | Inverted microvia structure and method of manufacture |
JP4549695B2 (ja) * | 2003-08-08 | 2010-09-22 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
TWI227502B (en) * | 2003-09-02 | 2005-02-01 | Ind Tech Res Inst | Precise multi-pole magnetic components and manufacturing method thereof |
JP2005129904A (ja) * | 2003-09-29 | 2005-05-19 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
KR100582079B1 (ko) * | 2003-11-06 | 2006-05-23 | 엘지전자 주식회사 | 인쇄회로기판 및 그 제조방법 |
JP4541763B2 (ja) * | 2004-01-19 | 2010-09-08 | 新光電気工業株式会社 | 回路基板の製造方法 |
US7384531B1 (en) | 2004-02-19 | 2008-06-10 | Hutchinson Technology Incorporated | Plated ground features for integrated lead suspensions |
JP4549694B2 (ja) * | 2004-02-27 | 2010-09-22 | 日本特殊陶業株式会社 | 配線基板の製造方法及び多数個取り基板 |
JP4549692B2 (ja) * | 2004-02-27 | 2010-09-22 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
JP4549691B2 (ja) * | 2004-02-27 | 2010-09-22 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
JP4549693B2 (ja) * | 2004-02-27 | 2010-09-22 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
TWI347151B (en) * | 2004-03-19 | 2011-08-11 | Panasonic Corp | Flexible substrate having interlaminar junctions, and process for producing the same |
US10811277B2 (en) | 2004-03-23 | 2020-10-20 | Amkor Technology, Inc. | Encapsulated semiconductor package |
US11081370B2 (en) | 2004-03-23 | 2021-08-03 | Amkor Technology Singapore Holding Pte. Ltd. | Methods of manufacturing an encapsulated semiconductor device |
JP4170266B2 (ja) * | 2004-07-02 | 2008-10-22 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
JP2007096337A (ja) * | 2004-07-07 | 2007-04-12 | Nec Corp | 半導体搭載用配線基板、半導体パッケージ、及びその製造方法 |
JP2006049660A (ja) * | 2004-08-06 | 2006-02-16 | Cmk Corp | プリント配線板の製造方法 |
JP2006086358A (ja) * | 2004-09-16 | 2006-03-30 | Sumitomo Electric Printed Circuit Inc | 両面プリント配線板の製造方法 |
KR100688744B1 (ko) * | 2004-11-15 | 2007-02-28 | 삼성전기주식회사 | 고밀도 인쇄회로기판 및 이의 제조방법 |
KR100674319B1 (ko) * | 2004-12-02 | 2007-01-24 | 삼성전기주식회사 | 얇은 코어층을 갖는 인쇄회로기판 제조방법 |
KR100601485B1 (ko) * | 2004-12-30 | 2006-07-18 | 삼성전기주식회사 | Bga 패키지 기판 및 그 제조방법 |
US20060204685A1 (en) * | 2005-03-11 | 2006-09-14 | Eastman Kodak Company | Inkjet media comprising mixture of fusible reactive polymer particles |
CN1873935B (zh) * | 2005-05-31 | 2010-06-16 | 新光电气工业株式会社 | 配线基板的制造方法及半导体器件的制造方法 |
SG149040A1 (en) * | 2005-06-22 | 2009-01-29 | 3M Innovative Properties Co | Dielectric substrate with holes and method of manufacture |
KR100761706B1 (ko) * | 2006-09-06 | 2007-09-28 | 삼성전기주식회사 | 인쇄회로기판 제조방법 |
US7807215B2 (en) | 2006-09-21 | 2010-10-05 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing copper-clad laminate for VOP application |
JP2008078487A (ja) * | 2006-09-22 | 2008-04-03 | Samsung Electro Mech Co Ltd | Vop用銅張積層板の製造方法 |
US7875804B1 (en) | 2006-09-27 | 2011-01-25 | Hutchinson Technology Incorporated | Plated ground features for integrated lead suspensions |
US8440916B2 (en) * | 2007-06-28 | 2013-05-14 | Intel Corporation | Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method |
JP2009021435A (ja) * | 2007-07-12 | 2009-01-29 | Sony Chemical & Information Device Corp | 配線基板の製造方法 |
JP4635033B2 (ja) * | 2007-08-21 | 2011-02-16 | 新光電気工業株式会社 | 配線基板の製造方法及び電子部品実装構造体の製造方法 |
JP4825784B2 (ja) * | 2007-12-13 | 2011-11-30 | 新光電気工業株式会社 | 半導体装置用パッケージおよびその製造方法 |
KR101449022B1 (ko) * | 2008-02-29 | 2014-10-08 | 엘지이노텍 주식회사 | 인쇄회로기판 및 이의 제조방법 |
TWI519222B (zh) * | 2008-02-29 | 2016-01-21 | Lg伊諾特股份有限公司 | 印刷電路板及其製造方法 |
JP5078683B2 (ja) * | 2008-03-11 | 2012-11-21 | パナソニック株式会社 | プリント基板、及び表面実装デバイスの実装構造体 |
US10051743B2 (en) | 2008-04-04 | 2018-08-14 | Hitachi Chemical Company, Ltd. | Two-layered laminate having metal foil cladded on its one surface, method for production of the laminate, single-sided printed wiring board, and method for production of the wiring board |
US8110752B2 (en) * | 2008-04-08 | 2012-02-07 | Ibiden Co., Ltd. | Wiring substrate and method for manufacturing the same |
KR100990588B1 (ko) * | 2008-05-27 | 2010-10-29 | 삼성전기주식회사 | 랜드리스 비아를 갖는 인쇄회로기판 및 그 제조방법 |
JP5057339B2 (ja) * | 2008-07-31 | 2012-10-24 | 京セラSlcテクノロジー株式会社 | 配線基板の製造方法 |
US8104171B2 (en) * | 2008-08-27 | 2012-01-31 | Advanced Semiconductor Engineering, Inc. | Method of fabricating multi-layered substrate |
TWI372454B (en) * | 2008-12-09 | 2012-09-11 | Advanced Semiconductor Eng | Quad flat non-leaded package and manufacturing method thereof |
KR101095211B1 (ko) | 2008-12-17 | 2011-12-16 | 삼성전기주식회사 | 기판 제조용 캐리어 부재 및 이를 이용한 기판 제조방법 |
US8592691B2 (en) * | 2009-02-27 | 2013-11-26 | Ibiden Co., Ltd. | Printed wiring board |
JP2010239010A (ja) * | 2009-03-31 | 2010-10-21 | Elna Co Ltd | プリント配線板の製造方法およびプリント配線板 |
EP2416355B1 (en) * | 2009-04-02 | 2016-12-21 | Murata Manufacturing Co., Ltd. | Circuit board |
KR101055495B1 (ko) * | 2009-04-14 | 2011-08-08 | 삼성전기주식회사 | 기판 제조용 캐리어 부재 및 이를 이용한 기판 제조방법 |
US8529991B2 (en) * | 2009-07-31 | 2013-09-10 | Raytheon Canada Limited | Method and apparatus for cutting a part without damaging a coating thereon |
KR101043540B1 (ko) * | 2009-10-01 | 2011-06-21 | 삼성전기주식회사 | 인쇄회로기판의 제조방법 |
US20110114372A1 (en) * | 2009-10-30 | 2011-05-19 | Ibiden Co., Ltd. | Printed wiring board |
US8067266B2 (en) * | 2009-12-23 | 2011-11-29 | Intel Corporation | Methods for the fabrication of microelectronic device substrates by attaching two cores together during fabrication |
CN102194703A (zh) * | 2010-03-16 | 2011-09-21 | 旭德科技股份有限公司 | 线路基板及其制作方法 |
US20110253439A1 (en) * | 2010-04-20 | 2011-10-20 | Subtron Technology Co. Ltd. | Circuit substrate and manufacturing method thereof |
KR101796116B1 (ko) | 2010-10-20 | 2017-11-10 | 삼성전자 주식회사 | 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법 |
TWI431742B (zh) * | 2011-04-27 | 2014-03-21 | Unimicron Technology Corp | 線路板製造方法及基層線路板 |
CN102858092A (zh) * | 2011-06-27 | 2013-01-02 | 富葵精密组件(深圳)有限公司 | 电路板及其制作方法 |
WO2013005451A1 (ja) * | 2011-07-06 | 2013-01-10 | 株式会社 豊田自動織機 | 多層配線板および多層配線板の製造方法 |
US9230899B2 (en) * | 2011-09-30 | 2016-01-05 | Unimicron Technology Corporation | Packaging substrate having a holder, method of fabricating the packaging substrate, package structure having a holder, and method of fabricating the package structure |
TWI419627B (zh) * | 2011-10-12 | 2013-12-11 | Subtron Technology Co Ltd | 線路板結構及其製作方法 |
TWI442482B (zh) * | 2011-10-17 | 2014-06-21 | Advance Materials Corp | 封裝基板之製法 |
US9040837B2 (en) * | 2011-12-14 | 2015-05-26 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
US9532466B2 (en) | 2011-12-22 | 2016-12-27 | Haesung Ds Co., Ltd. | Method of manufacturing multi-layer circuit board and multi-layer circuit board manufactured by using the method |
CN103208429B (zh) * | 2012-01-12 | 2015-11-18 | 联致科技股份有限公司 | 封装基板的制法 |
JP5413693B2 (ja) * | 2012-02-06 | 2014-02-12 | 日立化成株式会社 | 回路形成用支持基板、及び半導体素子搭載用パッケージ基板の製造方法 |
JP2013187255A (ja) * | 2012-03-06 | 2013-09-19 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
JP6054080B2 (ja) * | 2012-07-20 | 2016-12-27 | 新光電気工業株式会社 | 支持体及びその製造方法、配線基板の製造方法、電子部品装置の製造方法、配線構造体 |
JP5432354B2 (ja) * | 2012-10-26 | 2014-03-05 | 新光電気工業株式会社 | 配線基板製造用の仮基板及びその製造方法 |
KR101375368B1 (ko) | 2012-12-27 | 2014-03-19 | 주식회사 심텍 | 미세 접속 패턴층을 구비하는 인쇄회로기판 및 이의 제조 방법 |
JP6144058B2 (ja) * | 2013-01-31 | 2017-06-07 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
JP2014220330A (ja) * | 2013-05-07 | 2014-11-20 | 日立金属株式会社 | 光配線基板、光配線基板の製造方法、及び光モジュール |
CN104284530B (zh) * | 2013-07-11 | 2018-08-17 | 上海美维科技有限公司 | 无芯板工艺制作印制电路板的方法 |
CN204014250U (zh) * | 2014-05-16 | 2014-12-10 | 奥特斯(中国)有限公司 | 用于生产电子元件的连接***的半成品 |
CN105307424A (zh) * | 2014-06-23 | 2016-02-03 | 欣兴电子股份有限公司 | 多层软性线路结构的制作方法 |
US20160073505A1 (en) * | 2014-09-05 | 2016-03-10 | Unimicron Technology Corp. | Manufacturing method of multilayer flexible circuit structure |
CN105792546A (zh) * | 2014-12-22 | 2016-07-20 | 北大方正集团有限公司 | 一种多层互连板的制作方法及多层互连pcb板 |
US10237983B2 (en) | 2014-12-23 | 2019-03-19 | Sanmina Corporation | Method for forming hole plug |
JP2016127068A (ja) * | 2014-12-26 | 2016-07-11 | 富士通株式会社 | 配線基板とその製造方法 |
TWI571994B (zh) * | 2015-06-30 | 2017-02-21 | 旭德科技股份有限公司 | 封裝基板及其製作方法 |
WO2017085849A1 (ja) * | 2015-11-19 | 2017-05-26 | 三井金属鉱業株式会社 | 誘電体層を有するプリント配線板の製造方法 |
US10679722B2 (en) | 2016-08-26 | 2020-06-09 | Sandisk Technologies Llc | Storage system with several integrated components and method for use therewith |
CN108156748A (zh) * | 2017-12-29 | 2018-06-12 | 加弘科技咨询(上海)有限公司 | 印制电路板双面贴装时的信号线扇出方法及印制电路板 |
CN110278657B (zh) * | 2018-03-16 | 2022-05-27 | 宏启胜精密电子(秦皇岛)有限公司 | 复合电路板及其制造方法 |
CN112789368A (zh) | 2018-06-21 | 2021-05-11 | 艾瑞科公司 | 图案化无电镀金属 |
CN110972413B (zh) * | 2018-09-29 | 2023-05-26 | 宏启胜精密电子(秦皇岛)有限公司 | 复合电路板及其制作方法 |
US10624213B1 (en) * | 2018-12-20 | 2020-04-14 | Intel Corporation | Asymmetric electronic substrate and method of manufacture |
CN112867243A (zh) * | 2021-01-06 | 2021-05-28 | 英韧科技(上海)有限公司 | 多层电路板 |
TWI795959B (zh) * | 2021-04-23 | 2023-03-11 | 強茂股份有限公司 | 表面黏著式功率半導體封裝元件及其製法 |
CN113597118B (zh) * | 2021-09-28 | 2021-12-31 | 深圳和美精艺半导体科技股份有限公司 | 一种无电镀导线镀金工艺方法 |
KR102629708B1 (ko) | 2023-07-31 | 2024-01-29 | 아주전자(주) | 인쇄회로기판의 마운트홀 형성방법 |
KR102629710B1 (ko) | 2023-07-31 | 2024-01-29 | 아주전자(주) | 인쇄회로기판의 캐비티 형성방법 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4963697A (en) * | 1988-02-12 | 1990-10-16 | Texas Instruments Incorporated | Advanced polymers on metal printed wiring board |
US5315072A (en) * | 1992-01-27 | 1994-05-24 | Hitachi Seiko, Ltd. | Printed wiring board having blind holes |
US5473120A (en) * | 1992-04-27 | 1995-12-05 | Tokuyama Corporation | Multilayer board and fabrication method thereof |
US5495665A (en) * | 1994-11-04 | 1996-03-05 | International Business Machines Corporation | Process for providing a landless via connection |
US5509200A (en) * | 1994-11-21 | 1996-04-23 | International Business Machines Corporation | Method of making laminar stackable circuit board structure |
US5487218A (en) * | 1994-11-21 | 1996-01-30 | International Business Machines Corporation | Method for making printed circuit boards with selectivity filled plated through holes |
US5699613A (en) * | 1995-09-25 | 1997-12-23 | International Business Machines Corporation | Fine dimension stacked vias for a multiple layer circuit board structure |
JPH1027952A (ja) * | 1996-07-09 | 1998-01-27 | Sharp Corp | プリント配線板及びその製造方法 |
JP3633252B2 (ja) * | 1997-01-10 | 2005-03-30 | イビデン株式会社 | プリント配線板及びその製造方法 |
JP2937933B2 (ja) * | 1997-03-24 | 1999-08-23 | 富山日本電気株式会社 | 多層プリント配線板の製造方法 |
JP3986608B2 (ja) | 1997-04-08 | 2007-10-03 | 株式会社デンソー | ボールグリッドアレイパッケージ形半導体部品の実装構造 |
EP1895589A3 (en) * | 1997-10-17 | 2013-04-03 | Ibiden Co., Ltd. | Semiconductor package substrate |
JPH11177237A (ja) * | 1997-12-16 | 1999-07-02 | Hitachi Chem Co Ltd | ビルドアップ多層プリント配線板とその製造方法 |
JPH11204938A (ja) * | 1998-01-09 | 1999-07-30 | Hitachi Aic Inc | 薄物多層プリント配線板の製造方法 |
JP3437453B2 (ja) * | 1998-07-06 | 2003-08-18 | イビデン株式会社 | Icチップ実装用プリント配線板およびその製造方法 |
JP2000058990A (ja) * | 1998-08-06 | 2000-02-25 | Hitachi Metals Ltd | プリント基板およびビルドアップ基板ならびに半導体装置 |
JP2000068650A (ja) * | 1998-08-24 | 2000-03-03 | Ibiden Co Ltd | 多層プリント配線板 |
JP4127433B2 (ja) * | 1998-09-17 | 2008-07-30 | イビデン株式会社 | 多層ビルドアップ配線板及び多層ビルドアップ配線板の製造方法 |
US6214445B1 (en) * | 1998-12-25 | 2001-04-10 | Ngk Spark Plug Co., Ltd. | Printed wiring board, core substrate, and method for fabricating the core substrate |
US6291779B1 (en) * | 1999-06-30 | 2001-09-18 | International Business Machines Corporation | Fine pitch circuitization with filled plated through holes |
US6373717B1 (en) * | 1999-07-02 | 2002-04-16 | International Business Machines Corporation | Electronic package with high density interconnect layer |
US6452117B2 (en) * | 1999-08-26 | 2002-09-17 | International Business Machines Corporation | Method for filling high aspect ratio via holes in electronic substrates and the resulting holes |
-
2000
- 2000-04-11 KR KR20000019037A patent/KR100333627B1/ko active IP Right Grant
-
2001
- 2001-03-29 JP JP2001096366A patent/JP5000809B2/ja not_active Expired - Fee Related
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101505248B1 (ko) * | 2011-11-09 | 2015-03-23 | 니혼도꾸슈도교 가부시키가이샤 | 다층 배선기판의 제조방법 |
CN102883538A (zh) * | 2012-10-16 | 2013-01-16 | 田茂福 | Fpc自动成型机 |
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US6884945B2 (en) | 2005-04-26 |
KR100333627B1 (ko) | 2002-04-22 |
US6580036B2 (en) | 2003-06-17 |
US20030168255A1 (en) | 2003-09-11 |
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