KR100990588B1 - 랜드리스 비아를 갖는 인쇄회로기판 및 그 제조방법 - Google Patents
랜드리스 비아를 갖는 인쇄회로기판 및 그 제조방법 Download PDFInfo
- Publication number
- KR100990588B1 KR100990588B1 KR1020080049277A KR20080049277A KR100990588B1 KR 100990588 B1 KR100990588 B1 KR 100990588B1 KR 1020080049277 A KR1020080049277 A KR 1020080049277A KR 20080049277 A KR20080049277 A KR 20080049277A KR 100990588 B1 KR100990588 B1 KR 100990588B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- copper foil
- foil layer
- printed circuit
- circuit board
- Prior art date
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09545—Plated through-holes or blind vias without lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
- H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
Claims (6)
- 삭제
- 삭제
- (A) 일면에 제1 동박층이 형성되고 타면에 제2 동박층이 형성된 절연층을 갖는 양면기판을 제공하는 단계;(B) 상기 제2 동박층 및 상기 절연층을 관통하는 비아홀을 형성하는 단계;(C) 상기 비아홀의 내벽에 도금층을 형성하는 단계;(D) 상기 양면기판에 비아, 상기 비아의 직경이 최소인 면에 형성되는 상기 비아의 최소직경보다 작은 라인폭을 가지는 회로패턴을 포함하는 제1 회로층, 및 하부랜드를 포함하는 제2 회로층을 형성하는 단계;를 포함하고,상기 제1 동박층은 상기 절연층 상에 적층된 하부 동박층 및 상기 하부 동박층 상에 적층된 상부 동박층으로 이루어지고, 상기 하부 동박층 및 상기 상부 동박층은 이형재로 부착된 랜드리스 비아를 갖는 인쇄회로기판의 제조방법.
- 삭제
- 제3항에 있어서,상기 (D) 단계는 어디티브 공법으로 수행되는 랜드리스 비아를 갖는 인쇄회로기판의 제조방법.
- 제3항에 있어서,상기 회로층을 형성하는 단계는,(ⅰ) 상기 상부 동박층을 제거하는 단계;(ⅱ) 상기 하부 동박층 상에 제1 레지스트층을 적층하고, 상기 제2 동박층 상에 제2 레지스트층을 적층하는 단계;(ⅲ) 상기 제1 레지스트층은 상기 비아의 직경보다 작은 폭을 가지는 회로패턴 포함하는 제1 회로층 형성용 개구부를 갖고, 상기 제2 레지스트층은 하부랜드를 포함하는 제2 회로층 형성용 개구부를 갖도록 패터닝하는 단계;(ⅳ) 상기 개구부를 금속 도금하고 잔류한 제1 및 제2 레지스트층을 제거하는 단계;를 포함하는 랜드리스 비아를 갖는 인쇄회로기판의 제조방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080049277A KR100990588B1 (ko) | 2008-05-27 | 2008-05-27 | 랜드리스 비아를 갖는 인쇄회로기판 및 그 제조방법 |
US12/219,079 US20090294164A1 (en) | 2008-05-27 | 2008-07-15 | Printed circuit board including landless via and method of manufacturing the same |
US13/301,063 US20120066902A1 (en) | 2008-05-27 | 2011-11-21 | Method of manufacturing printed circuit board including landless via |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080049277A KR100990588B1 (ko) | 2008-05-27 | 2008-05-27 | 랜드리스 비아를 갖는 인쇄회로기판 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20090123284A KR20090123284A (ko) | 2009-12-02 |
KR100990588B1 true KR100990588B1 (ko) | 2010-10-29 |
Family
ID=41378370
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020080049277A KR100990588B1 (ko) | 2008-05-27 | 2008-05-27 | 랜드리스 비아를 갖는 인쇄회로기판 및 그 제조방법 |
Country Status (2)
Country | Link |
---|---|
US (2) | US20090294164A1 (ko) |
KR (1) | KR100990588B1 (ko) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9793199B2 (en) * | 2009-12-18 | 2017-10-17 | Ati Technologies Ulc | Circuit board with via trace connection and method of making the same |
US20120090883A1 (en) * | 2010-10-13 | 2012-04-19 | Qualcomm Incorporated | Method and Apparatus for Improving Substrate Warpage |
KR101287742B1 (ko) * | 2011-11-23 | 2013-07-18 | 삼성전기주식회사 | 인쇄 회로 기판 및 그 제조 방법 |
KR101597996B1 (ko) * | 2014-05-22 | 2016-02-29 | 대덕전자 주식회사 | 회로기판 및 제조방법 |
KR102356809B1 (ko) * | 2014-12-26 | 2022-01-28 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US10334728B2 (en) | 2016-02-09 | 2019-06-25 | Advanced Semiconductor Engineering, Inc. | Reduced-dimension via-land structure and method of making the same |
US10950531B2 (en) * | 2019-05-30 | 2021-03-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
KR20210047528A (ko) * | 2019-10-22 | 2021-04-30 | 엘지이노텍 주식회사 | 인쇄회로기판 및 이의 제조 방법 |
CN113286413A (zh) * | 2021-04-01 | 2021-08-20 | 珠海精路电子有限公司 | 散热电路板及其制造工艺 |
CN113950203B (zh) * | 2021-12-20 | 2022-03-11 | 广东科翔电子科技股份有限公司 | 一种高精密Mini-LED PCB的孔中盘制作方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002359464A (ja) | 2001-05-31 | 2002-12-13 | Murata Mfg Co Ltd | 配線基板の製造方法 |
JP2004228349A (ja) | 2003-01-23 | 2004-08-12 | Matsushita Electric Ind Co Ltd | 多層プリント配線板の製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3356786A (en) * | 1964-10-07 | 1967-12-05 | Texas Instruments Inc | Modular circuit boards |
US4159222A (en) * | 1977-01-11 | 1979-06-26 | Pactel Corporation | Method of manufacturing high density fine line printed circuitry |
US5097593A (en) * | 1988-12-16 | 1992-03-24 | International Business Machines Corporation | Method of forming a hybrid printed circuit board |
KR100333627B1 (ko) * | 2000-04-11 | 2002-04-22 | 구자홍 | 다층 인쇄회로기판 및 그 제조방법 |
JP4203435B2 (ja) * | 2003-05-16 | 2009-01-07 | 日本特殊陶業株式会社 | 多層樹脂配線基板 |
JP2007096185A (ja) * | 2005-09-30 | 2007-04-12 | Sanyo Electric Co Ltd | 回路基板 |
TWI335785B (en) * | 2006-10-19 | 2011-01-01 | Unimicron Technology Corp | Circuit board structure and fabrication method thereof |
TWI468093B (zh) * | 2008-10-31 | 2015-01-01 | Princo Corp | 多層基板之導孔結構及其製造方法 |
-
2008
- 2008-05-27 KR KR1020080049277A patent/KR100990588B1/ko active IP Right Grant
- 2008-07-15 US US12/219,079 patent/US20090294164A1/en not_active Abandoned
-
2011
- 2011-11-21 US US13/301,063 patent/US20120066902A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002359464A (ja) | 2001-05-31 | 2002-12-13 | Murata Mfg Co Ltd | 配線基板の製造方法 |
JP2004228349A (ja) | 2003-01-23 | 2004-08-12 | Matsushita Electric Ind Co Ltd | 多層プリント配線板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20120066902A1 (en) | 2012-03-22 |
US20090294164A1 (en) | 2009-12-03 |
KR20090123284A (ko) | 2009-12-02 |
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