KR101773260B1 - 리드 프레임의 제조 방법 - Google Patents

리드 프레임의 제조 방법 Download PDF

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Publication number
KR101773260B1
KR101773260B1 KR1020150169367A KR20150169367A KR101773260B1 KR 101773260 B1 KR101773260 B1 KR 101773260B1 KR 1020150169367 A KR1020150169367 A KR 1020150169367A KR 20150169367 A KR20150169367 A KR 20150169367A KR 101773260 B1 KR101773260 B1 KR 101773260B1
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KR
South Korea
Prior art keywords
etching
mask
lead frame
pattern
metal plate
Prior art date
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KR1020150169367A
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English (en)
Korean (ko)
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KR20160065763A (ko
Inventor
도시히로 다카하시
Original Assignee
에스에이치 메테리얼스 코퍼레이션 리미티드
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Publication of KR20160065763A publication Critical patent/KR20160065763A/ko
Application granted granted Critical
Publication of KR101773260B1 publication Critical patent/KR101773260B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • ing And Chemical Polishing (AREA)
KR1020150169367A 2014-12-01 2015-11-30 리드 프레임의 제조 방법 KR101773260B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2014-242864 2014-12-01
JP2014242864A JP6362111B2 (ja) 2014-12-01 2014-12-01 リードフレームの製造方法

Publications (2)

Publication Number Publication Date
KR20160065763A KR20160065763A (ko) 2016-06-09
KR101773260B1 true KR101773260B1 (ko) 2017-08-31

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KR1020150169367A KR101773260B1 (ko) 2014-12-01 2015-11-30 리드 프레임의 제조 방법

Country Status (4)

Country Link
JP (1) JP6362111B2 (ja)
KR (1) KR101773260B1 (ja)
CN (1) CN105655259B (ja)
TW (1) TWI600131B (ja)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6259139B1 (ja) * 2017-03-24 2018-01-10 シチズンファインデバイス株式会社 板状部材、部材、矩形状片、部材製造方法および流体噴射オリフィスプレートの製造方法
JP6724851B2 (ja) * 2017-04-14 2020-07-15 株式会社デンソー 基材、それを用いたモールドパーケージ、基材の製造方法、およびモールドパッケージの製造方法
JP7353794B2 (ja) 2019-05-13 2023-10-02 ローム株式会社 半導体装置、その製造方法、及びモジュール
TW202129077A (zh) * 2019-10-11 2021-08-01 日商聯合精密科技股份有限公司 金屬加工部件及其製造方法、具備該金屬加工部件的部件搭載模組
JP7292776B2 (ja) * 2020-01-30 2023-06-19 大口マテリアル株式会社 リードフレーム
CN113534612B (zh) * 2020-04-17 2023-02-17 中铝洛阳铜加工有限公司 一种检测蚀刻用高精度引线框架材料平整度的快速方法
CN112151489B (zh) * 2020-09-01 2023-06-06 通富微电科技(南通)有限公司 引线框架、引线框架的形成方法及引线框架封装体
JPWO2022113661A1 (ja) * 2020-11-30 2022-06-02
JP7494107B2 (ja) 2020-12-28 2024-06-03 新光電気工業株式会社 リードフレーム、リードフレームの製造方法及び半導体装置
JP7413626B1 (ja) 2023-05-02 2024-01-16 長華科技股▲ふん▼有限公司 リードフレーム及びその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008187045A (ja) * 2007-01-30 2008-08-14 Matsushita Electric Ind Co Ltd 半導体装置用リードフレームとその製造方法、半導体装置
JP2009302209A (ja) * 2008-06-11 2009-12-24 Nec Electronics Corp リードフレーム、半導体装置、リードフレームの製造方法および半導体装置の製造方法
JP2010114451A (ja) * 2009-12-04 2010-05-20 Sumitomo Metal Mining Co Ltd リードフレームの製造方法

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JPH0231844B2 (ja) * 1986-08-18 1990-07-17 Toppan Printing Co Ltd Handotaisochoriidofureemunoseizohoho
JP3077918B2 (ja) * 1991-07-04 2000-08-21 共同印刷株式会社 エッチング方法
JPH11126859A (ja) * 1997-10-23 1999-05-11 Toppan Printing Co Ltd リードフレームの製造方法
JP2000195984A (ja) * 1998-12-24 2000-07-14 Shinko Electric Ind Co Ltd 半導体装置用キャリア基板及びその製造方法及び半導体装置及びその製造方法
JP3879410B2 (ja) * 2001-02-06 2007-02-14 凸版印刷株式会社 リードフレームの製造方法
JP3963655B2 (ja) * 2001-03-22 2007-08-22 三洋電機株式会社 回路装置の製造方法
EP1602749A1 (en) * 2003-01-17 2005-12-07 Toppan Printing Co., Ltd. Metal photo-etching product and production method therefor
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JP5087787B2 (ja) * 2008-02-12 2012-12-05 住友金属鉱山株式会社 部分めっきリードフレームの製造方法
JP2010010634A (ja) * 2008-06-30 2010-01-14 Shinko Electric Ind Co Ltd リードフレーム及び半導体装置の製造方法
TW201250964A (en) * 2011-01-27 2012-12-16 Dainippon Printing Co Ltd Resin-attached lead frame, method for manufacturing same, and lead frame
JP5813335B2 (ja) * 2011-02-08 2015-11-17 新光電気工業株式会社 リードフレーム、半導体装置、リードフレームの製造方法及び半導体装置の製造方法
JP6052734B2 (ja) * 2013-03-18 2016-12-27 Shマテリアル株式会社 半導体素子搭載用リードフレーム及びその製造方法
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Publication number Priority date Publication date Assignee Title
JP2008187045A (ja) * 2007-01-30 2008-08-14 Matsushita Electric Ind Co Ltd 半導体装置用リードフレームとその製造方法、半導体装置
JP2009302209A (ja) * 2008-06-11 2009-12-24 Nec Electronics Corp リードフレーム、半導体装置、リードフレームの製造方法および半導体装置の製造方法
JP2010114451A (ja) * 2009-12-04 2010-05-20 Sumitomo Metal Mining Co Ltd リードフレームの製造方法

Also Published As

Publication number Publication date
TWI600131B (zh) 2017-09-21
TW201631725A (zh) 2016-09-01
JP6362111B2 (ja) 2018-07-25
CN105655259A (zh) 2016-06-08
JP2016105432A (ja) 2016-06-09
KR20160065763A (ko) 2016-06-09
CN105655259B (zh) 2019-01-11

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