JP2012084938A - 半導体装置製造用基板 - Google Patents
半導体装置製造用基板 Download PDFInfo
- Publication number
- JP2012084938A JP2012084938A JP2012022143A JP2012022143A JP2012084938A JP 2012084938 A JP2012084938 A JP 2012084938A JP 2012022143 A JP2012022143 A JP 2012022143A JP 2012022143 A JP2012022143 A JP 2012022143A JP 2012084938 A JP2012084938 A JP 2012084938A
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- Prior art keywords
- semiconductor device
- metal plate
- substrate
- plating layer
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】金属板の表面に複数個の半導体装置用の端子部などをめっき層として形成しており、半導体装置の製造に際しては、複数の半導体素子を搭載してそれらを樹脂封止体で封止した後、前記めっき層を前記樹脂封止体に残して金属板だけが剥離されることになる半導体装置製造用基板であって、前記金属板1には、個々の半導体装置用の前記めっき層2,3が、両面に形成されていることを特徴とする。
【選択図】 図1
Description
2 パッド部
3 端子部
4 半導体素子
5 ボンディングワイヤ
6 樹脂封止体
6a フランジ部
Claims (5)
- 金属板の表面に複数個の半導体装置用の端子部などをめっき層として形成しており、半導体装置の製造に際しては、複数の半導体素子を搭載してそれらを樹脂封止体で封止した後、前記めっき層を前記樹脂封止体に残して金属板だけが剥離されることになる半導体装置製造用基板であって、前記金属板には、個々の半導体装置用の前記めっき層が、両面に形成されていることを特徴とする半導体装置製造用基板。
- 前記金属板は、両面の各々に、個々の半導体装置用の前記めっき層を、複数の領域に分けて各々マトリックス状に形成していることを特徴とする請求項1に記載の半導体装置製造用基板。
- 前記めっき層は、10〜100μmの厚さに形成されていることを特徴とする請求項1又は2に記載の半導体装置製造用基板。
- 前記めっき層は、金めっき層を含む多層のめっき層であることを特徴とする請求項1乃至3のいずれかに記載の半導体装置製造用基板。
- 前記金属板は、ステンレス鋼であることを特徴とする請求項1乃至4のいずれかに記載の半導体装置製造用基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012022143A JP2012084938A (ja) | 2012-02-03 | 2012-02-03 | 半導体装置製造用基板 |
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JP2012022143A JP2012084938A (ja) | 2012-02-03 | 2012-02-03 | 半導体装置製造用基板 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007153558A Division JP5098452B2 (ja) | 2007-06-11 | 2007-06-11 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
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JP2012084938A true JP2012084938A (ja) | 2012-04-26 |
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JP2012022143A Pending JP2012084938A (ja) | 2012-02-03 | 2012-02-03 | 半導体装置製造用基板 |
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JP (1) | JP2012084938A (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001067513A1 (fr) * | 2000-03-09 | 2001-09-13 | Fujitsu Limited | Dispositif a semi-conducteurs, araignee de connexions, et procedes de fabrication correspondants |
JP2002226797A (ja) * | 2001-01-29 | 2002-08-14 | Nitto Denko Corp | 耐熱性粘着テープおよび半導体装置の製造方法 |
JP2006196922A (ja) * | 2000-04-25 | 2006-07-27 | Kyushu Hitachi Maxell Ltd | 半導体装置、その製造方法、及び電着フレーム |
JP2006222164A (ja) * | 2005-02-08 | 2006-08-24 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2007129068A (ja) * | 2005-11-04 | 2007-05-24 | Toshiba Corp | 半導体装置とその製造方法、及びその製造に用いる基板 |
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2012
- 2012-02-03 JP JP2012022143A patent/JP2012084938A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001067513A1 (fr) * | 2000-03-09 | 2001-09-13 | Fujitsu Limited | Dispositif a semi-conducteurs, araignee de connexions, et procedes de fabrication correspondants |
JP2006196922A (ja) * | 2000-04-25 | 2006-07-27 | Kyushu Hitachi Maxell Ltd | 半導体装置、その製造方法、及び電着フレーム |
JP2002226797A (ja) * | 2001-01-29 | 2002-08-14 | Nitto Denko Corp | 耐熱性粘着テープおよび半導体装置の製造方法 |
JP2006222164A (ja) * | 2005-02-08 | 2006-08-24 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2007129068A (ja) * | 2005-11-04 | 2007-05-24 | Toshiba Corp | 半導体装置とその製造方法、及びその製造に用いる基板 |
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