JP6199601B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6199601B2 JP6199601B2 JP2013096477A JP2013096477A JP6199601B2 JP 6199601 B2 JP6199601 B2 JP 6199601B2 JP 2013096477 A JP2013096477 A JP 2013096477A JP 2013096477 A JP2013096477 A JP 2013096477A JP 6199601 B2 JP6199601 B2 JP 6199601B2
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- Prior art keywords
- chip
- wiring board
- semiconductor chip
- semiconductor device
- semiconductor
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Description
図1は実施の形態の半導体装置の構造の一例を示す平面図、図2は図1に示す半導体装置の構造を蓋部材を透過して示す平面図、図3は図1に示すA−A線に沿って切断した構造を示す断面図、図4は図1に示すB−B線に沿って切断した構造を示す断面図、図5は図3に示すC部を拡大して示す部分拡大断面図、図6は図4に示すC部を拡大して示す部分拡大断面図である。また、図7は図1に示す半導体装置の裏面側の構造を示す裏面図、図8は図1に示す半導体装置に搭載されるチップ部品の構造の一例を示す斜視図、図9は図1に示す半導体装置に設けられた蓋部材の構造の一例を示す平面図および側面図である。
1a 上面(第1面)
1aa,1ab 第1辺
1ac,1ad 第2辺
1b 下面(第2面)
1c,1d ランド(端子、電極)
1e 基材
1f ソルダレジスト膜(絶縁膜)
1g 搭載領域
1h 接合代領域
1i マーク
1j,1k 溝(樹脂拡散回避部、凹部)
2 コントロールチップ(第1半導体チップ)
2a 主面(第1主面)
2aa,2ab 長辺
2ac,2ad 短辺
2b 裏面(第1裏面)
2c 電極パッド(電極)
2d 側面
3 メモリチップ(第2半導体チップ)
3a 主面(第2主面)
3aa,3ab 長辺
3ac,3ad 短辺
3b 裏面(第2裏面)
3c 電極パッド(電極)
3d 側面
3e 貫通電極
4 バンプ電極(バンプ、突起電極)
5 BGA(Ball Grid Array 、半導体装置)
6,6a,6b アンダーフィル(樹脂)
7 リッド(蓋部材)
7a,7b 縁部(第1縁部、鍔部)
7c,7d 縁部(第2縁部、鍔部)
7e 曲げ部
7f 天井部
7g 金属めっき
8 ボール電極(外部接続用端子、外部電極端子)
9,9a,9b チップ部品
9c 本体部
9d 端子部(電極部)
10 接着材
11 空間部
12 熱伝導性接着材(導電性樹脂、半田)
13 半田
14 BGA(Ball Grid Array 、半導体装置)
15 メモリチップ
16 BGA(Ball Grid Array 、半導体装置)
17 接着材
18 バンプ
20,21 BGA
22 開口部
23 半田
Claims (15)
- 第1面、前記第1面とは反対側の第2面、第1辺、前記第1辺とは反対側の第2辺、前記第1および第2辺と交差する第3辺、前記第3辺とは反対側の第4辺、および前記第2面に配置された複数のボール電極を有する矩形状の配線基板と、
第1主面、前記第1主面とは反対側の第1裏面、第1長辺、前記第1長辺とは反対側の第2長辺、前記第1および第2長辺と交差する第1短辺、前記第1短辺とは反対側の第2短辺、ならびに前記第1主面上に形成された複数の第1バンプ電極を有し、前記第1主面と前記配線基板の前記第1面が対向するように前記配線基板上に搭載された矩形状の第1半導体チップと、
第2主面、前記第2主面とは反対側の第2裏面、第3長辺、前記第3長辺とは反対側の第4長辺、前記第3および第4長辺と交差する第3短辺、前記第3短辺とは反対側の第4短辺、並びに前記第2主面上に形成された複数の第2バンプ電極を有し、前記第2主面と前記配線基板の前記第1面とが対向するように、前記第1半導体チップと並んで前記配線基板上に搭載された矩形状の第2半導体チップと、
前記配線基板の前記第1面上に配置され、前記第1および第2半導体チップを覆う金属製のリッドと、
を備え、
平面視において、前記第1半導体チップの前記第1長辺と前記第2半導体チップの前記第3長辺とは対向し、かつ前記第1半導体チップの前記第2長辺と前記第2半導体チップの前記第4長辺とは背向して配置されており、
前記第1半導体チップの前記第2長辺は、平面視において前記配線基板の前記第1辺と対向して配置されており、
前記第2半導体チップの前記第4長辺は、平面視において前記配線基板の前記第2辺と対向して配置されており、
前記第1半導体チップの前記第1短辺および前記第2半導体チップの前記第3短辺のそれぞれは、平面視において前記配線基板の前記第3辺と対向して配置されており、
前記第1半導体チップの前記第2短辺および前記第2半導体チップの前記第4短辺のそれぞれは、平面視において前記配線基板の前記第4辺と対向して配置されており、
前記リッドは、平面視において天井部と前記天井部の周りに配置された周縁部および前記天井部と前記周縁部を接続する曲げ部を有しており、
前記天井部と前記周縁部は、断面視において平面状に延在しており、
前記周縁部は、平面視において前記配線基板の前記第1辺に沿って、かつ前記第1辺と前記第1半導体チップの前記第2長辺との間に配置された第1縁部、前記配線基板の前記第2辺に沿って配置され、かつ前記第2辺と前記第2半導体チップの前記第4長辺との間に配置された第2縁部、前記配線基板の前記第3辺に沿って配置され、かつ前記第3辺と前記第1半導体チップの前記第1短辺および前記第2半導体チップの前記第3短辺との間に配置された第3縁部、並びに前記配線基板の前記第4辺に沿って配置され、かつ前記第4辺と前記第1半導体チップの前記第2短辺および前記第2半導体チップの前記第4短辺との間に設置された第4縁部を含み、
平面視において、前記第1縁部の第1幅は、前記配線基板の前記第3辺に沿った第1方向において前記第2縁部の第2幅と、実質的に等しく、
平面視において、前記第3縁部の第3幅は、前記第1方向と垂直に交差する第2方向において前記第4縁部の第4幅と、実質的に等しく、
平面視において、前記第3縁部の前記第3幅は、前記第1縁部の前記第1幅よりも大きく、
前記第3および第4縁部のそれぞれは、断面視において接着材を介して前記配線基板の前記第1面に固定されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記配線基板の前記第1面は、正方形である、半導体装置。 - 請求項2に記載の半導体装置において、
前記配線基板の前記第1面上において、前記リッドの前記第3縁部と前記第1半導体チップの前記第1短辺および前記第2半導体チップの前記第3短辺との間の第1領域に、複数の第1チップ部品が搭載されており、
前記配線基板の前記第1面上において、前記リッドの前記第4縁部と前記第1半導体チップの前記第2短辺および前記第2半導体チップの前記第4短辺との間の第2領域に、複数の第2チップ部品が搭載されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記第2半導体チップは、複数のメモリチップが積層された積層メモリチップであって、
上段のメモリチップは、下段のメモリチップと樹脂系の接着材を介して接合されており、前記下段のメモリチップとは複数の貫通電極および複数のバンプを介して電気的に接続されており、
前記第1半導体チップは、前記積層メモリチップを制御するコントロールチップである、半導体装置。 - 請求項4に記載の半導体装置において、
断面視において、前記リッドの前記第1縁部および前記第2縁部と前記配線基板の前記第1面とは、空間部を介して対向しており、前記空間部に接着剤を介在していない、半導体装置。 - 請求項3に記載の半導体装置において、
断面視において、前記第1半導体チップの前記第1主面および前記第2半導体チップの前記第2主面のそれぞれと、前記配線基板の前記第1面との間に樹脂が充填されている、半導体装置。 - 請求項6に記載の半導体装置において、
平面視において、前記配線基板の前記第1面の前記第1半導体チップの前記第1長辺と前記第2半導体チップの前記第3長辺の間の領域に前記第1長辺に沿って第1溝部が形成されている、半導体装置。 - 請求項7に記載の半導体装置において、
平面視において、前記配線基板の前記第1面の前記第1領域において、前記第1半導体チップの前記第1短辺および前記第2半導体チップの前記第3短辺と前記複数の第1チップ部品との間の領域に、前記配線基板の前記第3辺に沿って第2溝部が形成されており、
平面視において、前記配線基板の前記第1面の前記第2領域において、前記第1半導体チップの前記第2短辺および前記第2半導体チップの前記第4短辺と前記複数の第2チップ部品との間の領域に、前記配線基板の前記第4辺に沿って第3溝部が形成されている、半導体装置。 - 請求項8に記載の半導体装置において、
前記第1、第2および第3溝部の底辺から銅配線の表面が露出している、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1半導体チップの前記第1裏面および前記第2半導体チップの前記第2裏面のそれぞれは、断面視において熱伝導性接着材もしくは半田材を介して前記リッドと接合している、半導体装置。 - 請求項1に記載の半導体装置において、
前記リッドは、表面に金属メッキが施された銅板からなる、半導体装置。 - 請求項3に記載の半導体装置において、
前記配線基板の前記第2面の前記複数のボール電極で囲まれた領域に、平面視において複数の第3チップ部品が設けられている、半導体装置。 - 請求項12に記載の半導体装置において、
前記複数のボール電極それぞれの前記第2面からの高さは、断面視において前記第2面に設けられた前記複数の第3チップ部品の前記第2面からの高さよりも高い、半導体装置。 - 請求項3に記載の半導体装置において、
前記リッドの前記第1面からの高さは、断面視において前記第1面に設けられた前記複数の第1および第2チップ部品の前記第1面からの高さよりも高い、半導体装置。 - 請求項13に記載の半導体装置において、
前記複数の第1、第2、および第3チップ部品のそれぞれは、チップコンデンサである、半導体装置。
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JP2013096477A JP6199601B2 (ja) | 2013-05-01 | 2013-05-01 | 半導体装置 |
US14/254,805 US9460938B2 (en) | 2013-05-01 | 2014-04-16 | Semiconductor device including a plurality of semiconductor chips, and a cover member with first and second brims |
CN201410182740.1A CN104134651B (zh) | 2013-05-01 | 2014-04-30 | 半导体装置 |
HK15102428.1A HK1201989A1 (en) | 2013-05-01 | 2015-03-10 | Semiconductor device |
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CN107534027B (zh) * | 2015-06-15 | 2021-08-17 | 索尼公司 | 半导体装置、电子设备和制造方法 |
JP6591234B2 (ja) * | 2015-08-21 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2017112241A (ja) * | 2015-12-17 | 2017-06-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2017123446A (ja) * | 2016-01-08 | 2017-07-13 | 株式会社日立製作所 | 半導体装置および半導体パッケージ装置 |
US10796976B2 (en) | 2018-10-31 | 2020-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of forming the same |
KR20210022911A (ko) * | 2019-08-21 | 2021-03-04 | 삼성전기주식회사 | 반도체 패키지 |
JP2022081872A (ja) * | 2020-11-20 | 2022-06-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
TW202307717A (zh) * | 2021-08-04 | 2023-02-16 | 義守大學 | 配置三維堆疊晶片間的訊號墊片的方法和電子裝置 |
CN114210597B (zh) * | 2022-02-22 | 2022-04-26 | 深圳市正和兴电子有限公司 | 一种半导体器件的导电胶推荐方法、***和可读存储介质 |
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JP3417608B2 (ja) | 1993-08-03 | 2003-06-16 | 日本特殊陶業株式会社 | 半導体パッケージ用のセラミック製リッド基板 |
JPH0851167A (ja) | 1994-05-31 | 1996-02-20 | Sumitomo Kinzoku Ceramics:Kk | 半導体パッケージ封止用リッドとそのリッドを用いた半導体パッケージおよびそのリッドのα線遮蔽層形成方法 |
JP2861981B2 (ja) * | 1997-04-11 | 1999-02-24 | 日本電気株式会社 | 半導体装置の冷却構造 |
JP3462979B2 (ja) * | 1997-12-01 | 2003-11-05 | 株式会社東芝 | 半導体装置 |
JP3097644B2 (ja) * | 1998-01-06 | 2000-10-10 | 日本電気株式会社 | 半導体装置接続構造及び接続方法 |
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JP3676091B2 (ja) * | 1998-08-10 | 2005-07-27 | 富士通株式会社 | 半導体装置 |
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JP4254669B2 (ja) * | 2004-09-07 | 2009-04-15 | 豊田合成株式会社 | 発光装置 |
US7524701B2 (en) * | 2005-04-20 | 2009-04-28 | International Rectifier Corporation | Chip-scale package |
JP4768314B2 (ja) * | 2005-05-16 | 2011-09-07 | 株式会社東芝 | 半導体装置 |
JP2007042719A (ja) | 2005-08-01 | 2007-02-15 | Nec Electronics Corp | 半導体装置 |
JP2007234988A (ja) * | 2006-03-02 | 2007-09-13 | Epson Toyocom Corp | 半導体素子の実装基板及び実装方法 |
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JP2012054597A (ja) | 2011-11-07 | 2012-03-15 | Renesas Electronics Corp | 半導体装置 |
US20130258610A1 (en) * | 2012-03-29 | 2013-10-03 | Jianguo Li | Semiconductor chip device with vented lid |
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US9460938B2 (en) | 2016-10-04 |
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