JP4627323B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4627323B2 JP4627323B2 JP2008004744A JP2008004744A JP4627323B2 JP 4627323 B2 JP4627323 B2 JP 4627323B2 JP 2008004744 A JP2008004744 A JP 2008004744A JP 2008004744 A JP2008004744 A JP 2008004744A JP 4627323 B2 JP4627323 B2 JP 4627323B2
- Authority
- JP
- Japan
- Prior art keywords
- bga substrate
- semiconductor device
- semiconductor chip
- substrate
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
図1は、本発明の実施の形態1における半導体装置の断面図を示す。図1において、符号1は有機材料を用いたBGA基板、2はBGA基板1上にバンプ3を介してフリップチップ接合された半導体チップ、4は半導体チップ2とBGA基板1との間を充填するアンダーフィル樹脂、7はBGA基板1の上面にリング接着剤5を介して取り付けられたリング、8は半導体チップ2とリング7との上面に、半導体チップ1側はヒートスプレッダ接着剤を介しリング7側はリング接着剤5と同じ接着剤を介して取り付けられたヒートスプレッダ、9はBGA基板1の下面(または裏面)に形成された半田ボール、10はスタックドヴィア(Stacked Via)である。
図2は、本発明の実施の形態2における半導体装置の断面図を示す。図2で図1と同じ符号を付した部分は同じ機能を有するものであるため説明は省略する。図2において、符号11は高誘電率の材料からなる高誘電率層(キャパシタ層)である。
図4は、本発明の実施の形態3における半導体装置の断面図を示す。図4で図1ないし図3と同じ符号を付した部分は同じ機能を有するものであるため説明は省略する。図4において、符号12はBGA基板1の下面に取り付けられたチップコンデンサである。
図5は、本発明の実施の形態4における半導体装置の断面図を示す。図5で図1ないし図4と同じ符号を付した部分は同じ機能を有するものであるため説明は省略する。図5において、符号14はBGA基板1とリング7との間に用いられる高誘電材接着剤である。
図6は、本発明の実施の形態5における半導体装置の断面図を示す。図6で図1ないし図5と同じ符号を付した部分は同じ機能を有するものであるため説明は省略する。図6において、符号15はBGA基板1とリング7との間に用いられる高誘電材接着剤である。
図7は、本発明の実施の形態6における半導体装置の断面図を示す。図7で図1ないし図6と同じ符号を付した部分は同じ機能を有するものであるため説明は省略する。図7において、符号16はパッケージ部1を実装する実装基板である。
Claims (2)
- 有機材料を用いて形成された、多層構造のBGA基板、複数のバンプを介して前記BGA基板の主面に接合された半導体チップ、及び前記主面と対向する前記BGA基板の反対側の面であって、前記半導体チップのエッジ部分に対応する位置に形成され、電源とグランドとを接続するチップコンデンサを備えた半導体装置。
- 有機材料を用いて形成された、多層構造のBGA基板、複数のバンプを介して前記BGA基板の主面に接合された半導体チップ、及び前記主面と対向する前記BGA基板の反対側の面であって、前記半導体チップのエッジ部分に対応する位置に形成され、電源とグランドとを接続するチップコンデンサを備え、
前記BGA基板は、前記多層構造の積層方向に重なるように複数の接続孔が繋ぎ合わされてなるスタックドビアを有し、
前記スタックドビアが形成されるピッチは、前記複数のバンプが形成されるピッチと一致している、半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008004744A JP4627323B2 (ja) | 2008-01-11 | 2008-01-11 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008004744A JP4627323B2 (ja) | 2008-01-11 | 2008-01-11 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11206576A Division JP2001035960A (ja) | 1999-07-21 | 1999-07-21 | 半導体装置および製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008135772A JP2008135772A (ja) | 2008-06-12 |
JP4627323B2 true JP4627323B2 (ja) | 2011-02-09 |
Family
ID=39560338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008004744A Expired - Fee Related JP4627323B2 (ja) | 2008-01-11 | 2008-01-11 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4627323B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6881726B2 (ja) | 2016-06-28 | 2021-06-02 | 株式会社Joled | 実装基板 |
JP6799430B2 (ja) | 2016-10-04 | 2020-12-16 | 株式会社Joled | 半導体装置及び表示装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07283538A (ja) * | 1994-04-14 | 1995-10-27 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
JPH08172252A (ja) * | 1994-12-19 | 1996-07-02 | Kyocera Corp | 回路基板 |
JPH09260537A (ja) * | 1996-03-26 | 1997-10-03 | Sumitomo Kinzoku Electro Device:Kk | フリップチップセラミック基板 |
-
2008
- 2008-01-11 JP JP2008004744A patent/JP4627323B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07283538A (ja) * | 1994-04-14 | 1995-10-27 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
JPH08172252A (ja) * | 1994-12-19 | 1996-07-02 | Kyocera Corp | 回路基板 |
JPH09260537A (ja) * | 1996-03-26 | 1997-10-03 | Sumitomo Kinzoku Electro Device:Kk | フリップチップセラミック基板 |
Also Published As
Publication number | Publication date |
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JP2008135772A (ja) | 2008-06-12 |
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