JP5476689B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 150000004767 nitrides Chemical class 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
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- 238000010438 heat treatment Methods 0.000 description 4
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- 238000007254 oxidation reaction Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
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- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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- 230000001681 protective effect Effects 0.000 description 2
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- 238000000137 annealing Methods 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 1
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- 230000005669 field effect Effects 0.000 description 1
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- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000005121 nitriding Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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Description
図1は、本発明にかかる製造方法により製造される超接合半導体装置の一例を示す断面図である。ここでは、縦型MOSFETを例にして説明する。図1に示すように、低抵抗のn++ドレイン層1の上に、n型半導体領域2とp型半導体領域3を交互に繰り返し接合させてなる並列pn構造4が設けられている。並列pn構造4のp型半導体領域3の表面層には、高不純物濃度のpベース領域5が設けられている。pベース領域5の表面層には、高不純物濃度のn+ソース領域6が設けられている。
実施の形態2にかかる半導体装置の製造方法について説明する。実施の形態2の説明および添付図面について、実施の形態1と重複する説明は省略する。図12〜図14は、実施の形態2にかかる製造方法による半導体装置を示す断面図である。まず、図2および図3に示すように、実施の形態1と同様にして、n型の低抵抗シリコン基板21の表面にn型半導体22を形成し、n型半導体22の表面にマスク酸化膜23およびマスク窒化膜24を形成し、マスク積層膜(マスク酸化膜23およびマスク窒化膜24)を開口する。
実施の形態3にかかる半導体装置の製造方法について説明する。実施の形態3の説明および添付図面について、実施の形態1と重複する説明は省略する。図15〜図24は、実施の形態3にかかる製造方法による半導体装置を示す断面図である。まず、実施の形態1と同様にして、n型の低抵抗シリコン基板(n++基板)21の表面にn型半導体22をエピタキシャル成長させる。次いで、例えばパイロジェニック酸化などの熱酸化法により、n型半導体22の表面にマスク酸化膜29を形成する(図15)。次いで、マスク酸化膜29の表面に図示省略したレジスト膜を塗布する。次いで、フォトリソグラフィおよびエッチングによって、図16に示すように、トレンチ形成領域上の部分のマスク酸化膜29を開口する。そして、レジスト膜を除去する。
22 n型半導体
23 マスク酸化膜
24 マスク窒化膜
25 トレンチ
27 p型半導体
Claims (3)
- 第1導電型半導体基板の主面に、一部が開口する第1のマスクを形成する第1のマスク工程と、
前記第1導電型半導体基板の、前記第1のマスクの開口部分に露出する半導体部分をエッチングしてトレンチを形成するエッチング工程と、
前記第1のマスクの残された部分の表面に、前記第1のマスクよりも狭い幅のレジスト膜からなる第2のマスクを積層し、前記第2のマスクを用いて前記第1のマスクの幅を狭くして、前記第1のマスクの開口部分の幅を広げて、前記第1導電型半導体基板の表面の、前記エッチング工程においてエッチングされずに残った半導体部分を露出する露出工程と、
前記第1導電型半導体基板の、前記露出工程で露出された半導体部分と、前記トレンチとに、第2導電型半導体の層をエピタキシャル成長する層形成工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第1のマスクは、酸化膜、窒化膜、または酸化膜と窒化膜を積層した膜であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記層形成工程において、シリコンソースガスとハロゲン化物ガスの混合ガスを供給したチャンバー内でエピタキシャル成長を行うことを特徴とする請求項1または2に記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2008199793A JP5476689B2 (ja) | 2008-08-01 | 2008-08-01 | 半導体装置の製造方法 |
CN2009101611800A CN101640171B (zh) | 2008-08-01 | 2009-07-31 | 半导体器件制造方法 |
US12/534,502 US7871905B2 (en) | 2008-08-01 | 2009-08-03 | Method for producing semiconductor device |
US12/967,653 US8242023B2 (en) | 2008-08-01 | 2010-12-14 | Method of producing a semiconductor device having a trench filled with an epitaxially grown semiconductor layer |
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JP2008199793A JP5476689B2 (ja) | 2008-08-01 | 2008-08-01 | 半導体装置の製造方法 |
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JP2010040653A JP2010040653A (ja) | 2010-02-18 |
JP5476689B2 true JP5476689B2 (ja) | 2014-04-23 |
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US (2) | US7871905B2 (ja) |
JP (1) | JP5476689B2 (ja) |
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JP5533067B2 (ja) * | 2010-03-15 | 2014-06-25 | 富士電機株式会社 | 超接合半導体装置の製造方法 |
CN102214561A (zh) * | 2010-04-06 | 2011-10-12 | 上海华虹Nec电子有限公司 | 超级结半导体器件及其制造方法 |
CN102403257B (zh) * | 2010-09-14 | 2014-02-26 | 上海华虹宏力半导体制造有限公司 | 改善超级结器件深沟槽刻蚀边界形貌的方法 |
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CN102820212B (zh) * | 2011-06-08 | 2015-08-12 | 无锡华润上华半导体有限公司 | 一种深沟槽超级pn结的形成方法 |
CN102856200A (zh) * | 2011-06-28 | 2013-01-02 | 上海华虹Nec电子有限公司 | 形成超级结mosfet的pn柱层的方法 |
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JP5556851B2 (ja) * | 2011-12-26 | 2014-07-23 | 株式会社デンソー | 半導体装置の製造方法 |
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JP2014060299A (ja) * | 2012-09-18 | 2014-04-03 | Toshiba Corp | 半導体装置 |
CN104576352B (zh) * | 2013-10-16 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | 改善深沟槽化学机械研磨均一性的方法 |
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JP5055687B2 (ja) * | 2004-07-05 | 2012-10-24 | 富士電機株式会社 | 半導体ウエハの製造方法 |
US8003522B2 (en) * | 2007-12-19 | 2011-08-23 | Fairchild Semiconductor Corporation | Method for forming trenches with wide upper portion and narrow lower portion |
KR100988776B1 (ko) * | 2007-12-27 | 2010-10-20 | 주식회사 동부하이텍 | 리세스드 게이트 트랜지스터의 제조 방법 |
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US20110086497A1 (en) | 2011-04-14 |
US8242023B2 (en) | 2012-08-14 |
CN101640171B (zh) | 2013-05-15 |
CN101640171A (zh) | 2010-02-03 |
US7871905B2 (en) | 2011-01-18 |
US20100029070A1 (en) | 2010-02-04 |
JP2010040653A (ja) | 2010-02-18 |
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