CN103094106B - 交替排列的p型和n型半导体薄层的制备方法 - Google Patents
交替排列的p型和n型半导体薄层的制备方法 Download PDFInfo
- Publication number
- CN103094106B CN103094106B CN201110332535.5A CN201110332535A CN103094106B CN 103094106 B CN103094106 B CN 103094106B CN 201110332535 A CN201110332535 A CN 201110332535A CN 103094106 B CN103094106 B CN 103094106B
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- doped dielectric
- semiconductor layer
- alternately arranged
- layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000002347 injection Methods 0.000 claims abstract description 9
- 239000007924 injection Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 15
- 238000000407 epitaxy Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 238000005516 engineering process Methods 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110332535.5A CN103094106B (zh) | 2011-10-28 | 2011-10-28 | 交替排列的p型和n型半导体薄层的制备方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110332535.5A CN103094106B (zh) | 2011-10-28 | 2011-10-28 | 交替排列的p型和n型半导体薄层的制备方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103094106A CN103094106A (zh) | 2013-05-08 |
CN103094106B true CN103094106B (zh) | 2015-12-02 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201110332535.5A Active CN103094106B (zh) | 2011-10-28 | 2011-10-28 | 交替排列的p型和n型半导体薄层的制备方法 |
Country Status (1)
Country | Link |
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CN (1) | CN103094106B (zh) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1557022A (zh) * | 2001-09-19 | 2004-12-22 | 株式会社东芝 | 半导体装置及其制造方法 |
CN101996868A (zh) * | 2009-08-27 | 2011-03-30 | 上海华虹Nec电子有限公司 | 交替排列的p型和n型半导体薄层的形成方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5476689B2 (ja) * | 2008-08-01 | 2014-04-23 | 富士電機株式会社 | 半導体装置の製造方法 |
-
2011
- 2011-10-28 CN CN201110332535.5A patent/CN103094106B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1557022A (zh) * | 2001-09-19 | 2004-12-22 | 株式会社东芝 | 半导体装置及其制造方法 |
CN101996868A (zh) * | 2009-08-27 | 2011-03-30 | 上海华虹Nec电子有限公司 | 交替排列的p型和n型半导体薄层的形成方法 |
Also Published As
Publication number | Publication date |
---|---|
CN103094106A (zh) | 2013-05-08 |
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Date | Code | Title | Description |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140107 |
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C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
TA01 | Transfer of patent application right |
Effective date of registration: 20140107 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant |