JP4068597B2 - 半導体装置 - Google Patents
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- JP4068597B2 JP4068597B2 JP2004201943A JP2004201943A JP4068597B2 JP 4068597 B2 JP4068597 B2 JP 4068597B2 JP 2004201943 A JP2004201943 A JP 2004201943A JP 2004201943 A JP2004201943 A JP 2004201943A JP 4068597 B2 JP4068597 B2 JP 4068597B2
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- 239000004065 semiconductor Substances 0.000 title claims description 265
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Description
[第1実施形態]
(半導体装置の構造)
(半導体装置の動作)
(半導体装置の製造方法)
(第1実施形態の主な効果)
(変形例)
[第2実施形態]
なお、各実施形態を説明する図において、既に説明した図の符号で示すものと同一のものについては、同一符号を付すことにより説明を省略する。
第1実施形態に係る半導体装置の主な特徴は、トレンチの底面上に絶縁領域が形成された状態で、トレンチにp型のエピタキシャル成長層を埋め込むことにより形成された第2半導体領域をスーパージャンクション構造の構成要素にした点である。
図1は、第1実施形態に係る半導体装置1の部分断面図である。半導体装置1は、多数のMOSFETセル3が並列接続された構造を有する縦型のパワーMOSFETである。半導体装置1は、n+型の半導体基板(例えばシリコン基板)5と、その表面7上に配置されたn型の複数の第1半導体領域9及びp型の複数の第2半導体領域11と、を備える。n型は第1導電型の一例であり、p型は第2導電型の一例である。
半導体装置1の動作について図1を用いて説明する。この動作において、各MOSFETセル3のソース領域21及びベース領域19は接地されている。また、ドレイン領域である半導体基板5には、ドレイン電極37を介して所定の正電圧が印加されている。
第1実施形態に係る半導体装置1の製造方法について、図1〜図10を用いて説明する。図2〜図10は、図1に示す半導体装置1の製造方法を工程順に示す断面図である。
第1実施形態の主な効果として、次の効果1と効果2がある。
図1に示す第1実施形態に係る半導体装置1によれば、リーク電流を低減することができる。この効果について比較形態と比較しながら説明する。図11及び図12は比較形態に係る第2半導体領域11の形成工程を示す断面図である。
第1実施形態に係る半導体装置1によれば、第1半導体領域9中のn型不純物の電荷量と第2半導体領域11中のp型不純物の電荷量とのバランスのずれの許容範囲を大きくすることができるため、半導体装置1の歩留まりを良くすることができる。以下、これについて詳細に説明する。
第1実施形態には変形例1〜4がある。
第1実施形態の変形例1は、図1に示す半導体装置1において、第2半導体領域11中のp型不純物の電荷量を、第1半導体領域9中のn型不純物の電荷量よりも大きくした点を特徴とする。ここで、領域11中のp型不純物の電荷量は、領域11の幅とその領域中のp型の不純物濃度との積で表され、領域9中のn型不純物の電荷量は、領域9の幅とその領域中のn型の不純物濃度との積で表される。第1実施形態の効果2の説明に用いた図16により、変形例1の効果を説明する。
図17は、変形例2に係る半導体装置59の断面図であり、図1と対応する。半導体装置59が半導体装置1と相違するのは、絶縁領域17を、異なる材料の膜からなる積層構造にした点である。絶縁領域17は、第2半導体領域11と接する上層が、エピタキシャル成長の際に不活性であるシリコン酸化膜等の絶縁膜であればよい。したがって、上層より下の層は、上層と異なる材料にすることができる。
図18は、変形例3に係る半導体装置63の部分断面図である。装置63が図1に示す半導体装置1と違う点は、トレンチの底面15が半導体基板5に到達しておらず、底面15が基板5の上方に位置していることである。これによる効果を説明する。
図1に示す第1実施形態は、トレンチ13に埋め込む半導体領域をp型の半導体領域にしているが、n型の半導体領域でもよい。これを変形例4で説明する。図19は、変形例4に係る半導体装置71の部分断面図であり、図1と対応する。変形例4では、これまでの例とは逆に第1導電型がp型で、第2導電型がn型となる。
図22は、第2実施形態に係る半導体装置81の部分断面図である。第1実施形態では、単結晶半導体層に複数のトレンチを形成し、この層の導電型と異なる導電型のエピタキシャル成長層を複数のトレンチに埋め込むことにより、スーパージャンクション構造を形成している。これに対して、第2実施形態では、n型の単結晶シリコン層をエピタキシャル成長法により形成し、この層にp型の不純物を選択的に注入し、この不純物を活性化する、という工程を必要回数(第2実施形態では6回)繰り返すことにより、スーパージャンクション構造を形成している。したがって、第2実施形態に係る半導体装置81は、n型の単結晶半導体層を含む複数の第1半導体領域9と、p型の単結晶半導体層を含む複数の第2半導体領域11と、を備え、複数の第1半導体領域9及び複数の第2半導体領域11の完全空乏化がオフ時に可能なように、第1半導体領域9及び第2半導体領域11が半導体基板5の表面7と平行な方向に周期的に配置されている、ということができる。
Claims (4)
- 第1導電型の半導体基板と、
前記半導体基板の裏面に接続されたドレイン電極と、
前記半導体基板の表面上に配置された第1導電型の単結晶半導体層に、複数のトレンチを設けることにより形成された複数の第1半導体領域と、
前記複数のトレンチの底面上にそれぞれ形成された複数の絶縁領域と、
前記複数の絶縁領域がそれぞれ形成された前記複数のトレンチに第2導電型のエピタキシャル成長層を埋め込むことにより形成された複数の第2半導体領域と、
前記第2半導体領域の上に形成された第2導電型のベース領域と、
前記ベース領域に形成された第1導電型のソース領域と、
前記ベース領域の上に形成されたゲート絶縁膜と、
このゲート絶縁膜を介して前記ベース領域の上に形成されたゲート電極と、
前記ソース領域及びベース領域に接続されたソース電極と、
を備え、
前記複数の第1半導体領域及び第2半導体領域が前記半導体基板の表面と平行な方向に交互に配置されている
ことを特徴とする半導体装置。 - 前記複数の絶縁領域は、異なる材料の膜からなる積層構造を有する
ことを特徴とする請求項1に記載の半導体装置。 - 第1導電型の半導体基板と、
前記半導体基板の表面上に配置された第1導電型の単結晶半導体層を含む複数の第1半導体領域と、
前記半導体基板の表面上に配置された第2導電型の単結晶半導体層を含む複数の第2半導体領域と、
前記複数の第2半導体領域の下部と前記半導体基板との間にそれぞれ設けられた複数の絶縁領域と、
前記第2半導体領域の上に形成された第2導電型のベース領域と、
前記ベース領域に形成された第1導電型のソース領域と、
前記ベース領域の上に形成されたゲート絶縁膜と、
このゲート絶縁膜を介して前記ベース領域の上に形成されたゲート電極と、
前記ソース領域及びベース領域に接続されたソース電極と、
を備え、
前記複数の第1半導体領域及び第2半導体領域が前記半導体基板の表面と平行な方向に交互に配置されている
ことを特徴とする半導体装置。 - 前記第2半導体領域の幅とその領域中の第2導電型の不純物濃度との積は、前記第1半導体領域の幅とその領域中の第1導電型の不純物濃度との積よりも大きい
ことを特徴とする請求項3に記載の半導体装置。
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JP2004201943A JP4068597B2 (ja) | 2004-07-08 | 2004-07-08 | 半導体装置 |
US11/146,129 US20060006458A1 (en) | 2004-07-08 | 2005-06-07 | Semiconductor device and method for manufacturing the same |
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JP2004201943A JP4068597B2 (ja) | 2004-07-08 | 2004-07-08 | 半導体装置 |
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JP2006024770A JP2006024770A (ja) | 2006-01-26 |
JP4068597B2 true JP4068597B2 (ja) | 2008-03-26 |
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JP (1) | JP4068597B2 (ja) |
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US7892924B1 (en) * | 2009-12-02 | 2011-02-22 | Alpha And Omega Semiconductor, Inc. | Method for making a charge balanced multi-nano shell drift region for superjunction semiconductor device |
CN102804386B (zh) * | 2010-01-29 | 2016-07-06 | 富士电机株式会社 | 半导体器件 |
US8772868B2 (en) | 2011-04-27 | 2014-07-08 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
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US8836028B2 (en) | 2011-04-27 | 2014-09-16 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
KR101904991B1 (ko) | 2011-05-25 | 2018-10-08 | 페어차일드코리아반도체 주식회사 | 슈퍼정션 반도체 소자 및 그 제조방법 |
JP5849894B2 (ja) * | 2011-12-01 | 2016-02-03 | 株式会社デンソー | 半導体装置 |
WO2013046544A1 (ja) * | 2011-09-27 | 2013-04-04 | 株式会社デンソー | 半導体装置 |
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CN103035493B (zh) * | 2012-06-15 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | 半导体器件的交替排列的p柱和n柱的形成方法 |
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JP6161903B2 (ja) * | 2013-01-21 | 2017-07-12 | ルネサスエレクトロニクス株式会社 | パワーmosfetの製造方法 |
EP2765611A3 (en) * | 2013-02-12 | 2014-12-03 | Seoul Semiconductor Co., Ltd. | Vertical gallium nitride transistors and methods of fabricating the same |
JP5918288B2 (ja) * | 2014-03-03 | 2016-05-18 | トヨタ自動車株式会社 | 半導体装置 |
JP6295797B2 (ja) * | 2014-04-10 | 2018-03-20 | 住友電気工業株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP6126150B2 (ja) * | 2015-03-06 | 2017-05-10 | トヨタ自動車株式会社 | 半導体装置 |
JP6441190B2 (ja) * | 2015-09-11 | 2018-12-19 | 株式会社東芝 | 半導体装置の製造方法 |
US11222962B2 (en) * | 2016-05-23 | 2022-01-11 | HUNTECK SEMICONDUCTOR (SHANGHAI) CO. Ltd. | Edge termination designs for super junction device |
CN105977308B (zh) * | 2016-06-21 | 2023-06-02 | 华润微电子(重庆)有限公司 | 超级势垒整流器器件及其制备方法 |
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US11056581B2 (en) * | 2017-08-21 | 2021-07-06 | Semiconductor Components Industries, Llc | Trench-gate insulated-gate bipolar transistors |
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DE102018106967B3 (de) * | 2018-03-23 | 2019-05-23 | Infineon Technologies Ag | SILIZIUMCARBID HALBLEITERBAUELEMENT und Halbleiterdiode |
CN113517193B (zh) * | 2021-04-06 | 2022-03-11 | 江苏新顺微电子股份有限公司 | 一种提高沟槽mos结构肖特基二极管性能的工艺方法 |
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JP4047384B2 (ja) * | 1996-02-05 | 2008-02-13 | シーメンス アクチエンゲゼルシヤフト | 電界効果により制御可能の半導体デバイス |
US5786769A (en) * | 1996-12-11 | 1998-07-28 | International Business Machines Corporation | Method and system for detecting the presence of adapter cards |
DE19854915C2 (de) * | 1998-11-27 | 2002-09-05 | Infineon Technologies Ag | MOS-Feldeffekttransistor mit Hilfselektrode |
FR2797094B1 (fr) * | 1999-07-28 | 2001-10-12 | St Microelectronics Sa | Procede de fabrication de composants unipolaires |
US6475864B1 (en) * | 1999-10-21 | 2002-11-05 | Fuji Electric Co., Ltd. | Method of manufacturing a super-junction semiconductor device with an conductivity type layer |
FR2830124B1 (fr) * | 2001-09-26 | 2005-03-04 | St Microelectronics Sa | Memoire vive |
GB0129450D0 (en) * | 2001-12-08 | 2002-01-30 | Koninkl Philips Electronics Nv | Trenched semiconductor devices and their manufacture |
JP2004342660A (ja) * | 2003-05-13 | 2004-12-02 | Toshiba Corp | 半導体装置及びその製造方法 |
US7276423B2 (en) * | 2003-12-05 | 2007-10-02 | International Rectifier Corporation | III-nitride device and method with variable epitaxial growth direction |
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