JP4966487B2 - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 137
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000010410 layer Substances 0.000 claims description 112
- 239000000758 substrate Substances 0.000 claims description 68
- 230000002265 prevention Effects 0.000 claims description 37
- 239000011241 protective layer Substances 0.000 claims description 28
- 239000010949 copper Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 238000009713 electroplating Methods 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 description 13
- 230000000694 effects Effects 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
Claims (13)
- 半導体基板と、前記半導体基板の表面に第1の絶縁膜を介して形成されたパッド電極と、前記半導体基板を貫通し前記パッド電極に到達するビアホールと、前記ビアホールの側壁及び半導体基板の裏面を覆う第2の絶縁膜と、前記ビアホールの中に形成され前記パッド電極と接続された貫通電極と、前記第2の絶縁膜上に形成された剥離防止層と、前記貫通電極、前記第2の絶縁膜及び前記剥離防止層を被覆する保護層と、を備え、
前記半導体基板の裏面に溝又は穴部が形成され、前記第2の絶縁膜及び前記剥離防止層の一部がこの溝又は穴部の中に配置されていることを特徴とする半導体装置。 - 前記剥離防止層は前記半導体基板のコーナー部に設けられたことを特徴とする請求項1に記載の半導体装置。
- 前記保護層が複数の島領域に分割されていることを特徴とする請求項1又は2に記載の半導体装置。
- 前記剥離防止層は少なくとも銅層を含むことを特徴とする請求項1、2、3のいずれか1項に記載の半導体装置。
- 半導体基板と、前記半導体基板の表面に第1の絶縁膜を介して形成されたパッド電極と、前記半導体基板を貫通し前記パッド電極に到達するビアホールと、前記ビアホールの側壁及び半導体基板の裏面を覆う第2の絶縁膜と、前記ビアホールの中に形成され前記パッド電極と接続された貫通電極と、前記貫通電極と接続され前記半導体基板の裏面の前記第2の絶縁膜上を延在する配線層と、前記第2の絶縁膜上に形成された剥離防止層と、前記貫通電極、前記第2の絶縁膜、前記配線層及び前記剥離防止層を被覆する保護層と、前記配線層上に形成された前記保護層の開口部を通して前記配線層に接続された導電端子と、を備え、前記半導体基板の裏面に溝又は穴部が形成され、前記第2の絶縁膜及び前記剥離防止層の一部がこの溝又は穴部の中に配置されていることを特徴とする半導体装置。
- 前記剥離防止層は前記半導体基板のコーナー部に設けられたことを特徴とする請求項5に記載の半導体装置。
- 前記保護層が複数の島領域に分割されていることを特徴とする請求項5又は6に記載の半導体装置。
- 前記剥離防止層は少なくとも銅層を含むことを特徴とする請求項5、6、7のいずれか1項に記載の半導体装置。
- その表面に第1の絶縁膜を介してパッド電極が形成された半導体基板を準備し、
前記パッド電極に対応する位置に前記半導体基板を貫通するビアホールを形成する工程と、
前記ビアホールの側壁及び前記半導体基板の裏面を被覆する第2の絶縁膜を形成する工程と、
前記ビアホールの中に前記パッド電極と接続された貫通電極及び、前記半導体基板の裏面上の前記第2の絶縁膜上の剥離防止層とを同時に形成する工程と、
前記貫通電極、前記第2の絶縁膜及び前記剥離防止層を被覆する保護層を形成する工程と、
前記ビアホールと同時に前記半導体基板の裏面に溝又は穴部をエッチングにより形成する工程とを備え、前記第2の絶縁膜及び前記剥離防止層の一部がこの溝又は穴部の中に形成されることを特徴とする半導体装置の製造方法。 - 前記貫通電極及び前記剥離防止層は電解メッキ法により形成されることを特徴とする請求項9に記載の半導体装置の製造方法。
- 前記剥離防止層は前記半導体基板のコーナー部に形成されることを特徴とする請求項9又は10に記載の半導体装置の製造方法。
- 前記保護層を複数の島領域に分割する工程を備えることを特徴とする請求項9、10、11のいずれか1項に記載の半導体装置の製造方法。
- 前記剥離防止層は少なくとも銅層を含むことを特徴とする請求項9、10、11、12のいずれか1項に記載の半導体装置の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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JP2004284794A JP4966487B2 (ja) | 2004-09-29 | 2004-09-29 | 半導体装置及びその製造方法 |
TW094129820A TWI305020B (en) | 2004-09-29 | 2005-08-31 | Semiconductor device and manufacturing process therefor |
KR1020050088565A KR100648122B1 (ko) | 2004-09-29 | 2005-09-23 | 반도체 장치 및 그 제조 방법 |
CNB2005101068638A CN100530609C (zh) | 2004-09-29 | 2005-09-26 | 半导体装置及其制造方法 |
US11/236,881 US7382037B2 (en) | 2004-09-29 | 2005-09-28 | Semiconductor device with a peeling prevention layer |
US12/109,800 US7906430B2 (en) | 2004-09-29 | 2008-04-25 | Method of manufacturing a semiconductor device with a peeling prevention layer |
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JP2004284794A JP4966487B2 (ja) | 2004-09-29 | 2004-09-29 | 半導体装置及びその製造方法 |
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JP2006100558A JP2006100558A (ja) | 2006-04-13 |
JP4966487B2 true JP4966487B2 (ja) | 2012-07-04 |
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US (2) | US7382037B2 (ja) |
JP (1) | JP4966487B2 (ja) |
KR (1) | KR100648122B1 (ja) |
CN (1) | CN100530609C (ja) |
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Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4675146B2 (ja) * | 2005-05-10 | 2011-04-20 | パナソニック株式会社 | 半導体装置 |
US7838997B2 (en) | 2005-06-14 | 2010-11-23 | John Trezza | Remote chip attachment |
US7560813B2 (en) | 2005-06-14 | 2009-07-14 | John Trezza | Chip-based thermo-stack |
US8456015B2 (en) | 2005-06-14 | 2013-06-04 | Cufer Asset Ltd. L.L.C. | Triaxial through-chip connection |
US7781886B2 (en) | 2005-06-14 | 2010-08-24 | John Trezza | Electronic chip contact structure |
US7687400B2 (en) | 2005-06-14 | 2010-03-30 | John Trezza | Side stacking apparatus and method |
US7215032B2 (en) | 2005-06-14 | 2007-05-08 | Cubic Wafer, Inc. | Triaxial through-chip connection |
US7786592B2 (en) | 2005-06-14 | 2010-08-31 | John Trezza | Chip capacitive coupling |
US7851348B2 (en) | 2005-06-14 | 2010-12-14 | Abhay Misra | Routingless chip architecture |
US8154131B2 (en) | 2005-06-14 | 2012-04-10 | Cufer Asset Ltd. L.L.C. | Profiled contact |
US8786092B2 (en) | 2005-06-17 | 2014-07-22 | Rohm Co., Ltd. | Semiconductor integrated circuit device |
JP2007311771A (ja) * | 2006-04-21 | 2007-11-29 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
US7687397B2 (en) * | 2006-06-06 | 2010-03-30 | John Trezza | Front-end processed wafer having through-chip connections |
JP4302720B2 (ja) * | 2006-06-28 | 2009-07-29 | 株式会社沖データ | 半導体装置、ledヘッド及び画像形成装置 |
US7670874B2 (en) | 2007-02-16 | 2010-03-02 | John Trezza | Plated pillar package formation |
CN102224579B (zh) * | 2008-11-25 | 2013-12-04 | 松下电器产业株式会社 | 半导体装置及电子设备 |
JP4659875B2 (ja) * | 2008-11-25 | 2011-03-30 | パナソニック株式会社 | 半導体装置 |
JP2010129952A (ja) * | 2008-12-01 | 2010-06-10 | Nippon Telegr & Teleph Corp <Ntt> | 貫通電極配線の製造方法 |
US8426938B2 (en) | 2009-02-16 | 2013-04-23 | Samsung Electronics Co., Ltd. | Image sensor and method of fabricating the same |
KR101571353B1 (ko) | 2009-02-16 | 2015-11-24 | 삼성전자 주식회사 | 이미지 센서 및 그의 제조 방법 |
US8264067B2 (en) * | 2009-10-09 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through silicon via (TSV) wire bond architecture |
US8399987B2 (en) * | 2009-12-04 | 2013-03-19 | Samsung Electronics Co., Ltd. | Microelectronic devices including conductive vias, conductive caps and variable thickness insulating layers |
US8207615B2 (en) * | 2010-01-20 | 2012-06-26 | Bai-Yao Lou | Chip package and method for fabricating the same |
US20110204517A1 (en) * | 2010-02-23 | 2011-08-25 | Qualcomm Incorporated | Semiconductor Device with Vias Having More Than One Material |
JP5352534B2 (ja) * | 2010-05-31 | 2013-11-27 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US8896136B2 (en) * | 2010-06-30 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment mark and method of formation |
JP5700502B2 (ja) * | 2010-07-28 | 2015-04-15 | 住友電工デバイス・イノベーション株式会社 | 半導体装置及び製造方法 |
WO2012084047A1 (en) * | 2010-12-23 | 2012-06-28 | Replisaurus Group Sas | An ecpr master electrode and a method for providing such ecpr master electrode |
JP5360134B2 (ja) * | 2011-06-01 | 2013-12-04 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US8546900B2 (en) * | 2011-06-09 | 2013-10-01 | Optiz, Inc. | 3D integration microelectronic assembly for integrated circuit devices |
US20140151095A1 (en) * | 2012-12-05 | 2014-06-05 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board and method for manufacturing the same |
US9716066B2 (en) | 2013-06-29 | 2017-07-25 | Intel Corporation | Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias |
CN103367139B (zh) * | 2013-07-11 | 2016-08-24 | 华进半导体封装先导技术研发中心有限公司 | 一种tsv孔底部介质层刻蚀方法 |
CN104617036B (zh) * | 2015-01-14 | 2018-07-27 | 华天科技(昆山)电子有限公司 | 晶圆级芯片尺寸封装中通孔互连的制作方法 |
JP6443362B2 (ja) * | 2016-03-03 | 2018-12-26 | 株式会社デンソー | 半導体装置 |
KR102619817B1 (ko) * | 2022-05-19 | 2024-01-02 | 세메스 주식회사 | 반도체 소자의 형성 방법 및 반도체 소자의 형성을 위한 기판 처리 시스템 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59163841A (ja) * | 1983-03-08 | 1984-09-14 | Toshiba Corp | 樹脂封止型半導体装置 |
JPS61269333A (ja) * | 1985-05-24 | 1986-11-28 | Hitachi Ltd | 半導体装置 |
US5399898A (en) * | 1992-07-17 | 1995-03-21 | Lsi Logic Corporation | Multi-chip semiconductor arrangements using flip chip dies |
JP2541028Y2 (ja) * | 1989-11-17 | 1997-07-09 | ソニー株式会社 | 半導体装置 |
US5229647A (en) * | 1991-03-27 | 1993-07-20 | Micron Technology, Inc. | High density data storage using stacked wafers |
US5561082A (en) * | 1992-07-31 | 1996-10-01 | Kabushiki Kaisha Toshiba | Method for forming an electrode and/or wiring layer by reducing copper oxide or silver oxide |
US5432999A (en) * | 1992-08-20 | 1995-07-18 | Capps; David F. | Integrated circuit lamination process |
US5424245A (en) * | 1994-01-04 | 1995-06-13 | Motorola, Inc. | Method of forming vias through two-sided substrate |
US5814889A (en) * | 1995-06-05 | 1998-09-29 | Harris Corporation | Intergrated circuit with coaxial isolation and method |
US5973396A (en) * | 1996-02-16 | 1999-10-26 | Micron Technology, Inc. | Surface mount IC using silicon vias in an area array format or same size as die array |
US6809421B1 (en) * | 1996-12-02 | 2004-10-26 | Kabushiki Kaisha Toshiba | Multichip semiconductor device, chip therefor and method of formation thereof |
US5915167A (en) * | 1997-04-04 | 1999-06-22 | Elm Technology Corporation | Three dimensional structure memory |
JPH1167755A (ja) * | 1997-08-21 | 1999-03-09 | Seiko Epson Corp | 半導体の構造 |
EP0926723B1 (en) * | 1997-11-26 | 2007-01-17 | STMicroelectronics S.r.l. | Process for forming front-back through contacts in micro-integrated electronic devices |
US6833613B1 (en) * | 1997-12-18 | 2004-12-21 | Micron Technology, Inc. | Stacked semiconductor package having laser machined contacts |
DE19853703A1 (de) * | 1998-11-20 | 2000-05-25 | Giesecke & Devrient Gmbh | Verfahren zur Herstellung eines beidseitig prozessierten integrierten Schaltkreises |
JP2001168093A (ja) * | 1999-12-09 | 2001-06-22 | Sharp Corp | 半導体装置 |
US6710446B2 (en) * | 1999-12-30 | 2004-03-23 | Renesas Technology Corporation | Semiconductor device comprising stress relaxation layers and method for manufacturing the same |
JP3879816B2 (ja) * | 2000-06-02 | 2007-02-14 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器 |
JP3530149B2 (ja) * | 2001-05-21 | 2004-05-24 | 新光電気工業株式会社 | 配線基板の製造方法及び半導体装置 |
US6848177B2 (en) * | 2002-03-28 | 2005-02-01 | Intel Corporation | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
JP4212293B2 (ja) * | 2002-04-15 | 2009-01-21 | 三洋電機株式会社 | 半導体装置の製造方法 |
TWI229435B (en) * | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
TWI227050B (en) * | 2002-10-11 | 2005-01-21 | Sanyo Electric Co | Semiconductor device and method for manufacturing the same |
JP4397583B2 (ja) * | 2002-12-24 | 2010-01-13 | 株式会社フジクラ | 半導体装置 |
US6833323B2 (en) * | 2003-01-29 | 2004-12-21 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming patterned features at a semiconductor wafer periphery to prevent metal peeling |
JP3800335B2 (ja) * | 2003-04-16 | 2006-07-26 | セイコーエプソン株式会社 | 光デバイス、光モジュール、半導体装置及び電子機器 |
JP4248928B2 (ja) * | 2003-05-13 | 2009-04-02 | ローム株式会社 | 半導体チップの製造方法、半導体装置の製造方法、半導体チップ、および半導体装置 |
JP4467318B2 (ja) * | 2004-01-28 | 2010-05-26 | Necエレクトロニクス株式会社 | 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法 |
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TW200629442A (en) | 2006-08-16 |
US20080254618A1 (en) | 2008-10-16 |
US7382037B2 (en) | 2008-06-03 |
KR20060051564A (ko) | 2006-05-19 |
JP2006100558A (ja) | 2006-04-13 |
TWI305020B (en) | 2009-01-01 |
CN100530609C (zh) | 2009-08-19 |
US7906430B2 (en) | 2011-03-15 |
US20060071342A1 (en) | 2006-04-06 |
CN1755916A (zh) | 2006-04-05 |
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