JP3986575B2 - ３次元集積回路の製造方法 - Google Patents

３次元集積回路の製造方法 Download PDF

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JP3986575B2
JP3986575B2 JP24473295A JP24473295A JP3986575B2 JP 3986575 B2 JP3986575 B2 JP 3986575B2 JP 24473295 A JP24473295 A JP 24473295A JP 24473295 A JP24473295 A JP 24473295A JP 3986575 B2 JP3986575 B2 JP 3986575B2
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ラム ペーター
ブッフネル ラインホールドゥ
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フラウンホッファー−ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー．ファオ
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Description

【０００１】
【発明の属する技術分野】
本発明は３次元集積回路の製造方法に関するものである。３次元の集積とは、プレーナ技術により製造された部品の垂直方向の結合である。３次元に集積されたマイクロエレクトロニクスのシステムの利点は、特に、２次元のシステムと比べ、同じデザイン設計で到達可能な高い実装密度とスイッチング速度である。後者は一方では個々の部品あるいは回路間のより短い経路により、他方ではパラレルな情報処理の可能性により生じる。場所が自由に選択できる高度に集積された垂直方向の接点による結合技術の実現のため、システムの機能能力を向上させなければならない。
【０００２】
【従来の技術】
自由に選択可能な垂直方向の接点による３次元の回路を作るために以下の方法が周知である。
【０００３】
Ｙ．Ａｋａｓａｋａ，Ｐｒｏｃ．ＩＥＥＥ７４（１９８６）１７０３には、多結晶のシリコンのプロセス化の完了した部品層を分離し、再結晶化させ、その結果再結晶化した層中で他の部品を製造することが提案されている。この方法の欠点は、再結晶化プロセスでの高い熱負荷による下の面中の部品の性能を劣化させる変質と、全てのシステムのシリアルなプロセス化が必須なことである。後者は一方では、製造における長い走行時間により、他方ではプロセスにより引き起こされる沈殿の合計による作用の低下によるものである。両者は、互いに分離する個々の面の様々な基層中のプロセス化と比べて、製造コストを著しく上昇させてしまう。
【０００４】
Y.Hayashi その他による、Proc.8th Int.Workshop on Future Elerctron Devices,1990,p.85 により、始めに互いに分離した個々の部品を様々な基層中で製造することが知られている。続いて基層は数ミクロンに薄くされ、前側および後側の接点を備え、接着により垂直方向に結合される。
【０００５】
しかし前側および後側の接点を作るために、標準の半導体製造（ＣＭＯＳ）にはない特別なプロセスが必要である。ＭＯＳと適合性のない材料（例えば金）と基層の裏側の構造決めが必要でない。
【０００６】
ＵＳ４，９３９，５６８には、個々のチップを積み上げキャリア基層の上で１つの堆積チップとすることによる３次元集積回路の製造方法が開示されている。このために、まず始めに、プロセス化の完了した集積回路を持つ基層を個々のチップに分割し、それによりウエハ面上のプロセス化が終わる。チップはテストされ、最初の個々のチップは熱と圧縮によりキャリア基層にはりつけられる。このステップの後、他のチップが同じ方法で最初のチップの上にはりつけられる。このようにして、他のチップ堆積の製造をを他のキャリア基層の上で始める前に、最初のチップ堆積が行われる。このため、ウエハ面上のチップ堆積のさらなるプロセス化はこの方法では不可能である。
【０００７】
今まで挙げた方法の基本的な欠点は、シリコン技術で使用できる装置がディスク形の基層、いわゆるウエハの処理（プロセス化）のみに基づくことから生じる。様々な基層、特に個々のチップのプロセス化は経験的な実験装置によってのみ可能であるが、要求される効果を伴う工業的製造には向かない。
【０００８】
ＵＳ４，９５４，８７５には個々のウエハの積み上げによる３次元の集積方法が開示されており、この場合、個々の部品面の結合は、特別に形成されたバイアホール介して行われる。
【０００９】
【発明が解決しようとする課題】
多数の同じ構成要素、いわゆるチップを含む基層のつなぎ合わせでは、個々の歩留まりの製品からの結果として生じる多層システムの歩留まりの問題が生じる。これにより、複数の部品面を持つシステムの歩留まりが算出でき、周知の方法であるＵＳ４，９５４，８７５では徹底的に歩留まりが減少する。個々の面の歩留まりが８０％である場合、１０の面から成る全システムでは１０％の歩留まりとなる。それによりこのようなシステムは不経済となり、この技術の使用はわずかな特別の使用フィールドに制限される。部品基層の性能はその際に回路と使用される製造プロセスの種類に依存する。例えば記憶装置の構成要素の製造で高い効果が達成されるが、一方マイクロプロセッサーのようなロジックの構成要素では、著しくわずかな効果しか達成されない。特にこのような回路の複数の種類がかさなりあうと、これにより全体としての効果は非常にわずかな効果を持つ回路の種類によって決まる。
【００１０】
本発明の課題は、通常の工業的な標準装置をウエーハの上で使用して、従来の周知の方法に比べて明らかな歩留まりを上昇させて製造コストを減少することができる３次元集積回路の製造方法を提供することにある。
【００１１】
【課題を解決するための手段】
前記課題は、本発明の請求項１の方法により解決される。方法の特別な形態は、本発明の従属請求項の対象である。
【００１２】
本発明による方法では、その都度、回路と金属被覆層を含む２つのプロセス化の完了した第１および第２の部品基層が、例えば接着層を介し互いに結合される。これにより接着層は付加的にパッシブな機能に影響し（請求項７）、表面を平坦化できる（請求項８）。この場合、上の部品基層はあらかじめ機能識別テストを受け、この機能識別テストにより部品基層の欠陥のないチップが選択される。続いてこの部品基層は裏側から薄くされ、個々のチップに分割されて解体される。その後、選択された完全なチップだけが、接着層を備えた下の部品基層（第１の部品基層）の上に互いに調整されてはり付けられ、これにより新しいチップ面が生成される。この方法により、新しくはり付けられたチップ面中で完全なチップしか含まないウエーハが準備される。
【００１３】
ここで、下の部品基層は既に複数の部品層を堆積部品の形で含んでいることもある。上の部品基層のチップは機能識別テストを受け（請求項２）、あるいは機能識別テストされ例えばマークされた欠陥チップを持つ既に機能識別テストされた部品基層が準備され使用される。上の部品基層には、最終的に薄くし分割する前に補助基層がはり付けられる。部品層の近くの上の部品基層を薄くする代わりに、ＳＯＩ基層の場合でも酸化物層の下方の基層領域を除去できる。
【００１４】
下の部品基層の上に個々のチップをはりつけたので、つながっている表面はもはや存在せず（チップ間の溝）、その結果、一定のプロセスステップ、特に写真平版型はもはや使用できない。このため、主として平坦化ステップが挿入される（請求項９）。
【００１５】
平坦化は様々な方法により遂行される。その際、最初に、例えばスピン−オングラス（Ｓｐｉｎ−ｏｎ−Ｇｌａｓ）あるいはＣＶＤ−酸化物のような絶縁層がはり付けられ、溝を充填する。続いて表面が平らにされ、これはエッチバック、機械的あるいは化学機械的研磨により行われる。
【００１６】
チップ面の上では実現不可能な他のプロセスは、平坦化プロセスの後に問題なく、あらかじめ選択されたチップを持つ基層で遂行される。
【００１７】
続いて例えば、既に個々の部品基層のプロセス化の際にチップ中に取り付けられ、下の部品基層の金属被覆層までエッチングされるバイアホール（請求項１０）を通り、上と下の回路面の金属被覆層の間ごとに電気的接続部材が作られる。その際、各々の個々のチップの上の構造決めのためのフォトマスクは調整構造によって別々に調整され、場合によってはありえる寸法の逸脱を個々のチップのはりつけにより調整し、高い調整精度が獲得される。
【００１８】
その後、部品平面中で更に機能識別テストされた機能能力があるチップを含む部品基層を、市販の製造装置で更に処理できる。
【００１９】
同じ方法で他の部品面もチップごとにはりつけられる（請求項３）。ここでは付属する基層を持つ今までに製造された堆積部品が新しい下の部品基層として役立つ。その際この方法では面の数は制限されない。更に個々の面だけでなく、既に複数の面から構成される堆積部分がチップごとにはりつけられる。
【００２０】
基層として、単結晶のシリコン基層、ＳＯＩ基層あるいは様々なテクノロジー群の基層、例えばIII-Ｖ−半導体が適している。
【００２１】
総じて、本発明の方法では、周知で既に使われている方法ステップしか使用されないので、新しいプロセスを開発する必要はない。
【００２２】
本発明によるこの方法によって、完全なチップのみがその都度その下にある部品基層の上にはりつけられる。これにより全てのシステムの効果の個々にプロセス化された基層への依存性が著しく減るという利点が生じる。部品基層のその都度個々の欠陥のあるチップを除去でき、その結果、全ての堆積部品が１つの欠陥層により使用不可能ということがなくなる。このため、本発明による方法により、３次元集積回路の製造での歩留まりは明らかに上昇し、製造コストは下がる。
【００２３】
【発明の実施の形態】
以下に本発明の実施の形態を図面に基づいて詳細に説明する。
【００２４】
図１に示すように、例えば単結晶のシリコンから成る第１の位部品基層１は、決められた回路図に従い配置される複数の通常同一のチップ２と、例えばＭＯＳトランジスターのような回路３と、通常アルミニウム、アルミ合金あるいは銅やタングステン等の金属からなる１つあるいは複数の金属被覆層４とを有している。
【００２５】
これらの金属被覆層４は、電気的絶縁のために、平坦化のためにホウ素あるいは燐を組み込むことのできる酸化物層５に囲まれている。最上の金属被覆層４は、その際に例えば酸化シリコン、窒化シリコンから構成されるパッシブ層６により覆われる。更に複数の面の正確なつなぎ合わせのために調整構造が挿入される（図１中では示されていない）。回路３の下方で部品基層１は例えば６２５μｍの厚さである。この部品基層１は、多層システムの下の基層である。
【００２６】
図２に示すように、第２の部品基層７も、同様に、決められた回路図に従って配置される通常同一の複数のチップ８と、例えばＭＯＳトランジスタのような回路９と、１つあるいは複数の金属被覆層１０とを有している。この第２の部品基層７は、基本的に第１の部品基層１と似た構造であるが、回路９の通常機能が異なる。更に、第２の部品基層７は、バイアホールを、後に電気的接触が第１の部品基層１の下にある回路に関して行われることになる箇所に備える。バイアホール１１は、回路９を持つ層の下方に到達する深さである。
【００２７】
前記第２の部品基層７の完成後、最上の金属被覆層１０のパッシブ層が一定の測定箇所で露出される。その後、第２の部品基層７の個々のチップ８は機能テストを受け、欠陥チップがインクジェット等によって特徴づけられる。続いて露出された測定箇所を再び覆うため、新たにパッシブ層がはりつけられる。
【００２８】
図３に示すように、第２の部品基層７の表面に平坦に、ポリイミドや感光性レジストのような有機的材料から成る接着層１２が形成される。この接着層１２は、典型的に１−２μｍの厚さで特に全体の表面の平坦化をもたらす。接着層１２の上に最終的に、例えばシリコンあるいはクオーツ・ウエハのような補助基層であるハンドリング基層１３が形成される。このハンドリング基層１３は、さらなるプロセスステップのための基層として使用され、さらなる処理の際部品基層７の表面を保護する。
【００２９】
この後、第２の部品基層７は、エッチングあるいは研磨により、裏側からバイアホール１１まで薄くされ、その結果回路９の下方の部品基層７の厚さは数ミクロンしかなく通常１−５μｍである。その際、第２の部品基層７における他の層の厚さは、含まれる回路の種類に依存して決められる。
【００３０】
図４に示すように、この段階でハンドリング基層１３を持つ第２の部品基層７は、個々のチップに分割される。これは、ここではエッチングプロセス、刃物あるいはレーザーによる切断により行われる。これに続いて、特徴づけられた機能能力がある完全なチップが、接着層１４を備えた第２の部品基層１に互いに調整されてはりつけられる。通常１−２μｍの厚さの接着層１４は、その際に全体の表面を平坦にすることができる。
【００３１】
続いてハンドリング基層１３が、例えばエッチングあるいは研磨により除去され、露出した接着層１２は通常酸素プラズマあるいは溶媒により除去される。チップのはりつけの後、第１の部品基層１の表面は、個々のチップ間に溝を持つ。層１５による平坦化プロセスによって、前記溝に層１５（充填層）が充填されて平らな表面が作られる。２つの部品面を持つ第１の部品基層１は、通常のシリコン基層と同様に標準テクノロジー装置により更に処理することができる。
【００３２】
図５に示すように、この後、最終的に、上の部品である第２の部品基層７の金属被覆層１０と、下の部品である第１の部品基層１の金属被覆層４との間に垂直な電気的接続部材１６が作られる。更に写真平版ステップにより、上の第２の部品基層７の金属被覆層１０のコンタクトホールと準備されたバイアホール１１が、下の部品基層１ｌの金属被覆層４までつながり、金属分離と構造決めにより電気的接続が実現される。最後に表面に分離のためにパッシブ層１７が形成される。電気的接続はいうまでもなく他の方法でも実現される。例えば、準備された前側および後側の接点による下の基層へのチップのはりつけにより既に実現される（説明：Ｙ．Ｈａｙａｓｈｉ他を参照）。
【図面の簡単な説明】
【図１】本発明における第１の部品基層を説明するための図である。
【図２】本発明における第２の部品基層を説明するための図である。
【図３】本発明における接着層と補助基層を有する第２の部品基層を説明するための図である。
【図４】本発明における第１の部品基層と第２の部品基層とを接合した状態を説明するための図である。
【図５】本発明における第１の部品基層と第２の部品基層とを接合した状態において電気的接続部材を作る方法を説明するための図である。
【符号の説明】
１ 第１の部品基層
２ チップ
３ 回路
４ 金属被覆層
５ 酸化物層
６ パッシブ層
７ 第２の部品基層
８ チップ
９ 回路
１０ 金属被覆層
１１ バイアホール
１２ 接着層
１３ ハンドリング基層（補助基層）
１４ 接着層

Claims (9)

  1. 複数の独立したデバイスを有する第１デバイス層を備えた第１の基板を用意する第１のステップと、
    複数の独立したデバイスを有する第２デバイス層を備え、前記第２デバイス層を貫通するバイアホールを有する第２の基板を用意する第２のステップと、
    前記第２のデバイス層に含まれるデバイスを、機能するものと機能しないものとに区別するテストをする第３のステップと、
    前記第２の基板（７）の前記第２デバイス層側に、補助基板（１３）を接合する第４のステップと、
    前記第２の基板（７）の厚さを、前記第２デバイス層の反対側から前記バイアホールに至るまで薄くする第５のステップと、
    前記補助基板（１３）を含む前記第２のデバイス層を、前記第３のステップによって区別された機能するものと機能しないもののそれぞれの複数のチップへ分割する第６のステップと、
    前記第６のステップによって分割されたうちの機能するチップを、前記第１の基板（１）に並べてはりつける第７のステップと、
    前記第７のステップにおいて前記第１の基板（１）にはりつけられた前記チップから、前記補助基板（１３）を除去する第８のステップと、
    前記第７のステップにおいて前記第１の基板（１）にはりつけられた前記チップに含まれるデバイスと、前記第１デバイス層に含まれるデバイスとの間を、前記バイアホールを介して電気的に接続する第９のステップと
    を有することを特徴とする３次元集積回路の製造方法。
  2. 請求項１に記載の３次元集積回路の製造方法において、前記第２のステップから前記第９のステップを繰り返し、実行することによりつくられた基板が、前記第１の基板として使用されることを特徴とする３次元集積回路の製造方法。
  3. 請求項１または２に記載の３次元集積回路の製造方法において、前記補助基板（１３）が接着層（１２）を介して前記第２の基板（７）と結合されることを特徴とする３次元集積回路の製造方法。
  4. 請求項１から３のいずれかに記載の３次元集積回路の製造方法において、前記チップが接着層（１４）によって前記第１の基板（１）にはりつけられることを特徴とする３次元集積回路の製造方法。
  5. 請求項４に記載の３次元集積回路の製造方法において、前記接着層（１４）を保護層として使用することを特徴とする３次元集積回路の製造方法。
  6. 請求項４または５に記載の３次元集積回路の製造方法において、前記接着層（１４）を使用して表面を平坦にすることを特徴とする３次元集積回路の製造方法。
  7. 請求項１から６のいずれかに記載の３次元集積回路の製造方法において、前記第８のステップで、前記補助基板（１３）を除去した後のチップ間に形成された溝に、充填層を充填して表面を平坦にすることを特徴とする３次元集積回路の製造方法。
  8. 請求項１から７のいずれかに記載の３次元集積回路の製造方法において、前記第５のステップは、前記第２の基板（７）をエッチングあるいは研磨により薄くする工程を有することを特徴とする３次元集積回路の製造方法。
  9. 請求項１から８のいずれかに記載の３次元集積回路の製造方法において、ＳＯＩ基層が前記第２の基板（７）として使用されることを特徴とする３次元集積回路の製造方法。
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EP0703618A1 (de) 1996-03-27
US5563084A (en) 1996-10-08

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